JP2009225096A - Photocurrent-voltage conversion circuit - Google Patents

Photocurrent-voltage conversion circuit Download PDF

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JP2009225096A
JP2009225096A JP2008067256A JP2008067256A JP2009225096A JP 2009225096 A JP2009225096 A JP 2009225096A JP 2008067256 A JP2008067256 A JP 2008067256A JP 2008067256 A JP2008067256 A JP 2008067256A JP 2009225096 A JP2009225096 A JP 2009225096A
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circuit
photocurrent
transistor
frequency
voltage conversion
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JP4807369B2 (en
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Keita Miyaji
慶太 宮地
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TDK Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To specify a cut-off frequency on the higher frequency side while maintaining a gain. <P>SOLUTION: This photocurrent-voltage conversion circuit includes: a differential amplifier circuit 2 having a transistor pair TP constituted of a first transistor 11 to the gate terminal of which reference voltage Vref is impressed and a second transistor 12 to the gate terminal the photodiode PD of which is connected, and which is differentially connected to the first transistor 11, and a buffer circuit 15 which outputs voltage Vd from the transistor pair TP as an output signal Vout; a feedback circuit 3 which feeds back the output signal Vout; and a serial circuit 31 constituted of resistance 31a (a resistance value R1) and a capacitor 31b (a capacity value C1) connected in serial between an input terminal of the buffer circuit 15 and the ground, and specified so that the frequency (1/(2×π×C1×R1)) becomes higher than the cut-off frequency of a transfer function of a photocurrent-voltage conversion circuit 1 without the serial circuit 31, and lower than a unity gain frequency of a transfer function of the differential amplifier circuit 2. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

本発明は、受光素子に発生する光電流を電圧に変換する光電流・電圧変換回路に関するものである。   The present invention relates to a photocurrent / voltage conversion circuit for converting a photocurrent generated in a light receiving element into a voltage.

この種の光電流・電圧変換回路として、下記特許文献１に開示された光電流・電圧変換回路（電流電圧変換回路）が知られている。この種の光電流・電圧変換回路５１の基本構成は、図３に示すように、差動増幅回路５２および帰還回路５３を備えている。この場合、差動増幅回路５２は、ベース（制御端子）に基準電圧Ｖｒｅｆが印加される第１トランジスタ５４およびベース端子（制御端子）にフォトダイオード（受光素子）ＰＤが接続されると共に第１トランジスタ５４に対して差動接続される第２トランジスタ５５で構成されるトランジスタ対ＴＰ、第１トランジスタ５４および第２トランジスタ５５の各エミッタ端子とグランドとの間に配設された定電流源５６、第１トランジスタ５４および第２トランジスタ５５のコレクタに接続された負荷（電流ミラー回路）５７、並びにエミッタフォロワ回路（電流増幅回路）で構成されたバッファ回路５８を備え、フォトダイオードＰＤの出力電流（光電流）Ｉｐを電圧に変換して、バッファ回路５８から出力信号Ｖｏｕｔとして出力する。   As this type of photocurrent / voltage conversion circuit, a photocurrent / voltage conversion circuit (current-voltage conversion circuit) disclosed in Patent Document 1 below is known. The basic configuration of this type of photocurrent / voltage conversion circuit 51 includes a differential amplifier circuit 52 and a feedback circuit 53, as shown in FIG. In this case, the differential amplifier circuit 52 includes a first transistor 54 to which a reference voltage Vref is applied to a base (control terminal), a photodiode (light receiving element) PD connected to the base terminal (control terminal), and a first transistor. 54, a transistor pair TP composed of a second transistor 55 differentially connected to the transistor 54, a constant current source 56 disposed between the emitter terminals of the first transistor 54 and the second transistor 55 and the ground, A load (current mirror circuit) 57 connected to the collectors of the first transistor 54 and the second transistor 55 and a buffer circuit 58 constituted by an emitter follower circuit (current amplification circuit) are provided, and an output current (photocurrent) of the photodiode PD ) Ip is converted into a voltage and output from the buffer circuit 58 as the output signal Vout.

この光電流・電圧変換回路５１に対して出力信号Ｖｏｕｔのカットオフ周波数ｆｃを規定する場合には、通常、図３に示すように、抵抗５３ａ（抵抗値Ｒ）とコンデンサ５３ｂ（容量値Ｃ）の並列回路で帰還回路５３を構成する。これにより、光電流・電圧変換回路５１のカットオフ周波数ｆｃは、ｆｃ＝１／（２×π×Ｃ×Ｒ）に規定されて、抵抗５３ａの抵抗値Ｒによって定まる光電流・電圧変換回路５１の電流−電圧変換のゲインについての周波数特性は図２において破線で示すようになる。
特開平１０−１３５７４７号公報（第２頁、第１，３図） When the cut-off frequency fc of the output signal Vout is defined for the photocurrent / voltage conversion circuit 51, a resistor 53a (resistance value R) and a capacitor 53b (capacitance value C) are usually provided as shown in FIG. The feedback circuit 53 is configured by the parallel circuit. Thereby, the cut-off frequency fc of the photocurrent / voltage conversion circuit 51 is defined as fc = 1 / (2 × π × C × R), and is determined by the resistance value R of the resistor 53a. The frequency characteristics of the current-voltage conversion gain are as shown by the broken line in FIG.
Japanese Patent Laid-Open No. 10-135747 (2nd page, FIGS. 1 and 3)

ところで、この光電流・電圧変換回路５１においてゲインを維持しつつカットオフ周波数ｆｃをより高域側に規定したいときには、コンデンサ５３ｂの容量値Ｃを小さくする方法が一般的である。ところが、コンデンサ５３ｂは位相補償の機能も有しているため、この位相補償の機能を維持しようとしたときに容量値Ｃを小さくできない場合がある。また、コンデンサ５３ｂの容量値Ｃを小さくするという方法以外の方法によって位相補償を行うことで、コンデンサ５３ｂの容量値Ｃを小さくし得る状態にできたとしても、半導体プロセス上、コンデンサ５３ｂのサイズが小さいために、十分な絶対値精度を確保した状態では容量値Ｃの小さいコンデンサ５３ｂを形成するのが困難である。したがって、帰還回路５３のコンデンサ５３ｂでカットオフ周波数ｆｃを規定する従来の光電流・電圧変換回路５１には、ゲインを維持しつつカットオフ周波数ｆｃを高周波側に規定するのが困難であるという解決すべき課題が存在している。   By the way, when it is desired to specify the cut-off frequency fc on the higher frequency side while maintaining the gain in the photocurrent / voltage conversion circuit 51, a method of reducing the capacitance value C of the capacitor 53b is generally used. However, since the capacitor 53b also has a phase compensation function, there are cases where the capacitance value C cannot be reduced when attempting to maintain this phase compensation function. Even if the phase compensation is performed by a method other than the method of reducing the capacitance value C of the capacitor 53b, even if the capacitance value C of the capacitor 53b can be reduced, the size of the capacitor 53b is reduced in the semiconductor process. Because of the small size, it is difficult to form the capacitor 53b having a small capacitance value C in a state where sufficient absolute value accuracy is ensured. Therefore, in the conventional photocurrent / voltage conversion circuit 51 in which the cutoff frequency fc is defined by the capacitor 53b of the feedback circuit 53, it is difficult to define the cutoff frequency fc on the high frequency side while maintaining the gain. There are issues to be addressed.

本発明は、かかる課題を解決すべくなされたものであり、ゲインを維持しつつカットオフ周波数をより高周波側に規定し得る光電流・電圧変換回路を提供することを主目的とする。   The present invention has been made to solve such a problem, and a main object of the present invention is to provide a photocurrent / voltage conversion circuit capable of prescribing a cutoff frequency to a higher frequency side while maintaining a gain.

上記目的を達成すべく本発明に係る光電流・電圧変換回路は、受光素子に流れる光電流を電圧に変換して出力する光電流・電圧変換回路であって、制御端子に基準電圧が印加された第１トランジスタと制御端子に前記受光素子が接続されると共に前記第１トランジスタと差動接続された第２トランジスタとで構成されるトランジスタ対、および入力端子に印加された当該トランジスタ対の出力電圧を出力するバッファ回路を有する差動増幅回路と、当該差動増幅回路の出力信号を前記第２トランジスタの前記制御端子に帰還させる帰還回路と、前記バッファ回路の前記入力端子と基準電位との間に直列に接続された抵抗およびコンデンサで構成される直列回路とを備え、前記抵抗および前記コンデンサは、その抵抗値をＲ１とし、かつその容量値をＣ１としたときに、１／（２×π×Ｃ１×Ｒ１）で表される周波数が前記直列回路のないときの伝達関数のカットオフ周波数よりも高く、かつ前記差動増幅回路の伝達関数についてのユニティゲイン周波数よりも低くなるように、当該抵抗値Ｒ１および当該容量値Ｃ１が規定されている。   In order to achieve the above object, a photocurrent / voltage conversion circuit according to the present invention is a photocurrent / voltage conversion circuit that converts a photocurrent flowing through a light receiving element into a voltage and outputs the voltage, and a reference voltage is applied to a control terminal. A transistor pair including the first transistor and the light receiving element connected to the control terminal and a second transistor differentially connected to the first transistor, and an output voltage of the transistor pair applied to the input terminal A differential amplifier circuit having a buffer circuit that outputs a signal, a feedback circuit that feeds back an output signal of the differential amplifier circuit to the control terminal of the second transistor, and between the input terminal of the buffer circuit and a reference potential And a series circuit composed of a resistor and a capacitor connected in series to each other, the resistor and the capacitor having a resistance value R1 and a capacity thereof. When the value is C1, the frequency represented by 1 / (2 × π × C1 × R1) is higher than the cutoff frequency of the transfer function when there is no series circuit, and the transmission of the differential amplifier circuit The resistance value R1 and the capacitance value C1 are defined so as to be lower than the unity gain frequency for the function.

本発明に係る光電流・電圧変換回路では、差動増幅回路を構成するトランジスタ対から出力される電圧を入力するバッファ回路の入力端子と基準電位との間に抵抗（抵抗値Ｒ１）およびコンデンサ（容量値Ｃ１）で構成される直列回路が接続されることにより、１／（２×π×Ｃ１×Ｒ１）で表される周波数が、直列回路のないときの伝達関数のカットオフ周波数よりも高く、かつ差動増幅回路の伝達関数についてのユニティゲイン周波数よりも低くなるように直列回路の抵抗値Ｒ１および容量値Ｃ１が規定されている。したがって、この光電流・電圧変換回路によれば、直列回路の存在しない構成と比較して、帰還回路に変更を加えることなく（つまり、抵抗値Ｒ１によって定まる電流−電圧変換のゲインを維持しつつ）、その伝達関数のカットオフ周波数をより高速側にシフトさせることができ、より周波数の高い光電流についても、正確に出力信号に変換して出力することができる。   In the photocurrent / voltage conversion circuit according to the present invention, a resistor (resistance value R1) and a capacitor (between the input terminal of the buffer circuit for inputting the voltage output from the transistor pair constituting the differential amplifier circuit and the reference potential) By connecting a series circuit composed of capacitance value C1), the frequency represented by 1 / (2 × π × C1 × R1) is higher than the cutoff frequency of the transfer function when there is no series circuit. In addition, the resistance value R1 and the capacitance value C1 of the series circuit are defined so as to be lower than the unity gain frequency of the transfer function of the differential amplifier circuit. Therefore, according to the photocurrent / voltage conversion circuit, the feedback circuit is not changed as compared with the configuration without the series circuit (that is, the gain of the current-voltage conversion determined by the resistance value R1 is maintained). ), The cutoff frequency of the transfer function can be shifted to a higher speed side, and a photocurrent having a higher frequency can be accurately converted into an output signal and output.

以下、本発明に係る光電流・電圧変換回路の最良の形態について、添付図面を参照して説明する。   Hereinafter, the best mode of a photocurrent / voltage conversion circuit according to the present invention will be described with reference to the accompanying drawings.

最初に、光電流・電圧変換回路１の構成について、図面を参照して説明する。   First, the configuration of the photocurrent / voltage conversion circuit 1 will be described with reference to the drawings.

図１に示す光電流・電圧変換回路１は、光情報媒体に対する再生動作を少なくとも実行する再生装置に使用される光ピックアップ用受光装置に組み込み可能に構成されている。具体的には、この光電流・電圧変換回路１は、同図に示すように、差動増幅回路２および帰還回路３を備え、一例としてフォトダイオード（受光素子）ＰＤと同一チップ（ウェハ）上に配設されて、フォトダイオードＰＤに流れる光電流Ｉｐを電流−電圧変換して出力信号Ｖｏｕｔとして回路外部に出力する。   The photocurrent / voltage conversion circuit 1 shown in FIG. 1 is configured to be incorporated in a light receiving device for an optical pickup used in a reproducing device that executes at least a reproducing operation on an optical information medium. Specifically, this photocurrent / voltage conversion circuit 1 includes a differential amplifier circuit 2 and a feedback circuit 3 as shown in the figure, and as an example, on the same chip (wafer) as the photodiode (light receiving element) PD. The photocurrent Ip flowing through the photodiode PD is subjected to current-voltage conversion and output as an output signal Vout to the outside of the circuit.

差動増幅回路２は、図１に示すように、第１トランジスタ１１および第２トランジスタ１２で構成されるトランジスタ対ＴＰと、定電流源１３と、カレントミラー回路１４と、バッファ回路１５と、抵抗３１ａおよびコンデンサ３１ｂで構成された直列回路３１とを備えている。この場合、トランジスタ対ＴＰ、定電流源１３、カレントミラー回路１４およびバッファ回路１５は、一般的な演算増幅器の主要な構成であるため、差動増幅回路２は演算増幅器として構成されている。   As shown in FIG. 1, the differential amplifier circuit 2 includes a transistor pair TP composed of a first transistor 11 and a second transistor 12, a constant current source 13, a current mirror circuit 14, a buffer circuit 15, a resistor And a series circuit 31 composed of a capacitor 31b. In this case, since the transistor pair TP, the constant current source 13, the current mirror circuit 14, and the buffer circuit 15 are main components of a general operational amplifier, the differential amplifier circuit 2 is configured as an operational amplifier.

具体的には、トランジスタ対ＴＰは、第１トランジスタ（一例としてｎ型ＭＯＳＦＥＴ）１１のゲート端子（制御端子）に基準電圧Ｖｒｅｆが印加され、第１トランジスタ１１と差動接続された第２トランジスタ１２（一例としてｎ型ＭＯＳＦＥＴ）のゲート端子（制御端子）にフォトダイオードＰＤが接続されて構成されている。定電流源１３は、このように差動接続された第１および第２トランジスタ１１，１２の各ソース端子（出力端子）とグランドとの間に配設されて、各トランジスタ１１，１２の各ソース端子から流出する電流の総和を一定の電流値に維持しつつその電流を基準電位（一例としてグランド）に流出させる。カレントミラー回路１４は、２つのトランジスタ（一例としてｐ型ＭＯＳＦＥＴ）１６，１７で構成されて、第１および第２トランジスタ１１，１２の各ドレイン端子（入力端子）と電源Ｖｃｃとの間に配設されている。また、本例では、一例として、基準電圧Ｖｒｅｆは、基準電源１８によって生成される。また、カレントミラー回路１４は、本例ではトランジスタ対ＴＰの能動負荷として使用されて、トランジスタ対ＴＰの増幅度を高める機能を有している。   Specifically, in the transistor pair TP, the reference voltage Vref is applied to the gate terminal (control terminal) of the first transistor (for example, n-type MOSFET) 11, and the second transistor 12 differentially connected to the first transistor 11. A photodiode PD is connected to the gate terminal (control terminal) of (an n-type MOSFET as an example). The constant current source 13 is disposed between the source terminals (output terminals) of the first and second transistors 11 and 12 that are differentially connected as described above and the ground. While maintaining the total sum of currents flowing out from the terminals at a constant current value, the currents are allowed to flow out to a reference potential (for example, ground). The current mirror circuit 14 is composed of two transistors (p-type MOSFETs as an example) 16 and 17, and is arranged between the drain terminals (input terminals) of the first and second transistors 11 and 12 and the power supply Vcc. Has been. In this example, as an example, the reference voltage Vref is generated by the reference power supply 18. In addition, the current mirror circuit 14 is used as an active load of the transistor pair TP in this example, and has a function of increasing the amplification degree of the transistor pair TP.

バッファ回路１５は、電源Ｖｃｃにドレイン端子（入力端子）が接続されると共に、第２トランジスタ１２のドレイン端子（入力端子）にゲート端子（制御端子）が接続された第３トランジスタ（一例としてｎ型ＭＯＳＦＥＴ）１９と、第３トランジスタ１９のソース端子（出力端子）とグランドとの間に配設された定電流源２０とを備え、いわゆるソースフォロワ回路で構成されている。この構成により、バッファ回路１５は、第２トランジスタ１２のドレイン端子に生成される電圧Ｖｄを低インピーダンスで出力信号Ｖｏｕｔとして出力する。   The buffer circuit 15 includes a third transistor (as an example, an n-type) having a drain terminal (input terminal) connected to the power supply Vcc and a gate terminal (control terminal) connected to the drain terminal (input terminal) of the second transistor 12. MOSFET) 19 and a constant current source 20 disposed between the source terminal (output terminal) of the third transistor 19 and the ground, and is configured by a so-called source follower circuit. With this configuration, the buffer circuit 15 outputs the voltage Vd generated at the drain terminal of the second transistor 12 as the output signal Vout with low impedance.

直列回路３１は、抵抗３１ａおよびコンデンサ３１ｂが直列に接続されて構成されて、バッファ回路１５の入力端子でもある第３トランジスタ１９のゲート端子とグランド（本発明における基準電位の一例）との間に接続されている。この場合、第３トランジスタ１９のゲート端子と電源Ｖｃｃとの間に直列回路３１を接続してもよい。また、この直列回路３１によって差動増幅回路２の伝達関数にはゼロ（伝達ゼロ）が挿入され、このゼロの周波数は、抵抗３１ａの抵抗値をＲ１とし、かつコンデンサ３１ｂの容量値をＣ１としたときに、ｆ１＝１／（２×π×Ｃ１×Ｒ１）で表される。本例では、このゼロの周波数ｆ１が帰還回路３の後述する抵抗３ａの抵抗値Ｒとコンデンサ３ｂの容量値Ｃとで規定される光電流・電圧変換回路１の伝達関数のカットオフ周波数、つまり直列回路３１のないときの光電流・電圧変換回路１の伝達関数のカットオフ周波数ｆｃ（＝１／（２×π×Ｃ×Ｒ））よりも高く、かつ差動増幅回路２の伝達関数（オープンループゲインの伝達関数）についてのユニティゲイン周波数（利得が１となる周波数）ｆ２よりも低くなるように、抵抗３１ａの抵抗値Ｒ１およびコンデンサ３１ｂの容量値Ｃ１が規定されている。   The series circuit 31 includes a resistor 31a and a capacitor 31b connected in series, and is connected between the gate terminal of the third transistor 19 that is also the input terminal of the buffer circuit 15 and the ground (an example of the reference potential in the present invention). It is connected. In this case, the series circuit 31 may be connected between the gate terminal of the third transistor 19 and the power supply Vcc. Also, zero (transfer zero) is inserted into the transfer function of the differential amplifier circuit 2 by the series circuit 31, and this zero frequency has the resistance value of the resistor 31a as R1 and the capacitance value of the capacitor 31b as C1. Is expressed by f1 = 1 / (2 × π × C1 × R1). In this example, this zero frequency f1 is a cutoff frequency of the transfer function of the photocurrent / voltage conversion circuit 1 defined by a resistance value R of a resistor 3a (to be described later) of the feedback circuit 3 and a capacitance value C of the capacitor 3b. The transfer function of the differential amplifier circuit 2 is higher than the cutoff frequency fc (= 1 / (2 × π × C × R)) of the transfer function of the photocurrent / voltage conversion circuit 1 without the series circuit 31. The resistance value R1 of the resistor 31a and the capacitance value C1 of the capacitor 31b are defined so as to be lower than the unity gain frequency (frequency at which the gain becomes 1) f2 for the transfer function of the open loop gain.

帰還回路３は、一例として互いに並列に接続された抵抗３ａ（抵抗値Ｒ）とコンデンサ３ｂ（容量値Ｃ）とで構成されている。また、帰還回路３は、その一端側が第３トランジスタ１９のソース端子（差動増幅回路２の出力端子でもある）に接続され、かつその他端側が第２トランジスタ１２のゲート端子（差動増幅回路２の入力端子でもある）に接続されている。   As an example, the feedback circuit 3 includes a resistor 3a (resistance value R) and a capacitor 3b (capacitance value C) connected in parallel to each other. The feedback circuit 3 has one end connected to the source terminal of the third transistor 19 (which is also the output terminal of the differential amplifier circuit 2) and the other end connected to the gate terminal of the second transistor 12 (the differential amplifier circuit 2). Is also connected to the input terminal.

次に、光電流・電圧変換回路１の動作について説明する。   Next, the operation of the photocurrent / voltage conversion circuit 1 will be described.

電源Ｖｃｃが供給され、かつフォトダイオードＰＤに光が照射されている状態において、フォトダイオードＰＤで発生する光電流Ｉｐは図１において一点鎖線で示す経路（第３トランジスタ１９のソース端子から、帰還回路３を経由して第２トランジスタ１２のゲート端子に至る経路）に流れて、差動増幅回路２は上記したように演算増幅器として作動している。このため、光電流・電圧変換回路１は、光電流Ｉｐを電圧信号である出力信号Ｖｏｕｔに変換して出力している。この場合、この光電流・電圧変換回路１の差動増幅回路２は、その伝達関数に直列回路３１によってゼロ（周波数ｆ１）が挿入されているため、光電流・電圧変換回路１全体のゲインについての周波数特性におけるカットオフ周波数は、図２において実線で示すように、直列回路３１のない構成のときのカットオフ周波数ｆｃ（＝１／（２×π×Ｃ×Ｒ）。破線で示されている周波数特性のカットオフ周波数）よりも、高域側にシフトしている。したがって、この光電流・電圧変換回路１では、より周波数の高い光電流Ｉｐについても、正確に出力信号Ｖｏｕｔに変換して出力される。   In a state where the power supply Vcc is supplied and light is irradiated to the photodiode PD, the photocurrent Ip generated in the photodiode PD is a path indicated by a one-dot chain line in FIG. 1 (from the source terminal of the third transistor 19 to the feedback circuit). 3, the differential amplifier circuit 2 operates as an operational amplifier as described above. For this reason, the photocurrent / voltage conversion circuit 1 converts the photocurrent Ip into an output signal Vout which is a voltage signal and outputs it. In this case, since the differential amplifier circuit 2 of the photocurrent / voltage conversion circuit 1 has a zero (frequency f1) inserted in its transfer function by the series circuit 31, the gain of the entire photocurrent / voltage conversion circuit 1 is determined. 2, the cutoff frequency fc (= 1 / (2.times..pi..times.C.times.R) in the configuration without the series circuit 31, as indicated by the solid line in FIG. It is shifted to the higher frequency side than the cutoff frequency of the frequency characteristics. Therefore, the photocurrent / voltage conversion circuit 1 accurately converts the photocurrent Ip having a higher frequency into the output signal Vout and outputs it.

このように、この光電流・電圧変換回路１では、差動増幅回路２を構成するトランジスタ対ＴＰから出力される電圧Ｖｄを入力するバッファ回路１５の入力端子（第３トランジスタ１９のゲート端子）とグランドとの間に抵抗３１ａ（抵抗値Ｒ１）およびコンデンサ３１ｂ（容量値Ｃ１）で構成される直列回路３１が接続されることにより、直列回路３１のないときの光電流・電圧変換回路１の伝達関数のカットオフ周波数ｆｃ（＝１／（２×π×Ｃ×Ｒ））よりも下限値が高く、かつ差動増幅回路２の伝達関数（オープンループゲインの伝達関数）についてのユニティゲイン周波数ｆ２よりも上限値が低い周波数帯域に含まれる周波数ｆ１（＝１／（２×π×Ｃ１×Ｒ１））のゼロが差動増幅回路２に挿入されている。   Thus, in the photocurrent / voltage conversion circuit 1, the input terminal of the buffer circuit 15 (the gate terminal of the third transistor 19) for inputting the voltage Vd output from the transistor pair TP constituting the differential amplifier circuit 2 and A series circuit 31 composed of a resistor 31a (resistance value R1) and a capacitor 31b (capacitance value C1) is connected between the ground and the ground, so that the photocurrent / voltage conversion circuit 1 is transmitted without the series circuit 31. The lower limit value is higher than the cut-off frequency fc (= 1 / (2 × π × C × R)) of the function, and the unity gain frequency f2 for the transfer function (open loop gain transfer function) of the differential amplifier circuit 2 The zero of the frequency f1 (= 1 / (2 × π × C1 × R1)) included in the frequency band having the lower upper limit value is inserted in the differential amplifier circuit 2.

したがって、この光電流・電圧変換回路１によれば、直列回路３１の存在しない構成と比較して、帰還回路３に変更を加えることなく（つまり、抵抗３ａの抵抗値Ｒ１によって定まる電流−電圧変換のゲインを維持しつつ）、光電流・電圧変換回路１の伝達関数のカットオフ周波数をより高速側にシフトさせることができ、より周波数の高い光電流Ｉｐについても、正確に出力信号Ｖｏｕｔに変換して出力することができる。   Therefore, according to this photocurrent / voltage conversion circuit 1, compared with the configuration in which the series circuit 31 does not exist, the current-voltage conversion determined by the resistance value R1 of the resistor 3a without changing the feedback circuit 3 (that is, the current-voltage conversion). The cutoff frequency of the transfer function of the photocurrent / voltage conversion circuit 1 can be shifted to a higher speed side, and the photocurrent Ip having a higher frequency can be accurately converted into the output signal Vout. Can be output.

なお、本発明は、上記の構成に限定されない。例えば、光電流・電圧変換回路１では、トランジスタ対ＴＰ、カレントミラー回路１４およびバッファ回路１５をＭＯＳＦＥＴで構成しているが、従来の光電流・電圧変換回路５１と同様にして、バイポーラトランジスタで構成することもできる。また、光電流・電圧変換回路１では、差動増幅回路２をトランジスタ対ＴＰと、定電流源１３と、カレントミラー回路１４と、バッファ回路１５とで構成したが、他の構成を採用した差動増幅回路においても、差動増幅を行う回路部分の後段であるバッファ回路１５の入力端子と基準電位（高周波的にグランド電位となるグランド電位または電源電位）との間に直列回路３１を接続することにより、直列回路３１によって伝達関数内に形成されるゼロの周波数を光電流・電圧変換回路１と同様にして上記の周波数帯域内に規定することができる。したがって、このように他の構成を採用した差動増幅回路においても、カットオフ周波数を高周波側にシフトさせることができる結果、より周波数の高い光電流Ｉｐについても、正確に出力信号Ｖｏｕｔに変換することができる。また、１つの抵抗３１ａと１つのコンデンサ３１ｂとを直列に接続して直列回路３１を構成した例について上記したが、差動増幅回路２の伝達関数に等価的にゼロを挿入できる構成であれば、この構成に限定されず、種々の回路構成を採用することができる。   In addition, this invention is not limited to said structure. For example, in the photocurrent / voltage conversion circuit 1, the transistor pair TP, the current mirror circuit 14, and the buffer circuit 15 are configured by MOSFETs, but are configured by bipolar transistors in the same manner as the conventional photocurrent / voltage conversion circuit 51. You can also In the photocurrent / voltage conversion circuit 1, the differential amplifier circuit 2 includes the transistor pair TP, the constant current source 13, the current mirror circuit 14, and the buffer circuit 15. Also in the dynamic amplifier circuit, the series circuit 31 is connected between the input terminal of the buffer circuit 15 that is the subsequent stage of the circuit portion that performs differential amplification and a reference potential (a ground potential or a power supply potential that becomes a ground potential in terms of high frequency). Thus, the zero frequency formed in the transfer function by the series circuit 31 can be defined in the above frequency band in the same manner as the photocurrent / voltage conversion circuit 1. Therefore, even in the differential amplifier circuit adopting another configuration as described above, the cut-off frequency can be shifted to the high frequency side. As a result, the photocurrent Ip having a higher frequency can be accurately converted to the output signal Vout. be able to. Further, the example in which the series circuit 31 is configured by connecting one resistor 31a and one capacitor 31b in series has been described above. However, as long as the transfer function of the differential amplifier circuit 2 can be equivalently inserted with zero, Without being limited to this configuration, various circuit configurations can be employed.

光電流・電圧変換回路１の回路図である。1 is a circuit diagram of a photocurrent / voltage conversion circuit 1. FIG. 光電流・電圧変換回路１および従来の光電流・電圧変換回路５１の各ゲインの周波数特性図である。It is a frequency characteristic diagram of each gain of the photocurrent / voltage conversion circuit 1 and the conventional photocurrent / voltage conversion circuit 51. 従来の光電流・電圧変換回路５１の回路図である。FIG. 6 is a circuit diagram of a conventional photocurrent / voltage conversion circuit 51.

符号の説明Explanation of symbols

１ 光電流・電圧変換回路
２ 差動増幅回路
３ 帰還回路
３１ 直列回路
３１ａ 抵抗
３１ｂ コンデンサ
Ｉｐ 光電流
１１ 第１トランジスタ
１２ 第２トランジスタ
ＰＤ フォトダイオード
ＴＰ トランジスタ対
Ｖｏｕｔ 出力信号 DESCRIPTION OF SYMBOLS 1 Photocurrent and voltage conversion circuit 2 Differential amplifier circuit 3 Feedback circuit 31 Series circuit 31a Resistance 31b Capacitor Ip Photocurrent 11 1st transistor 12 2nd transistor PD Photodiode TP transistor pair Vout Output signal

Claims (1)

受光素子に流れる光電流を電圧に変換して出力する光電流・電圧変換回路であって、
制御端子に基準電圧が印加された第１トランジスタと制御端子に前記受光素子が接続されると共に前記第１トランジスタと差動接続された第２トランジスタとで構成されるトランジスタ対、および入力端子に印加された当該トランジスタ対の出力電圧を出力するバッファ回路を有する差動増幅回路と、
当該差動増幅回路の出力信号を前記第２トランジスタの前記制御端子に帰還させる帰還回路と、
前記バッファ回路の前記入力端子と基準電位との間に直列に接続された抵抗およびコンデンサで構成される直列回路とを備え、
前記抵抗および前記コンデンサは、その抵抗値をＲ１とし、かつその容量値をＣ１としたときに、１／（２×π×Ｃ１×Ｒ１）で表される周波数が前記直列回路のないときの伝達関数のカットオフ周波数よりも高く、かつ前記差動増幅回路の伝達関数についてのユニティゲイン周波数よりも低くなるように、当該抵抗値Ｒ１および当該容量値Ｃ１が規定されている光電流・電圧変換回路。 A photocurrent / voltage conversion circuit that converts a photocurrent flowing through a light receiving element into a voltage and outputs the voltage.
A transistor pair composed of a first transistor having a reference voltage applied to the control terminal, the light receiving element connected to the control terminal and a second transistor differentially connected to the control terminal, and an input terminal A differential amplifier circuit having a buffer circuit for outputting the output voltage of the transistor pair,
A feedback circuit that feeds back an output signal of the differential amplifier circuit to the control terminal of the second transistor;
A series circuit composed of a resistor and a capacitor connected in series between the input terminal of the buffer circuit and a reference potential;
The resistor and the capacitor transmit when the frequency expressed by 1 / (2 × π × C1 × R1) does not exist in the series circuit when the resistance value is R1 and the capacitance value is C1. A photocurrent / voltage conversion circuit in which the resistance value R1 and the capacitance value C1 are defined so as to be higher than the cutoff frequency of the function and lower than the unity gain frequency of the transfer function of the differential amplifier circuit .
JP2008067256A 2008-03-17 2008-03-17 Photocurrent / voltage converter Expired - Fee Related JP4807369B2 (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9153708B2 (en) 2013-03-22 2015-10-06 Kabushiki Kaisha Toshiba Light receiving circuit and photocoupler
JP2021002734A (en) * 2019-06-21 2021-01-07 セイコーエプソン株式会社 Circuit device, oscillator, electronic device, and mobile body

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JPH03286605A (en) * 1990-04-02 1991-12-17 Matsushita Electric Ind Co Ltd Optical receiver circuit
JPH0417190A (en) * 1990-05-11 1992-01-21 Hitachi Ltd Semiconductor device
JP2003234623A (en) * 2002-02-12 2003-08-22 Sharp Corp Light receiving amplifier circuit and optical pickup using the same
JP2006345481A (en) * 2005-05-12 2006-12-21 Matsushita Electric Ind Co Ltd Amplifying apparatus and optical disk drive apparatus

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03286605A (en) * 1990-04-02 1991-12-17 Matsushita Electric Ind Co Ltd Optical receiver circuit
JPH0417190A (en) * 1990-05-11 1992-01-21 Hitachi Ltd Semiconductor device
JP2003234623A (en) * 2002-02-12 2003-08-22 Sharp Corp Light receiving amplifier circuit and optical pickup using the same
JP2006345481A (en) * 2005-05-12 2006-12-21 Matsushita Electric Ind Co Ltd Amplifying apparatus and optical disk drive apparatus

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9153708B2 (en) 2013-03-22 2015-10-06 Kabushiki Kaisha Toshiba Light receiving circuit and photocoupler
JP2021002734A (en) * 2019-06-21 2021-01-07 セイコーエプソン株式会社 Circuit device, oscillator, electronic device, and mobile body
JP7346930B2 (en) 2019-06-21 2023-09-20 セイコーエプソン株式会社 Circuit devices, oscillators, electronic equipment and mobile objects

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