JP3102490B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial applications]

The present invention relates to a voltage limiter for stepping down an external power supply voltage (hereinafter abbreviated as a power supply voltage) in a chip and applying a low voltage to a fine transistor in the chip. Abbreviated) can be obtained.

[Prior art]

2. Description of the Related Art In recent years, as the degree of integration of semiconductor integrated circuits has increased, reduction in breakdown voltage due to miniaturization of semiconductor elements has become a problem. This problem can be solved by lowering the power supply voltage of the semiconductor device, but this causes incompatibility of the voltage relationship with other devices. Therefore, a method has been proposed in which the power supply voltage applied from the outside is, for example, 5 V, which has been widely used in the past, and an internal voltage lower than that (for example, 3.3 V) is produced by the semiconductor device. JP-A-1-136361
Describes an example of applying this method to a DRAM (dynamic random access memory) and an example of a circuit (voltage limiter) for generating an internal voltage from a power supply voltage. FIG. 4 shows a drive circuit diagram of the voltage limiter disclosed in the above conventional example. In the figure, V _R is a reference voltage lower than the power supply voltage V _CC . Driving circuit is a circuit in which the voltage value to generate a large internal voltage V _L of the same driving capability as V _R, and the differential amplifier circuit A comprising MOS transistors Q ₁ to Q _5, the output MOS transistor Q ₆ and current constituted by the buffer circuit B comprising pulling MOS transistor Q _7. Of the two input terminals of the differential amplifier circuit A, V _R is connected to one, since the other V _L as the internal voltage of the chip is fed back, the circuit is the internal voltage V _L It operates so as to follow the reference voltage V _R. Driving capability of the voltage limiter is determined by the channel width of the output MOS transistor Q _6. Therefore,
If designing a channel width of Q ₆ to a size commensurate with the current consumption of the load, it is possible to supply the internal voltage V _L to the load circuit.

In the prior art as described above, the stability of the operation of the voltage limiter is not considered. Hereinafter, FIG.
This will be described with reference to FIG. FIG. 4 shows an example of a DRAM as a voltage limiter and a load circuit for the voltage limiter.
In which equivalently represents in a volume of 650pF C _L and constant 50mA current flow I _L. FIG. 5 shows the frequency characteristics of gain and phase of the circuit shown in FIG. The solid lines in the figure show the gain and phase-frequency characteristics of the entire drive circuit when no feedback is applied (open loop). The characteristics shown by the dashed line and the dashed line
It is the gain and the phase-frequency characteristics of the differential amplifier circuit A and the buffer circuit B shown in the figure, and the sum of the frequency characteristics of the differential amplifier circuit A and the buffer circuit B is the gain and the phase-frequency characteristic of the entire drive circuit. Become. Here, at a frequency (cutoff frequency) at which the gain is 1 (0 dB), a numerical value indicating how much the phase delay has a margin of 180 ° is the phase margin.
In this example, the gain of the differential amplifier circuit A and the buffer circuit B
Since the difference in the frequency characteristic band is only about one digit, even if the phase margin is positive, the margin is small (10 °) and the operation becomes unstable (the feedback amplifier oscillates if the phase margin is negative). . Generally, it is said that a stable operation requires a phase margin of 45 ° or more. Since the mission of the voltage limiter is to supply a stable internal voltage to the internal circuit, the voltage limiter must not oscillate or operate stably. As a countermeasure to this problem, as shown in FIG. 3, it puts the capacitance C _O in parallel with the load circuit, the buffer circuit B
In this case, there is a method of dropping the band of the gain-frequency characteristic and performing phase compensation. However, this compensation capacitance C _O requires a large capacitance of about 10,000 pF. FIG. 6 shows the frequency characteristics at this time. As can be seen from FIG.
The frequency characteristic band is about one digit lower than before the phase compensation, and the difference between the gain-frequency characteristic band of the differential amplifier circuit A and the buffer circuit B can be reduced to about two digits. With this phase compensation, a phase margin of 45 ° can be secured. Meanwhile, put the capacitor C _F to the output terminal of the differential amplifier circuit A as shown in FIG. 2, a method of phase compensation is also conceivable. However, such a voltage limiter that loads an internal circuit in a DRAM chip as described above also requires a compensation capacitance of about 10,000 pF. FIG. 7 shows gain and phase-frequency characteristics at this time. However, the phase compensation method shown in FIG. 2, C _F
Not only is large, but also it is difficult to stabilize the internal voltage in the chip against fluctuations in the power supply voltage. This is shown in FIG. Figure 9 shows the variation of the internal voltage V _L for high-frequency power source voltage fluctuation of the circuit of Figure 2.
As can be seen from FIG.
The internal voltage _VL in the chip output from the voltage limiter fluctuates greatly. This is presumably because in FIG. 7, the bandwidth of the gain-frequency characteristic of the differential amplifier circuit A is too low, and the differential amplifier circuit A cannot follow the high-frequency power supply voltage fluctuation. As described above, in order to guarantee stable operation, it is only necessary to secure a phase margin of 45 ° or more by phase guarantee, but since the capacitance value at this time needs to be as large as 10,000 pF or more, the internal It is not realistic to put this capacitance in the layout area. As a phase compensation technique in an operational amplifier, a P-channel for output forming a buffer stage is also a MOS as disclosed in JP-A-62-66708 and JP-A-1-93207.
It is known to provide a phase compensation circuit comprising a series circuit of a resistor and a capacitor between a drain and a gate electrode of a transistor. However, such a phase compensation technique sufficiently suppresses internal voltage fluctuation due to power supply voltage fluctuation. Difficult to do. As the cause, the present inventors think as follows. That is, the impedance of the phase compensating circuit decreases for a signal having a relatively high frequency such as that based on the power supply voltage fluctuation, and the phase compensating circuit short-circuits the gate and the drain of the output P-channel MOS transistor in an AC manner. Acts in the direction. Accordingly, the output P-channel MOS transistor operates like a so-called diode-connected MOS transistor in which the gate and the drain are short-circuited, and the impedance between the source and the drain drops to a low level. As a result, the output p-channel MOS transistor positively injects a power supply voltage fluctuation component into the output terminal of the buffer stage. An object of the present invention is to solve the above-mentioned problems and to provide a voltage limiter with stable operation.

[Means for Solving the Problems]

In order to solve the above problem, according to the present invention, a phase compensation circuit including a resistor and a capacitor connected in series is inserted into an output terminal of a differential amplifier circuit of a drive circuit constituting a voltage limiter.

[Action]

By connecting a phase compensation capacitor and a resistor in series with the output terminal of the differential amplifier circuit of the drive circuit that constitutes the voltage limiter, the compensation capacitance can be made extremely small and, even if the power supply voltage fluctuates, the internal capacity is stable. It has been found that a voltage can be supplied. Thereby, the phase compensation circuit in the voltage limiter can be integrated in the semiconductor device.

【Example】

FIG. 1 shows an embodiment of the present invention. Driver circuit including a voltage limiter, a differential amplifier circuit AMP including MOS transistors Q _A to Q _E, the output MOS transistor Q _F (channel width /
Constituted by the channel length = 3000 / 1.2) and a MOS transistor Q _G for current sink buffer circuit BF. V
_CC ′ is a power supply voltage, and _{１ 1} ′ is a signal for controlling an operation mode of the drive circuit. V _R ′ is a reference voltage for obtaining the internal voltage V _L ′ (the same voltage value as V _R ′). As a load circuit of the above driving circuit, taking a DRAM as an example, a circuit in a DRAM chip powered by an internal voltage V _L 'is connected to a capacitor C _L ' (650 pF) and a current source I
_It was equivalently represented by _L '(50 mA). R _C and C _C are a resistance (300Ω) and a capacitance (20 pF) for phase compensation. A feature of the present invention resides in that the phase compensation circuit is configured by adding not only a capacitor but also a resistor. FIG. 8 shows the frequency characteristics of gain and phase of the circuit shown in FIG. The solid lines in the figure show the gain and phase-frequency characteristics of the entire drive circuit when no feedback is applied. The characteristics shown by the broken line and the dashed line are the gain and the phase-frequency characteristics of the differential amplifier circuit AMP and the buffer circuit BF shown in FIG. 1, respectively. As shown in FIG. 8, when a capacitor and a resistor connected in series as shown in FIG. 1 are inserted as phase compensation, recovery around the phase as shown by 81 and 82 in FIG. phenomenon occurs, the gain of the entire driving circuit when not to apply feedback - by a cut-off frequency f _C of the gain of the frequency characteristic is 1 (0 dB), can regain the phase delay of the differential amplifier circuit AMP, thereby The phase margin is 45 °, and stable operation can be guaranteed. The value of the compensation capacitance at this time can be reduced by about three orders of magnitude as compared with the case of the compensation using only the capacitance shown in FIG. 2, so that the layout area of the phase compensation circuit can be extremely reduced. Fig. 10 shows the internal voltage for high-frequency power supply voltage fluctuation.
This shows the fluctuation of V _L ′. As can be seen from the figure, the voltage fluctuation of the internal voltage V _L ′ hardly occurs even with a high-frequency power supply voltage fluctuation. This is because, in the embodiment according to the present invention shown in FIG. 1, as shown in FIG.
It can be considered that since the band of the gain-frequency characteristic of P does not need to be lowered, the differential amplifier circuit AMP can follow a high-frequency power supply voltage fluctuation. As described above, when phase compensation is performed on the output side of the differential amplifier circuit AMP, the phase compensation capacitance can be reduced by about three digits by adding a resistor in series with the phase compensation capacitance. Further, even if the power supply voltage fluctuates at a high frequency, a stable internal voltage V _L ′ can be supplied. In the above embodiment, the values of R _C and C _C are not necessarily arbitrary. That is, the PMOS of the differential amplifier circuit AMP
The drain conductance of the transistor _{Q A} g dsA, NMOS
Transistor Q _C of the drain conductance g _DSC, the drain conductance of the output PMOS transistor Q _F of the buffer circuit and g _DSF, respectively _{r dsA ≡1 / g dsA, r} dsC ≡1 / g
_dsC, r _dsF ≡1 / g _dsF defined as, r _dsa and r _DSC is pole frequency (the difference between the differential amplifier circuit which is determined by the gate capacitance C _G of the output PMOS transistor Q _F of the resistance and the buffer circuit to be connected in parallel In the gain-frequency characteristics of the dynamic amplifying circuit, the frequency at which the gain decreases by -3 dB with respect to the value when the gain is low is expressed as f
_P1 ｛f _P1 ≒ 1 / (2π (r _dsA r _dsC / (r _dsA + r _dsC ))
C _G )｝, the pole frequency of the buffer circuit determined by r _dsF and the load capacitance C _L ′ is f _P2 ｛f _P2 ≒ 1 / (2πr _dsF C _L ′)｝, R _C ,
The zero frequency generated by the insertion of C _C is _defined as f _Z1 ｛f _Z1 = 1 /
(2πR _{C C C)},} and the frequency at which the gain of the entire drive circuit is 1 (0 dB) when not subjected to feedback to f _C, first, FIG. 9, as described in FIG. 10, the power supply voltage ( V _CC , V _CC ′)
It is desirable to _satisfy f _P2 <f _P1 from the viewpoint of stability against the fluctuation of (condition I). As can be seen by comparing FIGS. 5 and 8, R _C ,
Apparent pole frequency of differential amplifier circuit AMP by inserting _C
f _P1 ′ moves to the vicinity of f _P2 . Here, if f _P1 ′ <f _P2 , the bandwidth of the differential amplifier circuit AMP is reduced, and the operation speed is lower than that of the buffer circuit BF. Therefore, there is a problem in stability against fluctuations in the power supply voltage. Therefore, it is desirable that f _P2 <f _P1 ′ (condition II). On the other hand, as shown in FIG. 8, the zero point frequency f _Z1 is the inflection point of the gain-frequency characteristic of the differential amplifier circuit AMP after the phase compensation, and f _P1 ′ <f _Z1. The zero point frequency _fZ1 due to R _C and C _C input to the output terminal of AMP is f _P2 <f _Z1
(Condition II '). Furthermore, the recovery behavior around the phase shown in FIG. 8 is so occur in the vicinity of f _Z1, f _C <f _Z1 the gain of the whole driving circuit becomes to phase compensation at frequencies of 1 (0 dB) or less has no effect. Therefore, f _Z1 <f _C
(Condition III). When the above conditions are combined, it can be seen that it is appropriate that the mutual relationship between the respective frequencies is approximately f _P2 <f _Z1 <f _C. The gain at the zero point frequency f _Z1 of the characteristic of the differential amplifier circuit in FIG. 8 is determined by the parallel resistance of r _dsA , r _dsC and R _C , and R _C
Increases or decreases as the value of. On the other hand, the apparent pole frequency f _P1 ′ of the differential amplifier is _{represented by} the parallel resistance of r _dsA and r _dsC and C _C + C _G
｛F _P1 ′ ≒ 1 / (2π (r _dsA r _dsC / (r _dsA +
r _dsC )) (C _C + C _G ))｝, and decreases as C _C increases. now,
When determining an appropriate f _Z1 , if R _C is too small, C _C will increase and f _P1 ′ <f _P2 ,
Condition II above cannot be satisfied. Therefore, R _C is f
It is desirable to set _P1 'to a value that can be made larger than _fP2 as much as possible. In the embodiment of the present invention shown in FIG. 1, if the pole frequency f _P2 of the buffer circuit is ｛r _dsF ｛1 / g _dsF as described above, f _P1 ≒ 1 / (2πr _dsF C _L ′) ｝, PMOS transistor
A drain conductance g _DSF of Q _F determined by the load capacitance C _L '(impedance of NMOS transistor Q _G in FIG. 1 is sufficiently higher than the impedance of the PMOS transistor Q _F) is, in general, of the buffer circuit It is given by the product of the output impedance X ₂ load capacitance C _L '. Here, the capacitance used in the phase compensation circuit of FIG. 1 will be described. These capacitors need to have a considerably large capacitance and a small voltage dependency. FIG. 11 (a) shows one method of realizing this with a normal CMOS process. In the figure, 1 is a P-type semiconductor substrate, 2 is an N-type well, 3 is an N ⁺ diffusion layer, 4 is SiO ₂ for isolation,
5 is a gate insulating film and 6 is a gate electrode. The capacitance is formed between the gate electrode 6 and the substrate surface with the gate insulating film 5 interposed therebetween, similarly to a normal MOS capacitance. Since a thin gate insulating film is used as the capacitive insulating film, a feature is that a large capacitance can be obtained in a relatively small area. However, the difference from the MOS capacitance is that N
The threshold voltage is negative because of the well. This will be described with reference to FIG. The horizontal axis represents the voltage applied to the capacitor (positive on the gate electrode side), and the vertical axis represents the capacitance. The threshold voltage (flat band voltage) is the applied voltage V ₀ when the capacitance changes greatly, and V ₀ <0
It is. Therefore, as long as a voltage in one direction is applied so that the gate electrode side becomes positive, the capacitance is almost constant. When a bidirectional voltage can be applied, use two capacitors shown in FIG.
What is necessary is just to connect in parallel in the opposite direction as shown in FIG. The steps required to form the capacitor of this embodiment are well formation, isolation region formation, gate insulating film formation, gate electrode formation, diffusion layer formation, and wiring, and all of these steps are normal. This is a step included in the CMOS process. Therefore, as long as the semiconductor device is manufactured by a CMOS process, it is not necessary to add a special step to manufacture the capacitor. Also, depending on the semiconductor device to which the present invention is applied, a stacked capacitance may be used. For example, a DRAM using a stacked capacitance as a storage capacitance of a memory cell formed on the surface of a semiconductor substrate is such. In such a case, the stacked capacitance may be used as the phase compensation capacitance. For the DRAM using the stacked capacitance, see the IEE Journal of Solid State Circuits, SC No. 15
Vol. 4, No. 4, pp. 661 to 666, August 1980 (IEEE J
ournal of Solid-State Circuits, Vol.SC-22, No.
3, pp. 661-666, Aug. 1980).

【The invention's effect】

As described above, according to the present invention, the value of the phase compensation capacitance can be made extremely small. Further, a stable internal voltage can be supplied even if the power supply voltage fluctuates from the outside.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing one embodiment of the present invention, and FIGS.
FIG. 4 is a circuit diagram according to a conventional phase compensation method, FIG. 4 is a drive circuit diagram for explaining a conventional example, FIG. 5 is a gain characteristic diagram and a phase-frequency characteristic diagram of the circuit shown in FIG. FIG. 7 shows a gain characteristic diagram and a phase-frequency characteristic diagram of the circuit shown in FIG. 3, FIG. 7 shows a gain characteristic diagram and a phase-frequency characteristic diagram of the circuit shown in FIG. 2, and FIG. Gain characteristic diagram and phase-frequency characteristic diagram of the circuit of the embodiment of the present invention shown,
FIG. 9 is a diagram showing the variation of the internal voltage with respect to the variation of the high frequency power supply voltage of the circuit shown in FIG. 2, and FIG. 10 is the variation of the internal voltage with respect to the variation of the high frequency power supply voltage of the embodiment of the present invention shown in FIG. FIG. 11 is a schematic sectional view of the phase compensation capacitor shown in FIG. 1 realized by a normal CMOS process and a characteristic diagram showing the voltage dependence of the capacitor.

──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Hitoshi Tanaka 5-20-1, Josuihonmachi, Kodaira-shi, Tokyo Within Hitachi Ultra SSI Engineering Co., Ltd. (72) Inventor Jun Eto Tokyo 1-280 Higashi-Koigakubo, Kokubunji-shi, Hitachi, Ltd.Central Research Laboratory, Hitachi, Ltd. No. 280, Hitachi Central Research Laboratory Co., Ltd. (72) Inventor Kiyoo Ito 1-280, Higashi Koikekubo, Kokubunji-shi, Tokyo Within Hitachi Central Research Laboratory Co., Ltd. (56) References JP-A-1-136361 (JP, A) JP-A-62-143507 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H03F 3/45 H01L 27/108 G11C 11/407

Claims (6)

(57) [Claims] A buffer circuit for receiving an input signal at an input thereof; a feedback path having one end coupled to an output of the buffer circuit; and amplifying a difference between a reference voltage and a signal supplied via the feedback path. A semiconductor integrated circuit including a drive circuit including a differential amplifier circuit that outputs the input signal to be supplied to the buffer circuit to an output terminal thereof, and a load driven by the drive circuit. A circuit comprising a series connection of a resistor and a capacitor is added between an output terminal of the differential amplifier circuit and a reference potential point of the circuit, and a pole frequency determined by an output impedance of the buffer circuit is defined as fp2. Assuming that the zero frequency of a circuit composed of a series circuit of capacitors is fz1 and the frequency at which the gain of the entire drive circuit is 1 is fc, fp2 <fz1 <fc The semiconductor device characterized by comprising Te. 2. The semiconductor device according to claim 1, wherein said drive circuit and said load are formed by a CMOS process. 3. The differential amplifier circuit according to claim 2, wherein the sources of the differential amplifier circuits are connected in common, and one of the gates is supplied with the reference voltage and the other gate is supplied with the signal via the feedback path. One channel conductivity type first and second MOS transistors, and the first and second MOS transistors.
Of the first MOS transistor and the first
And third and fourth MOS transistors having a second channel conductivity type different from the channel conductivity type of the buffer circuit. The buffer circuit has a gate coupled to an output terminal of the differential amplifier circuit and a drain connected to the output terminal. A fifth MOS transistor of a second channel conductivity type coupled to an output terminal of the buffer circuit; and a sixth MOS transistor for current extraction provided on the drain side of the fifth MOS transistor. A semiconductor device characterized by the above-mentioned. 4. The semiconductor device according to claim 3, wherein said capacitor is formed of a capacitor formed on a semiconductor substrate with a capacitor insulating film having a relatively small thickness. 5. The semiconductor device according to claim 4, wherein said capacitor is formed on a well formed in a semiconductor substrate. 6. The circuit according to claim 4, wherein said load comprises a DRAM having a stacked capacitance as a storage capacitance of a memory cell, and said capacitance in a circuit comprising a series connection of said resistor and said capacitor is constituted by a laminated capacitance. Semiconductor device.