JPH04171811A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH04171811A
JPH04171811A JP29966090A JP29966090A JPH04171811A JP H04171811 A JPH04171811 A JP H04171811A JP 29966090 A JP29966090 A JP 29966090A JP 29966090 A JP29966090 A JP 29966090A JP H04171811 A JPH04171811 A JP H04171811A
Authority
JP
Japan
Prior art keywords
substrate
layer
gaas
semiconductor device
grown
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP29966090A
Other languages
Japanese (ja)
Inventor
Kumie Izumisawa
泉沢 久美恵
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Olympus Corp
Original Assignee
Olympus Optical Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Olympus Optical Co Ltd filed Critical Olympus Optical Co Ltd
Priority to JP29966090A priority Critical patent/JPH04171811A/en
Publication of JPH04171811A publication Critical patent/JPH04171811A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To obtain a semiconductor device having no bend but a flat upper surface on the surface of a grown layer by depositing the first semiconductor grown layer having a coefficient of thermal expansion larger than that of a semiconductor substrate on the substrate and the second grown layer having a coefficient of thermal expansion smaller than that of the first grown layer on the first grown layer. CONSTITUTION:After an Si substrate 11 is placed in an MOCVD device, the substrate 11 is subject to heat treatment in an arsine atmosphere. After the heat treatment, GaAs is grown on the substrate 11 by using trimethylgallium and arsine as a gaseous starting material and a GaAs layer 12 is epitaxially grown. After the layer 12 is formed, an SiO2 layer 13 is formed by using monosilane and O2. Accordingly, a semiconductor device which is extremely reduced in bend and has a substantially flat upper surface is obtained and a large-aperture GaAs substrate, integrated circuit of a GaAs semiconductor device and Si semiconductor device, or inexpensive, high-efficiency, and light- weight solar battery can easily be realized.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は互いに熱膨張係数の異なる半導体層を積層シ゛
てなる多層構造を有する半導体装置に関する。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor device having a multilayer structure in which semiconductor layers having different coefficients of thermal expansion are laminated.

(従来の技術) 81基板上にGaAsをエピタキシャル成長させた多層
構造のものは、Siの基板としての特徴と、GaAsの
電気的、光学的特性との組み合わせか可能となり、Ga
As大口径基板、GaAs半導体装置とSi半導体装置
との集積回路、あるいは安価で高効率、軽量な太陽電池
等の実現が可能であることなどから注目されている。
(Prior art) A multilayer structure in which GaAs is epitaxially grown on an 81 substrate can combine the characteristics of Si as a substrate with the electrical and optical characteristics of GaAs.
It is attracting attention because it enables the realization of large-diameter As substrates, integrated circuits of GaAs semiconductor devices and Si semiconductor devices, and inexpensive, highly efficient, and lightweight solar cells.

従来、81基板上にGaAsをエピタキシャル成長させ
る方法として、MOCVD法や、MBE法を用いた2段
階成長法が提案されている。この2段階成長法はGaA
sとSiとの格子不整合の問題を解決しようとするもの
で、ます900−1000℃で熱処理したSi基板の温
度を400−500℃に一旦下げ、GaAsを110−
50n成長させたのち、つづいて通常のGaAsの成長
温度に昇温し、GaAs膜の成長を再開するという方法
である。
Conventionally, a two-step growth method using MOCVD or MBE has been proposed as a method for epitaxially growing GaAs on an 81 substrate. This two-step growth method uses GaA
This is an attempt to solve the problem of lattice mismatch between GaAs and Si.
After 50 nm of growth, the temperature is raised to the normal GaAs growth temperature and the growth of the GaAs film is restarted.

しかし、GaAsの熱膨張係数は6.8 Xl0−6/
℃であり、これはSiの熱膨張係数、2.6 Xl0−
6/℃の約2.5倍である。そのため上述のような従来
の方法においては、Si基板をGaASの成長温度から
室温へ冷却した際、GaAs表面が第2図に示すように
凹面状に湾曲してしまう。なお、本図中、1はSi基板
であり、2はこのSi基板1上にエビタキンヤル成長さ
れたGaAs層である。
However, the thermal expansion coefficient of GaAs is 6.8 Xl0-6/
℃, which is the thermal expansion coefficient of Si, 2.6
It is about 2.5 times that of 6/°C. Therefore, in the conventional method as described above, when the Si substrate is cooled from the GaAS growth temperature to room temperature, the GaAs surface is curved into a concave shape as shown in FIG. Note that in this figure, 1 is a Si substrate, and 2 is a GaAs layer grown on the Si substrate 1 by an epitaxial growth.

この湾曲はSi基板1上のGaAs層2を大口径基板と
して用いて半導体装置を大量生産する工程において様々
な問題を生じさせる原因となる。
This curvature causes various problems in the process of mass producing semiconductor devices using the GaAs layer 2 on the Si substrate 1 as a large diameter substrate.

すなわち、この湾曲のため処理条件が同一であっても、
Si基板1上のGaAs層2上面の中央部と周辺部とて
は、異なった結果が生じてしまう。
In other words, due to this curvature, even if the processing conditions are the same,
Different results will be produced between the central part and the peripheral part of the upper surface of the GaAs layer 2 on the Si substrate 1.

たとえばフォトリソグラフィ工程において、照射光の焦
点を中央部に合わせると、周辺部における解像度が極端
に低下してしまう。
For example, in a photolithography process, if the irradiation light is focused on the center, the resolution at the periphery will be extremely reduced.

(発明が解決しようとする課題) 本発明は半導体基板上に該基板よりも大きい熱膨張係数
を有す、る別の半導体の成長層を堆積した多層構造を有
する半導体装置において、この成長層の上面に湾曲のな
い表面平坦な多層構造を有する半導体装置を提供するこ
とを目的とする。
(Problems to be Solved by the Invention) The present invention provides a semiconductor device having a multilayer structure in which a grown layer of another semiconductor having a coefficient of thermal expansion larger than that of the substrate is deposited on a semiconductor substrate. An object of the present invention is to provide a semiconductor device having a multilayer structure with a flat top surface and no curvature.

(課題を解決するための手段) 本発明は上記課題を解決するため、この大きい熱膨張係
数を有する半導体エピタキシャル成長層の上にさらにこ
れよりも小さい熱膨張係数を有する層を成長させるとい
う手段を講じた。
(Means for Solving the Problems) In order to solve the above problems, the present invention takes a step of growing a layer having a smaller coefficient of thermal expansion on the semiconductor epitaxial growth layer having a larger coefficient of thermal expansion. Ta.

すなわち、本発明は半導体基板上に該基板よりも大きい
熱膨張係数を有する半導体の第1の成長層を堆積し、つ
いてこの成長温度を保ったままの状態で、さらにその上
に該第1の成長層よりも小さい熱膨張係数を有する第2
の成長層を堆積した多層構造を有する半導体装置を提供
するものである。
That is, the present invention deposits a first growth layer of a semiconductor having a coefficient of thermal expansion larger than that of the substrate on a semiconductor substrate, and then, while maintaining this growth temperature, further deposits the first growth layer thereon. a second layer with a smaller coefficient of thermal expansion than the growth layer;
The present invention provides a semiconductor device having a multilayer structure in which grown layers are deposited.

(作用) 半導体基板上に該基板よりも大きい熱膨張係数を有する
半導体の第1の成長層を堆積し、さらにその上に該第1
の成長層よりも小さい熱膨張係数を有する第2の成長層
を堆積させたため、半導体基板と第1の成長層との間の
作用と、第1の成長層と第2の成長層との間の作用とが
互いに釣り合い、その結果得られる多層構造体はその上
面が従来のように湾曲せず平坦となる。
(Function) A first growth layer of a semiconductor having a coefficient of thermal expansion larger than that of the substrate is deposited on a semiconductor substrate, and the first growth layer is further deposited on the semiconductor substrate.
Since a second grown layer having a coefficient of thermal expansion smaller than that of the grown layer is deposited, the interaction between the semiconductor substrate and the first grown layer and the relationship between the first grown layer and the second grown layer are The effects of (1) and (2) are in balance with each other, and the resulting multilayer structure has a flat top surface that is not curved as in the conventional case.

(実施例) 以下、本発明を図示の実施例を参照して説明する。(Example) Hereinafter, the present invention will be explained with reference to illustrated embodiments.

まず、厚さ300μm、<011>方向に約5度オフカ
ットした(100)面のSi基板11にエツチングを施
したのち、MOCVD装置内にこの基板1を装填し、ア
ルシン(ASH3)雰囲気中、900℃で熱処理した。
First, a Si substrate 11 with a thickness of 300 μm and a (100) plane that is off-cut by about 5 degrees in the <011> direction is etched, and then this substrate 1 is loaded into an MOCVD apparatus and etched in an arsine (ASH3) atmosphere. Heat treatment was performed at 900°C.

つづいて原料ガスとしてトリメチルガリウム(T M 
G a )とアルシンを用い、400℃でGaAsを2
0nm成長させた。 ついで750℃に昇温し、GaA
s層12を2μmエピタキシャル成長させた。
Next, trimethyl gallium (TM
Using Ga) and arsine, GaAs is 2
It was grown to 0 nm. Then, the temperature was raised to 750°C, and GaA
The s-layer 12 was epitaxially grown to a thickness of 2 μm.

その後、温度を750℃に保ったまま、モノシラン(S
L’H4)と02を用い、1μmの5i02層13を形
成した。
After that, while keeping the temperature at 750℃, monosilane (S
A 1 μm 5i02 layer 13 was formed using L'H4) and 02.

こめようにして得られた3層構造の半導体装置の平面度
をフィゾー型レーザー干渉計により測定したところ、G
aAs層2 iの2層構造の場合と比較して、湾曲が著
しく低減され、実質的に平坦な上面が形成されているこ
とか判明した。
When the flatness of the resulting three-layer semiconductor device was measured using a Fizeau laser interferometer, it was found that G
It was found that the curvature was significantly reduced and a substantially flat top surface was formed compared to the case of the two-layer structure of the aAs layer 2i.

また、この3層構造体を半導体装置の基板として用いた
場合、8102層13は絶縁層等の一部としてそのまま
利用することもてきた。
Further, when this three-layer structure is used as a substrate of a semiconductor device, the 8102 layer 13 can be used as it is as a part of an insulating layer or the like.

(発明の効果) 以上詳述したように、本発明によれば半導体基板上に該
基板よりも大きい熱膨張係数を有する半導体の第1の成
長層を堆積したのち、さらにその上に該第1の成長層よ
りも小さい熱膨張係数を有する第2の成長層を堆積する
ようにしたから、成長層の上面に湾曲のない上面平坦な
半導体装置を提供することができる。したがって、Ga
As大口径基板、GaAs半導体装置とSt半導体装置
との集積回路、あるいは安価で高効率、軽量な太陽電池
等の実現が容易に可能となる。
(Effects of the Invention) As described in detail above, according to the present invention, after depositing a first growth layer of a semiconductor having a coefficient of thermal expansion larger than that of the substrate on a semiconductor substrate, the first Since the second growth layer having a coefficient of thermal expansion smaller than that of the growth layer is deposited, it is possible to provide a semiconductor device with a flat top surface without any curvature on the top surface of the growth layer. Therefore, Ga
It becomes possible to easily realize As large diameter substrates, integrated circuits of GaAs semiconductor devices and St semiconductor devices, inexpensive, highly efficient, lightweight solar cells, and the like.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明に係わる半導体装置の斜視図、第2図は
従来の半導体装置の斜視図である。 図中、1・・・Si基板、2・・・GaAs層、11・
=Si基板、12・・・GaAs層、13・・・5i0
2層。
FIG. 1 is a perspective view of a semiconductor device according to the present invention, and FIG. 2 is a perspective view of a conventional semiconductor device. In the figure, 1...Si substrate, 2...GaAs layer, 11...
=Si substrate, 12...GaAs layer, 13...5i0
2 layers.

Claims (3)

【特許請求の範囲】[Claims] (1)半導体基板上に該基板よりも大きい熱膨張係数を
有する半導体の第1の成長層を堆積し、さらにその上に
該第1の成長層よりも小さい熱膨張係数を有する第2の
成長層を堆積した多層構造を有する半導体装置。
(1) Depositing a first growth layer of a semiconductor having a coefficient of thermal expansion larger than that of the substrate on a semiconductor substrate, and further growing a second growth layer thereon having a coefficient of thermal expansion smaller than the first growth layer. A semiconductor device having a multilayer structure in which layers are deposited.
(2)該半導体基板がSiであり、第1の成長層がGa
Asであり、第2の成長層がSiO_2である請求項1
記載の半導体装置。
(2) The semiconductor substrate is Si, and the first growth layer is Ga.
Claim 1: As, and the second growth layer is SiO_2.
The semiconductor device described.
(3)請求項1または2に記載の多層構造を複合基板と
して用いてなる半導体装置。
(3) A semiconductor device using the multilayer structure according to claim 1 or 2 as a composite substrate.
JP29966090A 1990-11-05 1990-11-05 Semiconductor device Pending JPH04171811A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP29966090A JPH04171811A (en) 1990-11-05 1990-11-05 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP29966090A JPH04171811A (en) 1990-11-05 1990-11-05 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH04171811A true JPH04171811A (en) 1992-06-19

Family

ID=17875434

Family Applications (1)

Application Number Title Priority Date Filing Date
JP29966090A Pending JPH04171811A (en) 1990-11-05 1990-11-05 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH04171811A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006523960A (en) * 2003-04-18 2006-10-19 レイセオン・カンパニー Method for processing a device structure having an attached wafer structure on a composite substrate having a matched coefficient of thermal expansion

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006523960A (en) * 2003-04-18 2006-10-19 レイセオン・カンパニー Method for processing a device structure having an attached wafer structure on a composite substrate having a matched coefficient of thermal expansion

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