JPH04170822A - Digital modulating system - Google Patents

Abstract

PURPOSE:To make the ratio of a maximum and a minimum inversion intervals in a DC-free code small by preventing the occurrence of level transition at the center of a bit in respect of final two bits among levels '1' existing continuously in an even number, and simultaneously, causing the level transition at the bit boundary of these two bits. CONSTITUTION:The end flag D3 of the fourth pattern of the special conversion rule of an M<2> code is detected by an AND gate 14 of 6-inputs and the end flag D3 of the input data of a third pattern is detected by the AND gate 16. Then, in the third pattern, as for the final bit among the levels '1' existing continuously in the even number, the level transition at the center of the bit is prevented from being caused. Besides, in the fourth pattern, as for the final two bits among the levels '1' existing continuously in the even number, the level transition at the center of the bit is prevented from being caused, and simultaneously, the level transition is caused at the bit boundary of these two bits. Thus, the ratio of the maximum inversion interval and the minimum inversion interval is made small, and the degree of centralization of a spectrum can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION A. FIELD OF INDUSTRIAL APPLICATION The present invention relates to a coding circuit for the transmission of data in serial binary form via an information channel, in particular the so-called M"
The present invention relates to a code (ModjNed Miller Code) encoding circuit.

B9 Summary of the Invention The present invention provides the first level (
This is expressed as "I") to cause a level transition at the center of the bit, and at the second level of the binary signal (this is expressed as 0''), if the level "0" continues, The level transition is caused at the bit boundary, and the level transition is not caused during the bit period of the level "0" following the level "1", and the binary signal is changed to the level "1". The second binary signal is classified into a predetermined pattern according to the level "0" state, and the occurrence of the level transition is controlled according to this pattern to suppress the DC component contained in the first binary signal. In a digital modulation method for forming a value signal, there is a first pattern in which the levels "]" are consecutive, one each of the levels "0" is present at the beginning and one at the end, and the levels "1" are present in between. '' or a second pattern in which an odd number or zero exists in a row, and the level "0" or the second pattern in which one exists first, followed by the level "1".
or a consecutive even number, and then the above level "0"
” are present two times in a row, and the above level “o” is present once, and then the above level “1” is present.
exists in consecutive even numbers, and following this, the above level "0"
In the third pattern, there is an even number of successive levels of level "1".
For the last bit of 2, the level transition at the center of the bit is prevented, and in the fourth pattern,
For the last two bits of the consecutively even number of level "1"s, by not causing a level transition at the center of the bit, and by causing a level transition at the bit boundary of these two bits, the above-mentioned By modulating the first binary signal, it is possible to increase the effect in achieving high-density magnetic recording.

C9 Prior Art Currently, there are various digital modulation methods for magnetic recording.

These digital modulation methods include the so-called D-1 for component color digital video tape recorders.
The NRZ modulation method used in the so-called D-2 format of composite color digital video tape recorders, the M' modulation method used in the so-called digital audio tape recorder (DAT), etc. -10 modulation method, 8-9 modulation method used in data recorders, etc.

The characteristic parameters for improving the recording density on tape or the like using such a digital modulation method and the characteristic parameters that affect the reliability of the system include the minimum inversion interval TM+ssMI inversion interval T. AI and detection window width T1
, the presence or absence of a DC component, etc.

The minimum inversion interval T MIN is the minimum interval between a position where a signal inversion (transition) occurs and the next inversion position. The larger the minimum inversion interval TMIN, the more convenient it is to increase the recording density.

The detection window width TvI indicates the degree of margin in which code errors do not occur even if there is a fluctuation of the signal in the time axis direction due to jitter or a peak shift due to code amount interference. This detection window width T can also be expressed as a so-called eye pattern aperture ratio. As for the detection window width T1, as described above, the larger the inversion (transition) interval, the higher the aperture ratio of the eye pattern can be.

The maximum inversion interval T MAf is the maximum interval between a position where a signal inversion (transition) occurs and the next inversion position. For example, the smaller the maximum reversal interval TMA
This is advantageous in that it can cope with peak shifts, peak shifts, etc.

The presence or absence of a DC component indicates whether the modulated signal includes a DC component. It is advantageous for this modulation signal to contain no direct current component.

Table 1 shows the relationship between each modulation method and each characteristic parameter described above.

Table 1 In Table 1, T indicates the data bit interval and DC
The symbols in the free column indicate × or disadvantageous because it has a DC component, ○ and ◎ which have no DC component and therefore are advantageous or extremely advantageous, respectively.

As shown in Table 1 above, it can be seen that the data transmission method that allows modulation without DC fluctuation is the M2 modulation method.

Since such a C-free code does not include a DC component in the frequency spectrum components of the modulated signal, it is very advantageous in designing a system.

Furthermore, the M2 modulation type is superior to other types in that it has a larger minimum inversion interval, and has the potential for higher density.

The basic invention of the M'' code, which is one of the digital modulation systems with the above-mentioned advantages, was published in Japanese Patent Application Laid-Open No. 52
It is disclosed in the publication No.-114206. According to this, the M2 code corresponds to a level transition at the center of the bit when the level is "1" for binary (bit unit) continuous data, and no level transition when the level is "0". Make things correspond. Also, the M2 code is
A mirror code (Mille
r Code), the last bit “1” when an even number of level “1”s are consecutive after the bit level “0”
By providing a special conversion rule that corresponds to "no inversion", the mirror (M2
) is the code.

The conversion rules for this improved mirror (M2) code are:
It is as follows.

In other words, M! The code is NRZ (Non Return
t.

A pattern consisting of bits with only level "1" for binary continuous data in Zero) format: Example: "1", "1", "l", ..., "l", and " at the beginning and end. A B pattern consisting of bits in which there is a 0" and zero or an odd number of "l"s between them.

Example 1: "0", "0", "0" Example 2: "0", "l", "1", "1", "0", first there is "0", then an even number of consecutive "1" exists and the following bit is "0".

Here, the sum value DSV (Digital Sum) of each level used when evaluating the DC component of the modulated signal is
Value) is expressed as the sum of the points according to the rule that when the code waveform is at high level "1", +1 point is given and when it is at low level "0", it is given 11 points. Among these patterns, this level sum value DSV becomes zero in patterns A and B, but it becomes zero in patterns C
It does not become zero in the pattern. Therefore, the generation of level transition is controlled so as not to invert the last bit "1" of the C pattern, thereby suppressing the DC component.

The timing chart shown in FIG. 7 shows the conversion by the mirror code and the conversion by the M2 code with respect to the input of continuous binary data in the NRZ format, and the respective level sum values DSV. When encoding continuous binary data in the NRZ format as shown in (A) of Figure 7, the M2 code is classified into three patterns, A-C, as shown in (B) of Figure 7. The period corresponding to each pattern is T
Represented by o, T, , Te. The signal shown in FIG. 7(C) is
This shows a signal obtained by converting the above-mentioned NRZ format binary continuous data into a mirror code. The level sum value DSV for the signal shown in (C) of FIG. 7 is (D
), the above level sum value DSV changes over time.
The product of the waveform level rule and the duration of the waveform level is displayed on the vertical axis, and is expressed by the sum of these products. In this input example, the sum of the products of the waveform level rule of the level sum value DSV and the duration of the waveform level continues to increase in the negative direction with time. Further, the signal shown in FIG. 7(E) indicates the above-described binary continuous data in the NRZ format or a signal converted into the M2 code. The level sum value DSV is shown in FIG. 7(F) using the same rule as in FIG. 7(D) above. On the other hand, the level summation value DSV shown in FIG. 7(F) can maintain the summation of products near zero. Here, T shown in (D) and (F) of Figure 7
is a time corresponding to the bit unit length of the binary continuous data in the NRZ format described above.

In this way, the M2 coat can be made to have no direct current component in the frequency spectrum of the recording current waveform by providing the special conversion rule as described above.

Further, the above-mentioned Japanese Patent Laid-Open No. 52-114206 also discloses an encoding circuit for generating the above-mentioned M2 code. This encoding circuit has a configuration shown in the circuit diagram of FIG. 8, and operates as follows.

In this encoding circuit, clock input terminals 30, 31
The clocks φ7 and φ2 supplied to the
The falling edge of clock φ2 indicates the boundary between bits, and the falling edge of clock φ2 indicates the center of the bits. The pulse width of the clocks φ1 and φ2 must not be less than (1/2) of 1 bit.

Further, input data D1 expressed as NRZ-L is supplied to the data input terminal 32.

The input data D1 is supplied to the J input terminal, and the first J is supplied to the input terminal via the inverter 33.
−, the flip-flop circuit 34 receives the input data D,
delay by 1 bit. form. This first J-
Data D0 formed by the flip-flop circuit 34 in
represents the current bit corresponding to the encoded output M".,? from this encoding circuit, and the input data D,
represents the next bit of the current bit of data D0.

The second J- flip-flop 37 to which the clock φ is supplied to the clock input terminal via the gate 35 and the inverter 36 passes through the gate 35 when the bit data D0 is currently at logic "1'". Count the clock φ, and when the current bit data D0 is logic “0”,
Data P indicating whether the number of logic "1"s in each sequence is currently even or odd by being reset by the clock φ passing through the gate 38. form.

Further, the inverted data is sent from the input terminal of the flip-flop 34 to the first J-. The third J- flip-flop 39, which is supplied to the J input terminal, currently has the bit D. When is logic "0", clock φ2 is counted to form data P2 indicating whether the number of logic "0's" for each sequence is currently even or odd.

In this encoding circuit, when the current bit data D0 and the input data D1 are both logic "0", a logic It is determined that “0” continues, and the clock φ1 is switched to the gate 4.
0 is supplied to the D flip-flop 42 via the gate 41, and when the logic "0" continues, the D flip-flop 42 is inverted at that bit boundary.

Furthermore, when the current bit data D0 is logic "1",
The bit central clock φ2 passing through the gate 35 is supplied to the D flip-flop 42, and the logic “1” is applied.
The D flip-flop 42 is inverted at the center of the bit.

Here, for sequences other than the above-mentioned C pattern, logic “
Zero or two 0's are included, but in the C pattern, the logic 0 is originally an odd number at the beginning of the sequence, but becomes an even number.

Therefore, this encoding circuit uses bit data D.

When the number of logic "0" and logic "I" in the sequence are both odd numbers (Pz = t, P, = 1), it is determined that the C pattern is the last, and the gate is activated. 43
The inversion is made 1 by resetting the flip-flop 39 to the third J- using the suppress signal S formed by the gate 45 or the clock φ1 which is supplied via the inverter 44 and passing through the gate 45 as the window pulse W.
The data is inverted an extra number of times so that the first logic "0" following the sequence of the third pattern is an odd number.

The above is the operation of the encoding circuit for generating the M2 code disclosed in the above-mentioned Japanese Patent Laid-Open No. 52-114206.

In this way, M2 code conversion is performed on a binary continuous signal in the NRZ format as shown in FIG.
MAW becomes 3T.

D. Invention or problem to be solved Although the M2 modulation type has the great advantage of being a DC-free code with no DC component, as shown in Table 1, the maximum inversion interval T, A, /minimum inversion Interval TMI
If the ratio of N is large, the degree of concentration of the spectrum will deteriorate, and the override characteristics will also deteriorate during recording.

In addition, the maximum reversal interval T, 4AK/minimum reversal interval T
As indicated by the ratio of M I N, if a recording pattern with a long inversion period and a recording pattern with a short inversion period are coincidentally connected in series, a peak shift may occur due to signal code amount interference. It becomes easier.

Therefore, in view of the above-mentioned problems, the present invention provides maximum inversion I! in a DC-free code! It is an object of the present invention to provide a digital signal modulation method in which the ratio of lffwIITMAXx/minimum inversion interval T M l s is small.

Means for Solving Problem E1 The digital signal modulation method according to the present invention causes a level transition at the center of the bit at the first level (this is expressed as "B") of the first binary signal in the NRZ format. , at the second level (represented as "0") of the binary signal, the level "
In the case of consecutive 0's, a level transition occurs at the bit boundary, and in the bit period of one level "O" following the level "1#", a level transition is not caused, and the binary value is The signal is classified into a predetermined pattern according to the state of the level "l" and the level "0", and the occurrence of the level transition is controlled according to this pattern, so that the direct current included in the first binary signal is In a digital modulation method that forms a second binary signal with suppressed components,
A first pattern in which a plurality of the above levels "1" are consecutive, one each of the above levels "0'" exists at the beginning and one at the end, and an odd number or zero of the above levels "1" exist in between. The second pattern is that the above level "0" exists one at first, then the above level "l" exists an even number of times in a row, and then the above level "0" or two successive times exist. The third pattern that exists is that the above level "0" exists first, then the above level "l" exists an even number of times in a row, and then the above level "0" exists one time. In the third pattern, the last bit of the consecutively even number of levels "1" is classified into In the fourth pattern, for the last two bits of the consecutive even number of level "1"s, the level transition at the center of the bit is prevented. In addition to preventing the occurrence of
The above problem is solved by providing a code circuit so as to modulate the first binary signal by causing a level transition at the bit boundary of these two bits.

F. Function The digital signal modulation method according to the present invention is based on the input 2
By classifying continuous value data into the above-mentioned third and fourth patterns and introducing the fourth pattern, the maximum inversion interval TMA when transmitted without being classified into the above-mentioned patterns in the conventional M2 code can be improved. It is possible to shorten the time interval. Furthermore, since the ratio of (maximum inversion interval TMAX/minimum inversion interval T□,) also becomes smaller, the degree of concentration of the spectrum improves.

G. Examples Hereinafter, specific examples of the present invention will be described with reference to the drawings.

FIG. 1 shows the configuration of an embodiment of an encoding circuit for realizing the digital modulation method according to the present invention.

The encoding circuit of this digital modulation method has the configuration shown below.

First, a data delay block 1 is provided with four D flip-flops 2 to 5. The input 200 million continuous data in NRZ format are sequentially delayed by 1 bit per D flip-flop and output. The outputs of each D flip-flop 2 to 5 are output in synchronization with the rising pulse of the clock NRCK, and the respective delay data N1
,N2,N,,N,.

Also, “1” count check block 6 is
It is composed of a D gate 7 and a D flip-flop 8.

The delayed data N from the Q terminal of the D flip-flop 4 is input to two input terminals of the AND gate 7, and the output signal from the Q terminal of the D flip-flop 8 is inverted.

The output of the AND gate 7 is output data x2 generated having a relationship with each delay data shown in FIG. 2, which will be described later, and is input to the D terminal of the D flip-flop 8. The Q output of this D flip-flop 8 is delayed by one tarok of the clock by the clock NRCK and is supplied to the AND gates 7, 14 and 15, respectively. Here, the Q output of the D flip-flop 8 is output data X shown in FIG. 2, which will be described later.

The "O" count check block 9 is composed of an AND gate 10, 2 manual AND gates, 11, 2 manual OR gates 12, and a D flip-flop I3 with 3 inverting inputs. The AND gate 10 with three inverted inputs receives the delayed data N2 from the Q terminal of the D flip-flop 4, the end flag C3 of the third pattern which is a special conversion rule for the M2 code according to the present invention, and the D flip-flop 13. Q of
A signal is supplied from the output, and delayed data N from the Q terminal of the D flip-flop 4 is supplied to the two-man AND gate II.
, and signals from the Q output of the D flip-flop 13 are supplied. The above two-man OR gate 12 is composed of these three
AND gate 10 consisting of two inverting inputs and two-man AND
The output signals of the gate 11 are logically summed. This output data indicates output data y generated by developing a relationship with each delay data shown in FIG. This output signal is input to the D flip-flop 13, and the clock N
1 of the above clock in synchronization with the rising pulse of RCK.
Output with a clock delay.

Here, the Q output of the D flip-flop 13 is output data y shown in FIG. 2, which will be described later.

Next, the end flag D of the fourth pattern, which is a special conversion rule for the improved M2 code (M-M2 code) according to the present invention, is detected by an AND gate 14 made up of six people.

This AND gate 14 receives the delayed data N, -N, which are binary continuous data, and the output data X, y2, respectively. Note that 2 of the delay data N2 and the output data y
Two signals are input inverted.

The third pattern is the detection signal CP, which is the 4-man power AN
Detected by D gate 15.

The AND gate 15 receives delayed data Nx, N- of binary continuous data, and the output data X2 and y3. Data other than the delay data N and D are inverted and input.

The end flag C2 of the NRZ format input data classified into the third pattern according to the present invention is detected by the AND gate 16.

The AND gate 16 receives the inverted delay data N, and inputs the output of the AND gate 15. This output is supplied to one terminal of the 3-inverting input AND gate IO of the "0" count check block 9.

The central inversion block 17 is composed of a three-man AND gate 18 and a D flip-flop 19.

3-person AND gate 18 has AND gate 14.15
The delayed data N4 is inputted from the Q terminal of the D flip-flop 5, and this output is supplied to the D terminal of the D flip-flop 19. The D flip-flop 19 outputs a center inverted output from the Q terminal of the D flip-flop 19 and sends it to the selector block 24 .

Further, the rear 3 edge inversion block 20 has 2 inversion inputs AN
D gate 21. Consists of two human-powered OR gates 22 and a D flip-flop 23.

The AND gate 21 includes a D flip-flop 4.5
Delayed data N, which is output from the Q terminal of.

and inputs N4. The logical product of the AND gate 21 is input to one end of the OR gate 22. Further, the end flag D of the fourth pattern is inputted to the other terminal of the OR gate 22 from the output terminal of the AND gate 14.

This OR gate 22 sends the logical sum of the above two inputs to the input terminal of a D flip-flop 23. D above
The flip-flop 23 outputs this input OR output data from the Q terminal as the last three edge inverted data, and sends it to the selector block 24.

The selector block 24 consists of two-man powered OR gates 25 and 26 and a two-man powered NAND gate 27.

The NRCK clock obtained by inverting the NRCK clock obtained by dividing the MMCK clock for M1 code conversion by (1/2) via the buffer 28 and the center inverted data are input to the two-man OR gates 25 and 26. Furthermore, the non-inverted NRCK clock and the last three edge inverted data are input to the OR gate 26 via the buffer 28. The output of these OR gates is the NAND gate 2
7 to the J input terminal of the flip-flop 29. The clock of this J- flip-flop 29 has a frequency twice that of the NRCK clock.

From the Q and output terminals of the flip-flop 29 to this J-, MMDATA (X), which is an improved M"(M-M") code, and MMDATA ( Y) is output.

Note that the clock of the D flip-flop shown in the above configuration uses the NRCK clock obtained by dividing the clock of the above-mentioned M' code conversion MMCK by (1/2).

In this way, an encoding circuit for improving the M2 code is configured.

FIG. 2 shows the relationship between the input data in the encoding circuit shown in FIG. 1 and the above-mentioned output data outputted through the respective logic circuits of the encoding circuit.

The input NRZ format binary continuous data as described above is delayed by one bit for each D flip-flop in the data delay block shown in FIG. At the time when the binary data N0 in the NRZ format (not shown in FIG. 2) is input to the D terminal of the D flip-flop 2 in FIG.
, N*, and N4. As shown in FIG. 2, time changes in the direction of the arrow. Therefore, the delay data shown in FIG. 2 is expressed as N, , N, , N, , N, when shown in the order of input.

Furthermore, the next M-M" code is generated using the clock MMCK, which has a frequency twice that of the clock NRCK. Therefore, the data of the next M-M" code is finally generated using the clock MMCK, which has a frequency twice that of the clock NRCK. Two are generated within. The generated M−M” code has M in the interval of the delayed data N1.
, ,M, and the delayed data N2 to N4 are similarly expressed as "M, ,M4", "M, ,M,", "M, ,
M,” is expressed.

In detecting “l# count” or “0” count,
The relationship with the delayed data is such that data is generated by the previous data and the next data, as shown in FIG.

Therefore, the subscript numbers used for counting "1" and "0" are expressed using the subscript numbers of the next delayed data.

For example, in FIG. 2, for the delayed data N and N2,
A count of "0" is represented as output data X, and a count of "0" is represented as output data y.

In particular, when the third and fourth pattern end flags are detected in N and N, the numbers in the subscripts of the third and fourth pattern end flags include the numbers in the subscripts of the respective delay data. It corresponds to That is, the third
The end flag of the pattern corresponds to C2 and C3,
Similarly, attach and remove the end flag of the fourth pattern,
It corresponds to

In addition, the delay data “N” and the count data of “1” “
Since the CP flag data generated at the count "y" of "X" and "0" is expressed by the relationship between two delayed data, the data " Similarly to the data ``y'' generated in the count of ``y'', the subscript numbers of the output data CP flag data for the delayed data N4 and N in FIG. The same number as the next delayed data N is expressed as CP.

Using these symbols explained above, the specific operation of the M-M" code encoding circuit shown in FIG. 1 for improving the M2 code is as follows. (The reference numeral a in Fig. 1
-See also W. ) This M! The encoding circuit for improving the code uses the clock MMCK (signal a in FIG. 1) to create the M-M2 code shown in FIG. Clock NPCK (
The signals shown in FIG. 1 are used.

In the data delay block 1, the input NRZ format binary continuous data is taken in in synchronization with the rising pulse of the clock NRCK supplied to each D flip-flop, as shown in FIG. The output of each D flip-flop is the clock NRCK.
Since it is output in synchronization with the rising pulse of the clock NRCK, it is output after being delayed by one clock of the clock NRCK, that is, by one bit.

The delayed output data N1 to N4 of the D flip-flops 2 to 5 shown in FIG. 1 are represented as output waveforms eh shown in FIG. 3.

In the "1" count check block 6 shown in FIG. 1, the output of the AND gate 7 is represented as output data X shown in FIG. 2, and the output of the D flip-flop 8 is represented as output data X. represents.

Also, “01 count check block 9 indicates that O
The output of the R gate 12 is expressed as output data y shown in FIG. 2, and the output of the D flip-flop 13 is expressed as output data y,
It is expressed as

"In the l# count check block 6, the condition for the output data X to output "l" is when the input delay data N = 1 and the output data X = 0. This " 1” count check block 6
Here, a rule is generated that does not invert the data for the next input data after "1" is input.

The D flip-flop 8 latches and outputs the output data X in synchronization with the rising pulse of the clock NRCK, as indicated by j in FIG.

(Signal with reference symbol in Figure 1) This output waveform i shown in Figure 2
Output data X is an output waveform j delayed by one clock of clock NRCK with respect to (output data X2).

Next, in the "0" count check block 9, the conditions for the output data yt to output "1" are: delay data N,=1, output data y.

There are two cases: when =1, or when delay data N =0, output data y =0, and C220. The output waveform in FIG. 3 includes this output data y.

(signal indicated by the reference numeral in FIG. 1).

Note that the above output data C1 includes output data CP, which will be described later.
The conditions are set by the delay data N, and the delay data N.

This output data y2 is input to the D flip-flop 13, latched in synchronization with the rising pulse of the clock NRCK, and output with a delay of one clock of the clock NRCK. This output waveform l is the output data ys shown in FIG.
(signal 1 in FIG. 1).

The output data y from this "0" count check block 9 is sent to the input terminal of an AND gate 14.15.

Next, the AND gate 15 consisting of four people shown in Fig.
At the output (signal with sign m), the output waveform m in Fig. 3 is
indicates output data CP.

The conditions for outputting this data CP, or 1 are delayed data N,
20, N, = 1, output data X and y.

When both are at level "0", level "1" is output.

This output data CP is sent to AND gate ]6.18.

The data CP detected above is combined with the delayed data N delayed by 2 bits to the AND gate 16 shown in FIG.
is input.

In this AND gate 16, the conditions for outputting level "1" are the 2-bit delay data N2 = 0, the output data CP = 1, and at this time, the end flag C1 of the third pattern (Fig. signal with sign n) is the level “
Outputs "l".

The end flag C8 of this third pattern is shown in the output waveform n in FIG.

On the other hand, the AND gate 14 detects whether it is the fourth pattern based on the delayed output of the input binary continuous data.

Here, the end flag D of the fourth pattern is level "
The conditions for outputting "l" are the above delay data N, = 1, N2
=0, N5=1, N, =1, output data x, =1, y,
It was when I was twenty.

This end flag D is based on the fourth pattern shown in FIG.
It is determined whether or not there is one level "0" and then one level "l" (sign 0 in Figure 1).
signal).

The end flag D of this fourth pattern is shown in output waveform 0 in FIG.

In this check, the AND game 114 shown in FIG.
Delayed data N, -N4, which are respectively delayed outputs of binary continuous data, are input to the input terminals. Also, AND gate 14
D in “l” count check block 6
Output data X3 of flip-flop 8 and D flip-flop 1 in “0” count check block 9
3 output data y is input. In this way, the end flag D of the fourth pattern detects the second to last bit of the consecutively even number of level "1"s. By detecting this position, it is possible to detect the bit boundary of the last two bits of the even number of successive level "1's" according to the fourth pattern rule.

In the central inversion block 17 shown in FIG.
The first level or level “1” of the rules of the code
A level transition is caused at the center of the bit at the input of It is configured so that it does not.

The condition for the output of the AND gate 18 in the central inversion block 17 shown in FIG. In order to prevent the level transition at the center of the bit from occurring in the last bit, when the output data CP3 = o and the fourth pattern end flag D3 = 0.4 bit delayed delay data N, -t, the level is set to "1". (signal p in FIG. 1).

The output waveform in accordance with this center-inversion condition is shown as output waveform p in FIG.

Further, this output is latched in the D flip-flop 19 in synchronization with the rising edge of the clock NRCK. This latch output is black.

The signal is delayed by l clocks of NRCK and output (signal q in FIG. 1).

The output waveform q of the timing chart in Fig. 3 is an output waveform (signal q shown in Fig. 1) that instructs a level transition at the center of the bit, that is, a center inversion, in the four patterns classified. It shows.

The output waveform r of the timing chart shown in FIG.
After 3 edge reversal pro shown in the figure, OR in Tsuk20
The output of the gate 22 is shown (signal r in FIG. 1).

In the rear 3 edge inversion block 20, AND gate 2
1 is input with delayed data N, , N, which are binary continuous data.

The conditions for setting the output of this AND gate 21 to "1" are 2
This is when the level is "0" together with the 3 bits of value continuous data and the delayed data N,=0, N420 delayed by 4 bits. As a result, the conventional M" code conversion rule is that when levels "0" or consecutive, the condition is such that a level transition is made at the hint boundary between level "0" and level "02."

Furthermore, this OR gate 22 outputs the end flag D of the fourth pattern, that is, the last three edges (delayed signals N4 and N
An end flag D is input as data for level transition (between 2). By this, the above OR
In the fourth pattern, the output of the gate 22 can cause a level transition at the bit boundary of the last two bits of an even number of successive levels "1".

The OR gate 22 outputs the logical sum of the end flag D of the fourth pattern and the output data of the AND gate 21.

Next, as shown in FIG. 1, this output is input to the D flip-flop 23, latched out in synchronization with the rising pulse of the clock NRCK, delayed by one clock of the clock NRCK, and sent to the selector block 24. sending.

The latch output is shown by the output waveform S in FIG.

Output data from the central inversion block 17 and the latter 3
The output data from the edge inversion block 20 is supplied to one end of each OR gate 25, 26 of the selector block 24, respectively.

The OR gate 25 in the selector block 24 outputs the logical sum of the center-inverted output waveform q shown in FIG. 3 and the input clock NRCK or the clock NRCK outputted via the inverted output of the buffer 28. ing. This output waveform is shown as output waveform t in the timing chart of FIG. 2 (signal t in FIG. 1).

The OR gate 26 also outputs the output waveform S shown in FIG.
outputs the logical sum with the clock NRCK outputted via the non-inverted output of the buffer 28. This output waveform is shown as output waveform U in the timing chart of FIG. 3 (signal U in FIG. 1).

The above two output waveforms t and U are generated by the NAND gate 27
is input.

The output (signal V) of the NAND gate 27 shown in FIG. 1 has an output waveform V shown in FIG. This output waveform V is a conversion pattern obtained by converting the first and second patterns by conventional M2 code conversion and converting the third and fourth patterns by special conversion rules (including the level transition prohibition rule). become.

This output waveform V is input to the J terminal and the terminal of the flip-flop 29 shown in FIG.

In this J-, the output W of the flip-flop 29 is MMDAT A (X
) is output as

The output waveform W shown in FIG. 3 is the improved M2 (M-M2
) shows the code. This output waveform W is the output waveform V
operates according to clock MMCK.

The output waveform W from the flip-flop 29 on this J- is
This indicates that a level transition (bit inversion) occurs every time a rising edge of the input output waveform V is detected.

When a level transition is made at the rising edge of this output waveform W, the relationship between the corresponding NRZ data and the output waveform W shown in FIG. (see )) shows that a transformation that satisfies each rule has been performed. Furthermore, in detail, the level transition shown in the output waveform W in FIG. 3 is the level transition corresponding to the above rule, that is, the conventional M2
This is done on the prohibited side in the code conversion rules (first to third patterns) and the fourth pattern. In the M-M" code conversion in the third and fourth patterns that perform special level transitions, the last bit of the even number of successive level "1"s in the third pattern is changed to the center level of the bit. In addition, for the last two bits of the consecutively even number of level "1"s in the fourth pattern, the level transition at the center of the bit is prevented, and the bit boundary of these two bits is It is clear that the regular relationship that causes a level transition to occur is satisfied.

In this way an improved M2 (M-M2) code is generated.

Note that the output from the terminal of the J- flip-flop 29 shown in FIG. 1 has an inverted output waveform of the output waveform W shown in FIG. 3 above. This output waveform is MMD ATA (Y
).

The above is the operation of the encoding circuit shown in FIG.

Using this improved M' (M-M2) coat transformation, bit data or level transitions (
The maximum inversion interval TMAK for bit inversion (bit inversion) can be made shorter than in conventional M2 code conversion. This point will be briefly explained with reference to FIGS. 4 and 5 based on the conversion rules and prohibited sides in the four patterns described above.

As shown in FIG. 4A, in the first pattern, a level transition is made at the center of the bit for an input of level "1". Furthermore, in the second pattern shown in FIG. 4(B),
When the level is "0" or "o", level transition is made at the bit boundary. However, the rules for the first and second patterns of not performing level transitions at level "0" following level "l", such as levels "1" and "0", are exactly the same as the conventional rules. be.

On the other hand, in the third pattern, as shown in FIG. 4C, the level transition at the center of the bit is prevented from occurring for the last bit among an even number of successive level "1"s. For example, when the following third pattern of consecutive binary data is input, the position of the delayed data N, which is delayed by 3 bits, is detected and the following data is input: For example: NRZ data N, Ns N,
N.

The third pattern is prohibited so that a level transition does not occur at the center of the bit even if there is an input of level "l" of level "1", "l", 10", "0" 33-bit delayed data N. Rules are set.

In addition, in the fourth pattern, as shown in FIG.
For bits, the level transition at the center of the bit is prevented, and the level transition is caused at the bit boundary of these two bits.For example, when the following 4th pattern of continuous binary data is input, 4 Detect the position of the bit-delayed data N4, e.g. NRZ data N, Ns Nx
N+ level "1", "1", "0", "1" delayed data N4 and N delayed by 4 bits and 3 bits respectively,
A fourth pattern prohibition rule is provided so that a level transition does not occur at the center of the bit, but a level transition occurs at the boundary between the bits, and the code is converted into an M-M'' code.

Here, for the input of the same binary continuous data, the improved M2 (M-M'
) code and the conventional M2 code encoding are shown in FIG.

Level transitions in conventional M2 code encoding are classified into patterns as shown in FIG. 5A. Similarly, the level transition using the improved M2 (M-M2) code for inputting the same binary continuous data is classified into each pattern and the level transition is performed as shown in Figure 5 (B). There is.

T shown in FIG. 5 is expressed as a unit of bit interval of NRZ data.

In the M2 (M-M”) code, which has been improved to show the difference in level transitions between (A) and (B) in Figure 5, the level transition in the fourth pattern is at the position of the level transition by the conventional M2 coat. are different.

Furthermore, when comparing the conversion of input binary continuous data using each code conversion rule with respect to the maximum inversion interval TMAX in Figures 5 (A) and (B), (A) in Figure 4
The maximum inversion interval T MA (T indicates the data bit interval).

On the other hand, the maximum inversion interval T MAX in this improved M2 code is iT,A, =2.5 T, as shown in FIG. 4(B). In this improved M” (M-M2) coat conversion, the conventional M2
It can be smaller than the maximum inversion interval T MAW in the code.

Note that the other minimum inversion intervals TMIN and detection window width T have the same characteristics as the conventional ones, and are respectively the minimum inversion intervals T, , .
, =IT, detection window width T, =0.5T.

The M2 code improved in this way can improve the reliability of equipment by reducing the maximum inversion interval TMAX while maintaining various characteristics of the conventional M2 code without deteriorating. Therefore, the improved M2 code has a maximum inversion interval T
The ratio of MAf/minimum inversion interval TMIN can also be made small. Therefore, the spectrum obtained by M-M2 code conversion as shown in FIG. 6(B) has a higher degree of concentration than the spectrum obtained by conventional M2 code conversion shown in FIG. 6(A). There is a tendency to improve.

Reducing the maximum inversion interval TMAx is also advantageous in improving override characteristics related to recording density, peak shift characteristics related to code amount interference, and the like. Another advantage is that it is easy to perform reproduction equivalence.

In view of these points, this improved M2 code is significant as a means for achieving high-density magnetic recording, and its effects are significant.

Effects of the Invention H As is clear from the above explanation, in the digital modulation method of the present invention, the maximum inversion interval TM is
AX can be made smaller. Furthermore, by reducing the maximum inversion interval TMAX, it is possible to improve the concentration of the spectrum, so this improved M2 code has advantageous override characteristics, peak shift characteristics, etc., and makes it easier to perform reproduction equalization. do.

Therefore, this improved M2 code is significant as a means of achieving high-density magnetic recording, and its effects are significant.

[Brief explanation of drawings]

FIG. 1 is an encoding circuit diagram of an embodiment of improved M2 code conversion, which is a digital modulation method according to the present invention, and FIG. 2 shows delay data and symbols for explaining the circuit operation shown in FIG. 1. 3 is a timing chart 1 explaining the circuit operation shown in FIG. 1, FIG. 4 is a schematic diagram illustrating the rules for each pattern of improved M2 code conversion, Figure 5 shows M2 code conversion and improved M
A schematic diagram showing the difference between the two code conversions, Figure 6 shows the M2 code conversion and the improved M! FIG. 7 is a schematic diagram showing the operation of conventional M2 code conversion, and FIG. 8 is an encoding circuit diagram of conventional M2 code conversion. l・・・・・・・・・Data delay block 6...
"1" count check block 9..."0" count check block 14...end flag C8 detection gate 16...end flag C8
Detection gate 17... Center reversal block 20... Rear 3 edge reversal block 24.
・・・・・・・・・Selector Block Patent Applicant Sony Corporation Agent Patent Attorney Koike Mima 1) Sakae Mura - Masaru Sato 6- Fig. 2 1-T+ M-M2 Cor F Crime Rules Figure 4

Claims (1)

[Claims] The first level of the first binary signal in NRZ format (this is defined as “1”)
”) causes a level transition at the center of the bit,
At the second level of the binary signal (this is expressed as "0"), if the level "0" continues, a level transition occurs at the bit boundary,
In addition to not allowing a level transition to occur during the above-mentioned level "0" bit periods, the above-mentioned binary signal is classified into a predetermined pattern according to the state of the above-mentioned level "1" and the above-mentioned level "0", and this pattern is In the digital modulation method, the generation of the level transition is controlled accordingly to form a second binary signal in which the DC component included in the first binary signal is suppressed, wherein the level "1" is a plurality of consecutive first patterns; a second pattern in which the level "0" is present once at the beginning and once at the end, and an odd number or zero of the level "1"s are consecutively present between them; A third pattern in which there is first one level "0", then an even number of consecutive level "1"s, and this is followed by two consecutive level "0"s. , There is first one level “0” above, then there is an even number of level “1”s in a row, then there is one level “0” above, and then there is one level “1” above. “1
In the third pattern, for the last bit among the consecutively even number of level "1"s, the level transition at the center of the bit occurs. In the fourth pattern, for the last two bits of the consecutively even number of level "1"s,
A digital modulation method that modulates the first binary signal by eliminating a level transition at the center of a bit and causing a level transition at a bit boundary between these two bits.