JPH07154263A - Digital modulator - Google Patents

Abstract

PURPOSE:To calculate a DSV after I-NRZI conversion by a low speed circuit. CONSTITUTION:A modulated signal is given to a division circuit 32. The division circuit 32 divides the signal into odd number bits and even number bits and gives them to tables 34, 35 respectively. The tables 34, 35 store a CDS and its inverted signal when the modulated signal is subject to NRZI conversion. The tables 34, 35 store polarity discrimination data representing number of bits '1s' and a cyclic adder 36 discriminates the polarity at the end of a just preceding code by applying cyclic addition to the polarity discrimination data. The tables 34, 35 output a CDS with a polarity based on the result of sum of the cyclic adder 36 to an adder 41. The adder 41 adds the CDS to obtain the CDS when the modulated signal is subject to I-NRZI conversion. A DSV cyclic adder 42 obtains the DSV by adding cyclically the CDS from the adder 41. Since the DSV is obtained in the process of parallel processing, the DSV is calculated by a low speed circuit.

Description

Detailed Description of the Invention

[Object of the Invention]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital modulator suitable for a digital magnetic recording / reproducing apparatus.

[0002]

2. Description of the Related Art In recent years, with the progress of digital technology, image information has been digitally processed, and, for example, a digital video tape recorder (hereinafter also referred to as VTR) has been developed. In the transmission and recording of digital signals, it is difficult to transmit or record the signal components in the low frequency region with high efficiency. Therefore, modulation to a balanced code for suppressing the signal components in the direct current and low frequency regions, That is, DC-free modulation is often used.

In magnetic recording, the output characteristics deteriorate as the recording frequency increases. Therefore, in digital recording, it is necessary to increase the minimum magnetization reversal interval, that is, to convert into a modulation signal having a large minimum pulse width. Further, similarly, it is impossible to obtain a sufficient output for the components in the DC and low frequency regions. Therefore, it is necessary to reduce the maximum pulse width of the modulation signal, that is, to obtain the DC-free characteristic in which not only the DC component but also the entire low-frequency component is suppressed.

As a means for achieving these conditions, there is the 8-14 modulation method disclosed in Document 1 (Japanese Patent Laid-Open No. 61-196469). FIG. 4 is a block diagram showing this proposal.

The encoder 11 converts 8-bit input data into a 14-bit code. In the encoder 11, the minimum value d of the number of “0” s sandwiched between “1” s is a code of 1 among the 14384 types of 16384 kinds of codes, and the maximum value k of the number of “0s” sandwiched between “1s” is k. Of 8 bits, the number of consecutive "0" s from the beginning of the code s0 is 1≤s0≤4, and the number of consecutive "0" s e0 at the end of the code is 4 or less. Represents input data. The output of the encoder 11 is the shift register 12 and the synchronization signal addition unit.
It is given to the NRZI modulator 14 via 13. NRZI modulator
14 performs NRZI modulation in which the recording level is inverted at the front end of the symbol "1".

Since the code of the encoder 11 is limited as described above, the data after NRZI modulation has a minimum pulse width of 2 from d = 1 and a maximum pulse width of 9 from k = 8. Since 8-bit data is converted into 14-bit data and transmitted, the 1-bit interval after modulation is 8T (T is a data period) / 14, and the minimum pulse width is 2. Therefore, the minimum magnetization reversal interval is about 1 It can be increased to .14T (= 16T / 14).

Even at the joint between cords, d
= 1, that is, in order to satisfy that “1” does not continue at the beginning and the end of the code and k = 8, 1 ≦ s0 <4
It is set to 0≤e0 <4.

Further, in the 8-14 modulation system, DSV (Di
CDS (Code D), which is the DSV for each modulation code, in order to reduce the absolute value of the (Gital Sum Value) (charge accumulation value).
Only codes whose absolute value of (igital Sum) is 6 or less are used.
Further, in order to reduce the absolute value of DSV, the encoder 11
Is a table A corresponding to DSV <0, a table B corresponding to DSV> 0, and a table C corresponding to DSV = 0.
Is prepared, and code conversion is performed by switching these three types of tables.

Tables A, B and C are input data 0 to 25.
5, the code of CDS = 0 is preferentially stored in a predetermined area of the tables A, B, and C. That is,
The input data corresponding to the predetermined area is the table A, B, C.
Whichever is used, the same code is converted to CDS = 0. Further, the table A stores the code of CDS> 0 and converts other data that cannot be converted into the code of CDS = 0 into the code of CDS> 0. Table B
Stores a code of CDS <0 and converts other data that cannot be converted into a code of CDS = 0 into a code of CDS <0. Table C stores the code having the smaller absolute CDS value among the codes of CDS ≠ 0 stored in tables A and B. Based on the DSV and the waveform polarity up to the code immediately before, one of the tables A, B and C is selected to limit the upper limit of the DSV. That is, the polarity determination unit
17 determines the waveform polarity of the code immediately before from the encoder 11,
The DSV calculator 18 calculates the DSV up to the immediately preceding code. The exclusive logic circuit 19 includes a polarity determination unit 17 and a DSV calculation unit.
The encoder 11 is controlled by obtaining the exclusive OR of the 18 outputs. Further, the DSV = 0 judging section 20 judges that DSV is 0 and controls the encoder 11.

The symbol "1" has a low level (hereinafter referred to as "L") and a high level (hereinafter referred to as "H").
That is, even if the same code is used, the sign polarity of CDS is inverted depending on the waveform polarity of the immediately preceding code. Therefore, the CDS of each code is defined as, for example, the waveform polarity of the immediately preceding code is negative.

The encoder 11 includes an exclusive logic circuit 19 and a DSV.
= 0 The table is selected by the output of the determination unit 20. The encoder 11 firstly d = 1, k = 8, 1≤s0 ≤4,0≤e
Among the codes that satisfy the condition of 0 ≦ 4, the code of CDS = 0 is preferentially assigned to the 8-bit input data in a one-to-one manner. Then, in correspondence with the remaining 8-bit input data, two codes having positive and negative CDSs are assigned one to two. That is, when the CDS of the code corresponding to the input data is not 0, it is converted into a code that reduces the DSV of the two codes corresponding to the input data. That is,
When the DSV up to the immediately preceding code is positive and the waveform polarity is negative, the CDS is converted into a negative code among the two codes whose CDS is positive and negative. Also, the DSV up to the code immediately before
Is negative and the waveform polarity is negative, the CDS converts to a positive code. As described above, in the 8-14 modulation method, when the input data is not the code of CDS = 0, the CDS should be converted into one of the positive code and the negative code according to the DSV and the waveform polarity up to the immediately preceding code. Therefore, the upper limit is set for DSV to obtain the DC-free characteristic.

FIG. 5 is a block diagram showing another conventional digital modulator which performs DC-free modulation. Figure 5
Is disclosed in Document 2 (Japanese Patent Laid-Open No. 3-234146) and realizes a new 8-14 modulation system adopted in the format D-3 system of the digital VTR.

The 8-bit input data is supplied to the encoder 2 and the modulation code CDS calculator 5. The encoder 2 converts the input data into a CD that is a DSV for each modulation code.
The absolute value of S is converted into a 14-bit modulation code whose absolute value is 4 or less and output to the parallel-serial conversion unit 8. The CDS calculation unit 5 outputs a 3-bit code indicating whether the CDS of the modulation code is 0, ± 2, ± 4 to the DSV calculation unit 4 of the modulation code. The DSV calculator 4 outputs a value obtained by adding the CDS of the input modulation code and the DSV at the end of the immediately preceding modulation code as a new DSV. The output of the DSV calculation unit 4 is either -2, 0 or 2, and is represented by 2 bits. The latch 6 latches the output of the DSV calculation unit 4, feeds it back to the DSV calculation unit 4, accumulates it, and outputs it to the encoder 2 and the modulation code end determination unit 3.

The modulation code termination method determining unit 3 determines the termination method of the last 6 bits of the 14-bit modulation code. There are 12 types of endings of the modulation code, and the ending judging unit 3 indicates the judgment result (ending) by 4 bits. Latch 7
Latches the output of the ending decision unit 3 and outputs it to the encoder 2 and feeds it back to the ending decision unit 3.

The encoder 2 converts the input data into a modulation code based on the outputs of the latches 6 and 7. That is, the encoder 2 has the number of consecutive bits of the same polarity (hereinafter, referred to as “run”) of 7 or less at the joint with the immediately preceding modulation code, and the absolute value of DSV at the end of the modulation code is 2
Select the following modulation code. The modulation code from the encoder 2 is given to the parallel-serial conversion unit 5. The parallel-serial conversion unit 5 serially outputs the modulation code to the recording unit 10 in synchronization with the clock from the terminal 9. Recording section
Reference numeral 10 records the modulation code on a predetermined recording medium.

As described above, in the apparatus of FIG. 5, since the run of the modulation code of the NRZ rule is 2 or more and 7 or less, high density recording is possible, and further azimuth recording and overwriting recording are possible. . Further, the DC-free modulation is realized by selecting the modulation code having the DSV closest to 0.

In both of the conventional examples shown in FIGS. 4 and 5, the DSV of the modulation signal is controlled to suppress the low frequency component of the modulation signal. Therefore, the means for calculating the value of DSV is an important element of the modulator. Generally, the DSV is defined as a value obtained by adding the symbol "1" of the modulated signal to +1 and the symbol "0" to -1. Therefore, the DSV can be obtained by repeating addition according to this rule each time each symbol of the bit-serial modulated signal is input. This calculation method uses NRZ conversion and N
It can be commonly applied to various conversion methods such as RZI conversion. However, the transmission speed of a bit-serial signal is extremely higher than that of a circuit portion that performs parallel processing. For example, in Document 1, since the modulation signal is composed of 14 bits, the transmission rate of the modulation signal is 14 times the transmission rate of the modulated signal. Therefore, it is not preferable to set an arithmetic circuit for calculating the DSV in a portion that processes a bit serial signal.

For this reason, in the apparatus shown in FIGS. 4 and 5, the DSV is obtained by using the CDS of each modulated data. Hereinafter, DSV calculation in NRZ conversion and NRZI conversion will be described using Documents 2 and 1, respectively.

Now, when the process of adding the n-th symbol as an and adding "1" of each symbol as +1 and "0" as -1 is represented by the symbol ▼, DSV can be expressed by the following equation (1). it can.

DSV = a1 ▼ a2 ▼ a3 ▼ ... ▼ a13 ▼ a14 ▼ a15 ▼ ... ▼ a28 ▼ a29 ▼ ... (1) The 14-bit parallel output of the encoder 2 shown in FIG. After being converted into a serial signal by 8, it is given to the recording unit 10 as it is. That is, the NRZ conversion is a conversion method that outputs an input signal as it is, and n
If the th symbol is an, the output is also an. Here, a1 to a14 are each bit of the first 14-bit parallel data (output of the encoder 2), and similarly am1 to am14 (m is a natural number) are each bit of the m-th 14-bit parallel data. As a matter of fact, DS for each modulation code
If V is put together, a formula (1) can be changed like a following formula (2).

DSV = (a1 ▼ a2 ▼ a3 ▼ ... ▼ a13 ▼ a14) + (a15 ▼ a15 ▼ ... ▼ a28) + (a29 ▼ a30 ▼ ... ▼ a31) + …… (2) From this equation (2) It can be seen that the DSV is obtained by cumulatively adding the CDS of each 14-bit parallel data. In Document 2, the 8-bit parallel data input to the encoder 2 is given to the CDS calculator 5 to obtain the CDS. Although not specified in Document 2, it is considered to use a table in which CDSs of 14-bit parallel outputs for 8-bit inputs are stored in advance. Using this table, the CDS is obtained from the input of the encoder 2 and the DSV calculation unit 4
The DSV is calculated by applying CDS to the cyclic adder composed of the latch 6 and the latch 6. In other words, the DSV calculation is performed in units of 14-bit parallel signals, which enables low-speed calculation.

Next, an example of the document 1 adopting the NRZI conversion will be described. FIG. 6 is a circuit diagram showing a specific configuration of the NRZI conversion circuit.

The input symbol an is given to the exclusive OR circuit 25. The output of the exclusive OR circuit 25 is the output symbol bn.
And is delayed by one data by the delay device 26 and then given to the exclusive logic circuit 25. That is, NRZI
When "1" is input, the conversion circuit inverts the modulated signal and outputs it. When the exclusive OR operation is represented by the symbol @, the NRZI conversion can be expressed by the following equation (3).

Bn = an @ bn-1 = an @ an-1 @ bn-2 = an @ an-1 @ an-2 @ ... @ b0 ... (3) Further, the DSV is expressed by the following equation (4). You can

DSV = b1 ▼ b2 ▼ b3 ▼ ... b13 ▼ b14 ▼ b15 ▼ b16 ▼ ... ▼ b28 ▼ b29 ▼ ... (4) Applying the expression (3) to the expression (4), the same as the expression (2). In summary, the following formula (5) is obtained.

DSV = {(a1 @ b0) ▼ (a2 @ a1 @ b0) ▼ (a3 @ a2 @ a1 @ b0) ▼ ... ▼ (a14 @ a13 @ a12 ... @ a2 @ a1 @ b0)} + {( a15 @ b14) ▼ (a16 ...) ...} + ... (5) As shown in Expression (5), the CDS of each data is the constituent bits am1 to am14 (m = natural number) of each data and the immediately preceding modulation data. The last bit bk14 (k = 0,1,2, ...)
Required from. The CDS operation of the equation (5) indicates an addition in which “1” of the signal after NRZI conversion is set to +1 and “0” is set to −1. CDS is based on Reference 3 (National Technic
al Report vol. 32 No. 4 Aug. 1986 pp432), the value is defined as that bk14 is "0" (negative polarity), and bk14 is "1". The sign is reversed in the. That is, when the immediately preceding waveform polarity is positive, it is necessary to invert the sign of CDS.
In the NRZI rule, the waveform is inverted by "1", so
The code polarity after NRZI conversion is inverted for codes with an odd number of “1”, and the waveform polarity does not change even after NRZI conversion for codes with an even number of “1”. Therefore, "1" for each code
The waveform polarity can be determined by determining whether the number of bits of is an odd number or an even number and performing integration.

In FIG. 4, the encoder 11 outputs a 14-bit parallel signal to the shift register 12 and at the same time,
The CDS is output to the DSV calculation unit 18, and the polarity reversal unit 17
The number of "1" in 14 bits is output to. The DSV calculation unit 18 cyclically adds the CDS, and the polarity determination unit 17 obtains and outputs the polarity of the addition result of the cyclic addition. Thus, DSV
Is required.

NRZ conversion used in FIG. 5 and N used in FIG.
In the RZI conversion, since the output modulation signal is different for the same input, the value of DSV (symbol “1” of the modulation signal is
Is added as +1 and “0” is added as −1), which varies depending on the method. That is, when calculating the DSV in the process of parallel processing, different calculation methods must be adopted for the NRZ conversion and the NRZI conversion, as shown in FIGS. 5 and 4.

By the way, recently, I-NRZI (interleaved NR) using exclusive logic around two clock periods is used.
ZI) transformation may be adopted. Figure 7 shows I-NRZ
It is a block diagram which shows an I conversion circuit.

Input data is given to the exclusive OR circuit 27. The output of the exclusive OR circuit 27 is given to the exclusive OR circuit 27 via the delay devices 28 and 29. The modulated output bn for the input symbol an is delayed by 2 bits, and the exclusive OR circuit 27 obtains the exclusive OR of the input symbol an and the output symbol bn-2 which is two bits before and outputs it as the output bn. However, the DS of this I-NRZI modulated signal
A method of calculating V in the process of parallel processing has not been considered, and when I-NRZI modulation is adopted, there is a problem that DSV must be calculated for a bit serial modulation signal.

[0031]

As described above, the above-described conventional digital modulator does not provide a method for calculating the DSV of a modulated signal by I-NRZI conversion in the process of parallel processing, and serial processing. In the process of
There is a problem that the SV has to be calculated and the circuit operation becomes high speed.

It is an object of the present invention to provide a digital modulator capable of slowing the circuit operation by calculating the DSV of a modulated signal by I-NRZI conversion in the process of parallel processing. .

[Constitution of Invention]

A digital modulation apparatus according to the present invention converts an input modulated signal into serial data and then I-NRZI converts and outputs the I-NRZ.
I conversion means, dividing means for dividing the modulated signal into first parallel data consisting of a first bit group every other bit and second parallel data consisting of another second bit group, and NRZI the first or second parallel data
Polarity discriminating means for discriminating the polarity at the end of each code after conversion and CDS for NRZI conversion of the first parallel data are stored, and polarities based on the discrimination result of the polarity discriminating means are stored. The first table for outputting the CDS and the second parallel data by N
A second table that stores the CDS in the case of RZI conversion and outputs the CDS with the polarity based on the determination result of the polarity determination means, and the C from the first and second tables.
DS is added, and the addition result is cyclically added to
DSV for obtaining the DSV of the modulated signal from the RZI conversion means
It is provided with a cyclic addition means.

[0034]

In the present invention, the dividing means divides the bit-parallel input modulated signal into the first parallel data consisting of the first bit group every other bit and the second parallel data consisting of the other second bit group. Split into and. The first and second tables are provided with data indicating the polarity at the end of the code immediately before the NRZI conversion of the first or second parallel data from the polarity determination means, and the polarity based on the polarity determination result. The CDS of is output. The cyclic addition means adds a CDS from the first and second tables to a CD when the modulated signal is I-NRZI converted.
S is obtained, and this CDS is cyclically added to obtain DSV.

[0035]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a digital modulator according to the present invention. This embodiment shows an example in which an 8-bit modulated signal is I-NRZI converted and output.

First, the modulation data for I-NRZI conversion will be described using mathematical expressions.

If the output symbol is bn for the n-th symbol an input to the I-NRZI conversion circuit, the following equation (6) is established.

Bn = an @ bn-2 = an @ (an-2 @ bn-4) (6) The DSV is given by the following equation (7).

DSV = b1 ▼ b2 ▼ b3 ▼ ... ▼ b13 ▼ b14 ▼ b15 ▼ b16 ▼ ... ▼ b28 ▼ b29 ▼ ... (7) When the equation (6) is applied to the equation (7) and summarized, the following equation ( 8) is led.

DSV = (a1 @ b-1) ▼ (a2 @ b0) ▼ (a3 @ b1) ▼ (a4 @ b2) ▼ (a5 @ b3) ... = (a1 @ b-1) ▼ (a2 @ b0) ) ▼ (a3 @ a1 @ b-1) ▼ (a4 @ a2 @ b0) ▼ (a5 @ a3 @ a1 @ b-1) ▼ ... = (a1 @ b-1) ▼ (a3 @ a1 @ b-1) ) ▼ (a5 @ a3 @ a1 @ b-1) ▼ (a7 @ a5 @ a3 @ a1 @ b-1) ▼ ... ▼ (a2 @ b0) ▼ (a4 @ a2 @ b0) ▼ (a6 @ a4 @ a2) @ B0) ▼ (a8 @ a6 @ a4 @ a2 @ b0) ▼ ... (8) As is clear from the equation (8), the IN shown in FIG.
The modulated signal output can be defined only by the initial values b-1, b0 of the delay devices 28, 29 of the RZI conversion circuit and the input symbol. Then, Equation (8) and the DS of the NRZI modulated signal
As is clear from comparison with the equation (5) showing the V operation, 1
The DSV of the NRZI modulated signal when an odd-numbered symbol, which is a symbol for every bit, is input, and the DV of the NRZI modulated signal when another even-numbered symbol is input.
The DSV of the I-NRZI modulated signal can be expressed by the sum with SV.

For this reason, in the present embodiment, the NRZI is divided for each parallel data by dividing the symbols of every other bit into the two parallel data of the first and second parallel data.
I-NRZI is calculated by calculating the sum of CDS when the conversion is performed.
The converted DSV is sought. That is, the 8-bit modulated signal inputted through the input terminal 31 is given to the dividing circuit 32, and the dividing circuit 32 makes two parallel data of every other bit of the input signal, that is, a parallel consisting of odd-numbered bits. Divide into data and parallel data consisting of even-numbered bits, and table each 4-bit parallel data.
Give to 34, 35. The tables 34 and 35 store the CDS and its inverted signal when the input 4-bit parallel data is NRZI converted, and determine whether the number of “1” s of the input 4-bit parallel data is odd or even. The polarity determination data shown is stored.

The polarity determination data from the table 34 is the exclusive OR circuit 37 of the cyclic adder 36 for determining the waveform polarity.
Give to. The output of the exclusive OR circuit 37 is given to the exclusive OR circuit 37 via the delay device 38, and the exclusive OR circuit 37
37 cyclically adds the polarity determination data from the table 34.
The result of this cyclic addition is given to the table 34 via the delay device 38. In the NRZI conversion, since the output is inverted at the bit of “1”, the original polarity is obtained by the even number of inversions (“1” is an even number), and the original polarity is obtained by the odd number of inversions (“1” is an odd number). The polarity is opposite to that of. Therefore, the output of the delay device 38 will show the polarity at the end of the code. Similarly, the polarity determination data from the table 35 is given to the exclusive OR circuit 39 of the cyclic adder 36. The output of the exclusive OR circuit 39 is given to the exclusive OR circuit 39 via the delay unit 40, and the cyclic addition result of the exclusive OR circuit 39 is sent to the table 35 via the delay unit 40.
Return to.

To the tables 34 and 35, the cyclic adder 36 gives the polarity discrimination result at the end of the immediately preceding code, and outputs the CDS having the polarity based on the discrimination result to the adder 41. The adder 41 is the C from the tables 34 and 35.
The input modulated signal is added to the I-NR by adding DS.
DSV cyclic adder 42 for CDS in ZI conversion
Output to. The DSV cyclic adder 42 includes an adder 43 and an adder
The delay unit 44 delays the output of 43 and supplies it to the adder 43. The DSV cyclic adder 42 cyclically adds the CDS from the adder 41 and outputs it to the output terminal 45 as a DSV output.

On the other hand, the modulated signal at the input terminal 31 is given to the P / S conversion circuit 33, and the P / S conversion circuit 33 converts the input 8-bit parallel data into bit-serial data and performs I-NRZI conversion. Output to circuit 46. I-NRZI
The conversion circuit 46 includes an exclusive OR circuit 47 to which the output of the P / S conversion circuit 33 is applied, a delay device 48 that delays the output of the exclusive OR circuit 47, and an exclusive OR circuit that delays the output of the delay device 48. It is composed of a delay device 49 which is provided to the circuit 47. I-
The NRZI conversion circuit 49 outputs the output of the P / S conversion circuit 33 to IN.
RZI conversion is performed and the signal is output from the delay device 49 to the output terminal 50 as a modulated signal output.

Next, the operation of the embodiment thus constructed will be described.

The 8-bit modulated signal input through the input terminal 31 is applied to the P / S conversion circuit 33 and converted into a bit serial signal. The modulation signal from the P / S conversion circuit 33 is I-NRZI converted by the I-NRZI conversion circuit 46, and the modulation signal output is output to the output terminal 50.

On the other hand, the 8-bit modulated signal is divided by the dividing circuit 32.
And parallel data composed of odd-numbered 4 bits and parallel data composed of even-numbered 4 bits. Table 34 is provided with odd-numbered 4 bits, and table 35 is provided with even-numbered 4 bits. Table 34
If the polarity at the end of the immediately preceding code is negative, the odd-numbered 4-bit parallel data is N
The CDS after RZI conversion is stored, and the inverted signal thereof is also stored. Further, the table 34 also stores polarity determination data, which is data of the number of bits of "1" of the odd-numbered 4 bits, and supplies this polarity determination data to the cyclic adder 36. The cyclic adder 36 cyclically adds the polarity determination data and outputs the cyclic addition result indicating the polarity at the end of the immediately preceding code to the table 34. The table 34 receives the cyclic addition result indicating the polarity at the end of the immediately preceding code from the cyclic adder 36, and outputs a positive or negative CDS to the adder 41 based on this polarity.

Similarly, the table 35 shows the CDS when the even-numbered 4-bit parallel data is NRZI converted,
It outputs to the adder 41 with a polarity based on the polarity at the end of the immediately preceding code. The adder 41 is a CD from the tables 34 and 35.
S is added to obtain the CDS when the 8-bit modulated signal is I-NRZI converted and output to the DSV cyclic adder 42. The DSV cyclic adder 42 sequentially receives the CDS of each term on the right side of the above equation (8) from the adder 41, and adds the adder 43 and the delay device.
Output terminal 45 by calculating DSV by cyclic addition using 44
Output from.

As described above, in this embodiment, the input modulated signal is divided into the odd-numbered bit and the even-numbered bit to divide the input modulated signal into two parallel data at every other bit, I-NRZ is obtained by calculating and adding the CDS in the case of NRZI conversion using these parallel data as input, and performing the cyclic addition of the addition results.
Since the DSV of the I-modulated signal is obtained and the DSV is calculated in the process of parallel processing, it is not necessary to speed up the circuit. For example, when the method of converting to a 14-bit signal is adopted, the DSV can be calculated at an operating speed 1/14 times as high as the case where the DSV is calculated in the process of serial processing.

FIG. 2 is a block diagram showing another embodiment of the present invention. 2, the same components as those in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted.

In the embodiment of FIG. 1, the modulated signal has an even number of bits, and the two parallel data divided by the dividing circuit 32 have the same number of bits. On the other hand, the present embodiment corresponds to the case where the number of bits of the modulated signal is an odd number. For example, if a 9-bit parallel signal is I
An example of the case of performing the -NRZI conversion will be described.

The 8-bit modulated signal is given to the conversion table 51. The conversion table 51 is adapted to convert 8-bit parallel data into 9-bit parallel data and output it to the division circuit 32 and the P / S conversion circuit 33. The division circuit 32 provides the table 53 with 5-bit parallel data consisting of odd-numbered bits of the 9-bit parallel data, and provides the table 54 with 4-bit parallel data consisting of even-numbered bits. The table 53 stores the CDS and its inversion signal when the 5-bit parallel data is NRZI converted, and outputs the polarity determination data indicating the number of “1” of the 5-bit parallel data to the cyclic adder 52. Also,
The table 54 stores the CDS and its inverted signal when 4-bit parallel data is NRZI converted, and
The polarity determination data indicating the number of “1” of the bit parallel data is output to the cyclic adder 52.

Now, a series of parallel data from the conversion table 51 is converted into symbols a1 to a9, symbols b1 to b9,
It is represented by symbols c1 to c9, .... When these parallel data are converted into serial data, the converted bit string is as shown in FIG. Figure 3
Arrows indicate symbols of every other bit, that is, one parallel data divided for DSV calculation.

As shown in FIG. 3, it is assumed that one of the parallel data consisting of every 1-bit symbol shown in the equation (8) is a collection of odd-numbered bits in the parallel data a1 to a9. Then, the parallel data b1 to b9 are a collection of even-numbered bits. Therefore, for example, the polarity at the end of the code immediately before for determining the polarity of the CDS of the even-numbered bits (arrows in FIG. 3) of the parallel data b1 to b9 is the odd-numbered last bit a9 of the parallel data a1 to a9. Must be judged by.

For this reason, in the present embodiment, the table 53 determines the polarity of the CDS based on the output of the table 54, and the table 54 determines the CDS based on the output of the table 53.
Determine the polarity of. That is, the tables 53 and 54 output the polarity determination data to the cyclic adder 52. The cyclic adder 52 cyclically adds the polarity judgment data from the table 53 by the exclusive OR circuit 37 and the delay device 38 and gives the addition result to the table 54, and the polarity judgment data from the table 54 is exclusive OR circuit 39. And the delay unit 40 performs cyclic addition and gives the addition result to the table 53.

In the embodiment constructed as described above,
The modulated signal input through the input terminal 1 is converted by the conversion table 51 into 9-bit parallel data. This 9-bit parallel data is divided into an odd-numbered bit and an even-numbered bit in the division circuit 32, and each of them is divided into the table 5
Give to 3,54. The table 53 stores the CDS and its inverted signal when the odd-numbered 5-bit parallel data is NRZI converted. The table 53 is given the cyclic addition result of the polarity determination data of the table 54. This cyclic addition result corresponds to the polarity at the end of the immediately preceding code for determining the polarity of the CDS of the odd-numbered bit,
The table 53 outputs the polarity CDS based on this cyclic addition result to the adder 41. Similarly, table 54
CD of polarity based on the cyclic addition result of 53 polarity determination data
The S is output to the adder 41. Other actions and effects are similar to those of the embodiment shown in FIG.

The present invention is not limited to the above embodiments. For example, in each of the above embodiments, the case where the number of bits of the modulated signal is an even number and the case where it is an odd number have been described. By treating the modulated signal having the number of bits by 2 data as one data, even if the modulated signal having the odd number of bits is processed by the embodiment of FIG.
It is also possible to calculate V. Further, the number of bits of "1" is added by the cyclic adder, but an adder can be built in the table.

[0058]

As described above, according to the present invention, I
By calculating the DSV of the modulated signal by one NRZI conversion in the process of parallel processing, it is possible to reduce the circuit operation speed.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a digital modulator according to the present invention.

FIG. 2 is a block diagram showing another embodiment of the present invention.

FIG. 3 is an explanatory diagram for explaining the embodiment of FIG.

FIG. 4 is a block diagram showing a conventional digital modulator.

FIG. 5 is a block diagram showing a conventional digital modulator.

FIG. 6 is a block diagram showing an NRZI conversion circuit.

FIG. 7 is a block diagram showing an I-NRZI conversion circuit.

[Explanation of symbols]

32 ... Division circuit, 33 ... P / S conversion circuit, 34, 35 ... Table, 36 ... Cyclic adder, 41 ... Adder, 42 ... DSV cyclic adder, 46 ... I-NRZI conversion circuit

Claims (1)

[Claims] 1. An I-NR for converting an input modulated signal into serial data, and then I-NRZI converting and outputting the serial data.
ZI conversion means, division means for dividing the modulated signal into first parallel data consisting of a first bit group every other bit and second parallel data consisting of another second bit group, and Polarity discriminating means for discriminating the polarity at the end of each code after the conversion when the first or second parallel data is NRZI converted, and C when the first parallel data is NRZI converted.
A first table that stores DS and outputs the CDS with a polarity based on the determination result of the polarity determination means, and a C when the second parallel data is NRZI converted.
A second table that stores DS and outputs the CDS with a polarity based on the determination result of the polarity determining means and the CDSs from the first and second tables are added, and the addition result is cyclically added. And a DSV cyclic addition means for obtaining the DSV of the modulated signal from the I-NRZI conversion means.