JPH04170086A - Printed wiring board - Google Patents
Printed wiring boardInfo
- Publication number
- JPH04170086A JPH04170086A JP29739290A JP29739290A JPH04170086A JP H04170086 A JPH04170086 A JP H04170086A JP 29739290 A JP29739290 A JP 29739290A JP 29739290 A JP29739290 A JP 29739290A JP H04170086 A JPH04170086 A JP H04170086A
- Authority
- JP
- Japan
- Prior art keywords
- resistance layer
- soldering
- soldering resistance
- solder
- printed wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000005476 soldering Methods 0.000 claims abstract description 57
- 239000000758 substrate Substances 0.000 claims description 7
- 229910000679 solder Inorganic materials 0.000 abstract description 28
- 239000004020 conductor Substances 0.000 abstract description 26
- 238000000034 method Methods 0.000 abstract description 4
- 239000004065 semiconductor Substances 0.000 abstract 1
- 239000006071 cream Substances 0.000 description 11
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3452—Solder masks
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は印刷配線板に関し、特に半田付は時の橋緒防正
対策を施した印刷配線板に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a printed wiring board, and in particular to a printed wiring board that is provided with measures to prevent bridges during soldering.
従来の印刷配線板は、第5図(a)、(b)及び第6図
に示すように、2つの導体パターン(パッド)2aの間
の間隔SがO,’7am7aに狭くなる場合、導体パタ
ーン2aの間の絶縁基板1上に導体パターン2aと接触
しないように半田付抵抗層(ソルダーレジスト)3を設
け、結果的に渭4を形成する方法や、特許第12948
18号の如く、第7図及び第8図の導体パターン〈ラン
ド)2b上に導体パターン2bと接触して、第1の半田
付抵抗層6を設け、さらに、第1の半田付抵抗層6の上
に第2の半田付抵抗層7を設ける方法が実施されてきた
。In the conventional printed wiring board, as shown in FIGS. 5(a), (b) and 6, when the distance S between two conductor patterns (pads) 2a becomes narrow to O,'7am7a, the conductor A method is disclosed in which a soldering resistance layer (solder resist) 3 is provided on an insulating substrate 1 between patterns 2a so as not to contact with the conductor pattern 2a, resulting in formation of a resistive layer 4, and Japanese Patent No. 12948
As shown in No. 18, a first soldering resistive layer 6 is provided on the conductive pattern (land) 2b of FIGS. 7 and 8 in contact with the conductive pattern 2b, and further, the first soldering resistive layer 6 A method has been implemented in which a second soldering resistive layer 7 is provided on top of the soldering resistor layer 7.
これは、同特許の訴訟における東京高等裁判所が判決し
た昭和59年行(ケ)第11号審決取消請求事件の判決
文からも明らかなように、導体パターン2bの上に半田
付けする部分を除き、第1の半田付抵抗層6を印刷し、
導体パターン2bと第1の半田付抵抗層6が接触してお
り、第5図(a)、(b)及び第6図の溝4の部分がな
いのが特徴となっている。As is clear from the judgment of the Tokyo High Court in the patent suit, Case No. 11 of 1980, in which the trial decision was requested to be rescinded, this applies except for the part soldered onto the conductor pattern 2b. , printing a first soldering resistive layer 6;
The conductive pattern 2b and the first soldering resistance layer 6 are in contact with each other, and the groove 4 shown in FIGS. 5(a), 6(b) and 6 is not present.
この従来の印刷配線板の半田付抵抗層の設は方では、近
年台頭してきた導体パターン間の間隔が0.5mm以下
の狭小ピッチ表面実装部品に対してリフロ一方式半田付
けを行なった場合に、半田ブリッジショートを防止する
効果が十分満足できなかった。This conventional method of setting the soldering resistance layer of a printed wiring board is difficult to perform when reflow one-way soldering is performed for narrow-pitch surface mount components with a spacing of 0.5 mm or less between conductor patterns, which has become popular in recent years. However, the effect of preventing solder bridge shorts was not satisfactory.
その理由は、
(1)第5図(a)、、(b)及び第6図の導体パター
ン2aの表面上に塗布されたクリーム半田(図示せず)
が半田付抵抗層3側に位置ずれを起こした場合、導体パ
ターン2aと半田付抵抗層3の両表面に半田クリームが
覆われることになり、半田クリームの加熱溶融時に、導
体パターン2aの間で半田8により半田ブリッジするこ
とが起きる。これは、渭4の深さdが半田付抵抗層3の
厚さであり、通常、数μm〜20μm程度と薄いため、
半田切れが悪いことに起因している。The reason for this is: (1) Cream solder (not shown) applied on the surface of the conductor pattern 2a in FIGS. 5(a), 6(b) and 6.
If the soldering resistor layer 3 is misaligned, both surfaces of the conductor pattern 2a and the soldering resistor layer 3 will be covered with solder cream, and when the solder cream is heated and melted, the solder cream will be dislocated between the conductor patterns 2a. Solder bridging occurs due to the solder 8. This is because the depth d of the edge 4 is the thickness of the soldering resistance layer 3, which is usually as thin as several μm to 20 μm.
This is caused by poor solder cutting.
(2)第7図(a)、(b)の印刷配線板では、主にフ
ロ一方式半田付けの半田ブリッジショートを防止する目
的に供されてきたが、リフロ一方式の半田付けに適用す
ると、導体パターン2bの表面上に塗布されたクリーム
半田(図示せず)が第2の半田付抵抗層7側に位置ずれ
を起した場合、第6図に示すような溝4がないので半田
切れか行なわれないこと。(2) The printed wiring boards shown in Figures 7(a) and (b) have been mainly used for the purpose of preventing solder bridge shorts in flow-through one-way soldering, but when applied to reflow-flow one-way soldering, If the cream solder (not shown) applied on the surface of the conductor pattern 2b is misaligned toward the second soldering resistance layer 7, the solder will break because there is no groove 4 as shown in FIG. or what is not done.
にある。It is in.
本発明の目的は、近年台頭してきた導体パターン間の間
隔が0.5mm以下の狭小ピッチ表面実装部品に対して
リフロ一方式半田付けを行った場合でも半田ブリッジシ
ョートが発生しない印刷配線板を提供することにある。An object of the present invention is to provide a printed wiring board in which solder bridge shorts do not occur even when reflow one-way soldering is performed for narrow-pitch surface mount components with a spacing of 0.5 mm or less between conductor patterns, which has become popular in recent years. It's about doing.
本発明は、絶縁基板上に導体パターンを形成し該導体パ
ターンの形成表面に部品を搭載し該部品のリードを半田
付けする印刷配線板において、前記絶縁基板の同一平面
上で対向する2つの前記導体パターンの間の間隔が0.
5w1II以下の部分の前記絶縁基板上に前記導体パタ
ーンに接触しないように第1の半田付抵抗層を設け、か
つ、前記第1の半田付抵抗層の上に前記導体パターンに
接触しないように第2の半田付抵抗層を被覆し前記導体
パターンと前記第2の半田付抵抗層の間に溝が形成され
ている。The present invention provides a printed wiring board in which a conductor pattern is formed on an insulating substrate, components are mounted on the surface of the conductor pattern, and leads of the components are soldered. The spacing between conductor patterns is 0.
A first soldering resistance layer is provided on the insulating substrate in a portion of 5W1II or less so as not to contact the conductor pattern, and a first soldering resistance layer is provided on the first soldering resistance layer so as not to contact the conductor pattern. A groove is formed between the conductive pattern and the second soldering resistive layer.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第1図(a)、(b)は本発明の第1の実施例の要部平
面図及びその断面図である。FIGS. 1(a) and 1(b) are a plan view and a sectional view of a main part of a first embodiment of the present invention.
第1の実施例は、第1図(a)、(b)に示すように、
導体パターン2aの間の間隔Sが0.5■l以下で、導
体パターン2a間に第5図(a)。The first embodiment, as shown in FIGS. 1(a) and (b),
The spacing S between the conductor patterns 2a is 0.5 μl or less, and the distance between the conductor patterns 2a is as shown in FIG. 5(a).
(b)に示す従来の印刷配線板の導体パターン2aの間
め絶縁基板1上の半田付抵抗層3に相当する幅Wの第1
の半田付抵抗層6を設け、この第1の半田付抵抗層6の
上に第1の半田付抵抗層6の幅Wと同一幅で導体パター
ン2aに接触しないように第2の半田付抵抗層7を設け
たものである。The first width W corresponding to the soldering resistance layer 3 on the insulating substrate 1 between the conductive patterns 2a of the conventional printed wiring board shown in (b)
A second soldering resistance layer 6 is provided on the first soldering resistance layer 6, and a second soldering resistance layer 6 is provided on the first soldering resistance layer 6 with the same width as the width W of the first soldering resistance layer 6 so as not to contact the conductive pattern 2a. A layer 7 is provided.
この第2の半田付抵抗層7は通常、第1の半田付抵抗層
6の印刷後、文字印刷するマーキング工程で同時に形成
することができる。This second soldering resistance layer 7 can usually be formed at the same time as the printing of the first soldering resistance layer 6 in a marking process of printing characters.
この結果、導体パターン2aと第2の半田付抵抗層7と
の間には第1の半田付抵抗層6の厚さ、プラス、第2の
半田付抵抗層7の厚さからなる深さd(通常、数10μ
m以上)の深い渭4が形成できる。As a result, there is a depth d between the conductive pattern 2a and the second soldering resistance layer 7, which is the thickness of the first soldering resistance layer 6 plus the thickness of the second soldering resistance layer 7. (Usually, several tens of μ
m or more) can be formed.
第2図は第1図(a)、(b)の印刷配線板に部品リー
ドを半田付けした断面図である。FIG. 2 is a sectional view of component leads soldered to the printed wiring board of FIGS. 1(a) and 1(b).
第2図に示すように、導体パターン2aの表面上に塗布
されるクリーム半田(図示せず)が第2の半田付抵抗層
7側に位置ずれを起こしても、深さdの深い溝4の中に
クリーム半田がはいり込むことや、半田クリームの加熱
溶融時、深さdの深い溝4で半田切れを起こすことで、
結果的に導体パターン2aの間では半田8による半田ブ
リッジが生じない、第2の半田付抵抗層7の長さは、導
体パターン2aの長さ程度以上あれば十分てある。As shown in FIG. 2, even if the cream solder (not shown) applied on the surface of the conductor pattern 2a is displaced toward the second soldering resistance layer 7, the deep groove 4 with a depth d When the solder cream gets into the groove, and when the solder cream is heated and melted, the solder breaks in the deep groove 4 with a depth of d.
As a result, the length of the second soldering resistance layer 7 that does not cause solder bridges due to the solder 8 between the conductor patterns 2a is sufficient if it is approximately equal to or longer than the length of the conductor patterns 2a.
第3図(a)、(b)は本発明の第2の実施例の要部平
面図及びその断面図である。FIGS. 3(a) and 3(b) are a plan view and a sectional view of a main part of a second embodiment of the present invention.
第2の実施例は、第3図(a>、(b)に示すように、
第1図<a)、(b)の第1の実施例と基本構造が同じ
であるが、第2の半田付抵抗層7の幅W1が第1の半田
付抵抗層6の幅W2より短いことが異なる。In the second embodiment, as shown in FIG. 3 (a>, (b)),
The basic structure is the same as that of the first embodiment shown in FIGS. Things are different.
この場合、溝4の形状は階段状になり、第1の実施例と
同様にクリーム半田の加熱溶融時には、半田切れが良い
ことが特徴となる。In this case, the groove 4 has a step-like shape, and is characterized by good solder cutting when the cream solder is heated and melted, as in the first embodiment.
また、第2の半田付抵抗層7を文字印刷で形成した場合
、幅Wlが第1の半田付抵抗層6の幅半田付抵抗層7の
印刷位置ずれが許容される。Further, when the second soldering resistive layer 7 is formed by character printing, a printing position shift of the soldering resistive layer 7 whose width Wl is equal to the width of the first soldering resistive layer 6 is allowed.
第4図は本発明の第3の実施例の要部断面図である。FIG. 4 is a sectional view of a main part of a third embodiment of the present invention.
第3の実施例は、第4図に示すように、導体パターン2
a近傍の第1の半田付抵抗層6の周囲に第2の半田付抵
抗層7を形成したものである。この場合には、7114
の第2の半田付抵抗層7側の形状は、通常の文字印刷で
形成するので、インクのだれが起こりスロープ状になる
。また、溝4の形状は直角状でもよい。いずれの渭4の
形状でも、第1.第2の実施例と同様に深い渭4がある
ことで、クリーム半田の加熱溶融時の半田切れが良好で
ある。In the third embodiment, as shown in FIG.
A second soldering resistance layer 7 is formed around the first soldering resistance layer 6 near point a. In this case, 7114
Since the shape of the second soldering resistance layer 7 side is formed by normal character printing, the ink drips and becomes slope-like. Moreover, the shape of the groove 4 may be a right angle. Regardless of the shape of the arm 4, the first. As in the second embodiment, the presence of the deep edges 4 allows for good solder breakage when the cream solder is heated and melted.
以上説明したように本発明は、導体パターンに接触しな
いにように、第2の半田付抵抗層を設けることにより、
深い溝を形成したので、リフロー方式の半田付けにおけ
る半田クリームの多少の印刷ずれや過供給に対して半田
ブリッジショートを防止できるという効果を有する。As explained above, the present invention provides the second soldering resistance layer so as not to contact the conductor pattern.
Since the deep grooves are formed, it is possible to prevent solder bridge short circuits due to slight printing misalignment or oversupply of solder cream during reflow soldering.
第1図(a)、(b)は本発明の第1の実施例の要部平
面図及びその断面図、第2図は第1図(a)、(b)の
印刷配線板に部品リードを半田付けした断面図、第3図
(a)、(b)は本発明の第2の実施例の要部平面図及
びその断面図、第4図は本発明の第3の実施例の要部断
面図、第5図(a)、(b)は従来の印刷配線板の一例
の要部平面図及びその断面図、第6図は第5図(a)、
(b)の印刷配線板に部品リードを半田付けした断面図
、第7図は従来の印刷配線板の他の例の平面図、第8図
は第7図の印刷配線板に部品を搭載した断面図である。
1・・・絶縁基板、2.2a、2b・・・導体パターン
、3・・・半田付抵抗層、4・・・溝、5・・・スルー
ホール、6・・・第1の半田付抵抗層、7・・・第2の
半田付抵抗層、8・・・半田、9・・・部品、10・・
・部品リード。FIGS. 1(a) and (b) are a plan view and a sectional view of the main parts of the first embodiment of the present invention, and FIG. 2 is a component lead on the printed wiring board of FIGS. 1(a) and (b). FIGS. 3(a) and 3(b) are plan views and sectional views of essential parts of the second embodiment of the present invention, and FIG. 4 is a schematic diagram of the third embodiment of the present invention. 5(a) and 5(b) are a plan view of essential parts of an example of a conventional printed wiring board and its sectional view; FIG. 6 is a partial sectional view; FIG. 5(a),
(b) is a cross-sectional view of component leads soldered to the printed wiring board, Figure 7 is a plan view of another example of a conventional printed wiring board, and Figure 8 is a diagram showing components mounted on the printed wiring board of Figure 7. FIG. DESCRIPTION OF SYMBOLS 1... Insulating board, 2.2a, 2b... Conductor pattern, 3... Soldering resistance layer, 4... Groove, 5... Through hole, 6... First soldering resistor layer, 7... second soldering resistance layer, 8... solder, 9... component, 10...
・Parts lead.
Claims (1)
形成表面に部品を搭載し該部品のリードを半田付けする
印刷配線板において、前記絶縁基板の同一平面上で対向
する2つの前記導体パターンの間の間隔が0.5mm以
下の部分の前記絶縁基板上に前記導体パターンに接触し
ないように第1の半田付抵抗層を設け、かつ、前記第1
の半田付抵抗層の上に前記導体パターンに接触しないよ
うに第2の半田付抵抗層を被覆し前記導体パターンと前
記第2の半田付抵抗層の間に溝を形成したことを特徴と
する印刷配線板。In a printed wiring board in which a conductive pattern is formed on an insulating substrate, a component is mounted on the formed surface of the conductive pattern, and a lead of the component is soldered, between two conductive patterns facing each other on the same plane of the insulating substrate. A first soldering resistance layer is provided on the insulating substrate in a portion where the interval between
A second soldering resistive layer is coated on the soldering resistive layer so as not to contact the conductive pattern, and a groove is formed between the conductive pattern and the second soldering resistive layer. Printed wiring board.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP29739290A JPH04170086A (en) | 1990-11-02 | 1990-11-02 | Printed wiring board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP29739290A JPH04170086A (en) | 1990-11-02 | 1990-11-02 | Printed wiring board |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH04170086A true JPH04170086A (en) | 1992-06-17 |
Family
ID=17845899
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP29739290A Pending JPH04170086A (en) | 1990-11-02 | 1990-11-02 | Printed wiring board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH04170086A (en) |
-
1990
- 1990-11-02 JP JP29739290A patent/JPH04170086A/en active Pending
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