JPH02148884A - Electronic component mounting land and formation thereof - Google Patents
Electronic component mounting land and formation thereofInfo
- Publication number
- JPH02148884A JPH02148884A JP63303256A JP30325688A JPH02148884A JP H02148884 A JPH02148884 A JP H02148884A JP 63303256 A JP63303256 A JP 63303256A JP 30325688 A JP30325688 A JP 30325688A JP H02148884 A JPH02148884 A JP H02148884A
- Authority
- JP
- Japan
- Prior art keywords
- electronic component
- component mounting
- mounting land
- land
- solder paste
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000015572 biosynthetic process Effects 0.000 title description 3
- 239000004020 conductor Substances 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 238000000034 method Methods 0.000 claims description 13
- 229910000679 solder Inorganic materials 0.000 abstract description 16
- 238000005476 soldering Methods 0.000 abstract description 5
- 238000007747 plating Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 5
- 239000011521 glass Substances 0.000 description 5
- 238000007639 printing Methods 0.000 description 3
- 239000003795 chemical substances by application Substances 0.000 description 2
- 238000006073 displacement reaction Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 238000005096 rolling process Methods 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3442—Leadless components having edge contacts, e.g. leadless chip capacitors, chip carriers
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4007—Surface contacts, e.g. bumps
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野コ
本発明は、電子部品を搭載する電子部品搭・残ランドと
その形成方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an electronic component board/remaining land on which electronic components are mounted, and a method for forming the same.
［従来の技術］
近年、実装密度を向上させるために表面実装が行なわれ
、円筒形や角型のコンデンサや抵抗等のリードレス電子
部品が、回路基板上に形成された導体パターン及び電子
部品搭載ランドに実装されるようになった。[Prior art] In recent years, surface mounting has been carried out to improve packaging density, and leadless electronic components such as cylindrical and square capacitors and resistors are mounted on conductor patterns and electronic components formed on circuit boards. Now implemented in Land.
リードレス電子部品は、予め半田ペーストをスクリーン
印刷等の手段によって塗布した回路基板面上の電子部品
搭載ランドにマウントしたあと、リフロー炉を通しで半
田付けされる。Leadless electronic components are mounted on electronic component mounting lands on a circuit board surface to which solder paste has been applied in advance by means such as screen printing, and then soldered through a reflow oven.
このような場合、−船釣に使用される電子部品搭載ラン
ドは、第６図に示すようなものである。回路基板ａ上に
形成される電子部品搭載ランド６とこれと接続する導体
パターン１は、通常、回路基板Ωの製造工程において、
ＰＩ数回のメツキ後エツチングを行うことにより、ある
いは複数回の印刷を繰り返すことにより形成される。ま
た、図示されてはいないが、基板ａ上にクロスオーバ一
部分がある場合には、導体パターンｌを印刷し、その上
に絶縁体としでクロスガラスを印刷した後、さらにこの
クロスガラス上に導体を印刷する。同じく図示されてい
ないが、基板ａ上にスルーホールがある場合には、メツ
キまたは印刷、吸引によりスルーホール部分に導体を形
成する。In such a case, the electronic component mounting land used for boat fishing is as shown in FIG. The electronic component mounting land 6 formed on the circuit board a and the conductive pattern 1 connected thereto are usually formed in the manufacturing process of the circuit board Ω.
The PI is formed by performing etching after plating several times, or by repeating printing multiple times. Although not shown in the figure, if there is a portion of the crossover on the substrate a, the conductor pattern l is printed, a cross glass is printed on it as an insulator, and then a conductor is printed on the cross glass. print. Although not shown, if there is a through hole on the substrate a, a conductor is formed in the through hole portion by plating, printing, or suction.
しかし、第６図のような電子部品搭載ランド６の形状で
は、特に、円筒状のり一ドレス電子部品５をマウントし
た時、第７図のように電子部品５が転がったりズしたり
することがある。However, with the shape of the electronic component mounting land 6 as shown in FIG. 6, especially when the cylindrical glue-less electronic component 5 is mounted, the electronic component 5 may roll or slide as shown in FIG. be.
この場合、電子部品６はズしたまま半田付けされること
になり、接触不良やシｍ −トの原因となる。In this case, the electronic component 6 will be soldered while being loose, which may cause poor contact or shims.
このような問題を解決するために、例えば実開昭６３−
１０６１７１号のような手段が既に提案されている。こ
れは第８図、第９図のように、電子部品ｋｔ 戦ランド
６の中央部分にＵ字状の切り欠は部分７を設けて、リー
ドレス電子部品５を安定的にマウントできるようにした
ちのである。In order to solve such problems, for example,
Measures such as No. 106171 have already been proposed. As shown in FIGS. 8 and 9, a U-shaped notch 7 is provided in the center of the electronic component kt battle land 6 so that the leadless electronic component 5 can be stably mounted. It is.
［発明が解決しようとする課題］
上記のような従来例の改善例において、第８図のように
電子部品５が電子部品搭載ランド６中央部分に設けられ
た切り欠は部分７土に収まるように搭載された場合には
問題は生じない。[Problems to be Solved by the Invention] In the improvement example of the conventional example as described above, as shown in FIG. There will be no problem if it is installed in
しかし、第９図のように電子部品５が、ｌ；ＩＪり欠は
部分７を挟んで両側に対峙した電子部品搭載ランド６の
縁部上にズしでマウントされた場合、その位置にそのま
ま半田付けされることになる。However, if the electronic component 5 is mounted on the edge of the electronic component mounting land 6 facing on both sides with the IJ notch 7 in between as shown in FIG. 9, it will remain in that position. It will be soldered.
こうした場合は、切り欠は部分７を設けたことが、電子
部品搭載ランド６の有効面積を狭くすることから、逆効
果となり、前記従来例と同様、接触不良やシロートの原
因となってしまう。In such a case, the provision of the cutout portion 7 narrows the effective area of the electronic component mounting land 6, which has the opposite effect, resulting in poor contact and erosion, as in the prior art example.
従って、上記従来技術においては、電子部品５を電子部
品を６戦ランド６上にマウントする場合に、第７図及び
第９図のように電子部品搭載ランド６上の縁部にズしで
マウントされると、何れの場合も、これが原因となって
接触不良やシ四−トを引き起こしでいた。Therefore, in the above conventional technology, when mounting the electronic component 5 on the sixth land 6, it is necessary to mount the electronic component 5 on the edge of the electronic component mounting land 6 as shown in FIGS. 7 and 9. In either case, this caused contact failure and seat failure.
そこで、本発明は、上記の問題点を解決するために、リ
ードレス電子部品を電子部品搭載ランド上にマウントす
る際にズレ難クシ、また、ズレが生じても半田付けを行
なう際にズレを修正するように接合強度の高い電子部品
１６載ランドとその形成方法を提供することを目的とす
る。Therefore, in order to solve the above-mentioned problems, the present invention has been developed to prevent leadless electronic components from shifting when mounted on electronic component mounting lands, and to prevent misalignment during soldering even if misalignment occurs. It is an object of the present invention to provide a land for mounting an electronic component 16 with high bonding strength and a method for forming the same.
［課題を解決するための手段］
すなわち、本発明は、第一に、絶縁基板ａ上に対向しで
形成された一対の導体膜からなる電子部品搭載ランド６
において、上記導体膜の中央部分に、凹状の溝２を互い
に対向するよう設けたことを特徴とする電子部品搭載ラ
ンドを提供する。[Means for Solving the Problems] That is, the present invention first provides an electronic component mounting land 6 consisting of a pair of conductor films formed facing each other on an insulating substrate a.
Provided is an electronic component mounting land characterized in that concave grooves 2 are provided in the central portion of the conductive film so as to face each other.
さらに第二に、絶縁基板ａ上に導体膜を形成する工程を
複数回経ることにより、上記絶縁基板ａ上に対向する一
対の電子部品搭載ランド６を形成する方法において、電
子部品搭載ランド６の全面に亙って導電膜を形成する第
一の導電膜６ａの形成工程と、上記導体膜の中央部分の
互いに対向する部分２を除いて、その上の他の部分３に
導体膜を形成する第二の導電膜６ｂの形成工程を有する
ことを特徴とする電子部品搭載ランド形成方法を提供す
る。Furthermore, secondly, in the method of forming a pair of opposing electronic component mounting lands 6 on the insulating substrate a by passing through the step of forming a conductive film on the insulating substrate a multiple times, the electronic component mounting lands 6 are A step of forming a first conductive film 6a in which a conductive film is formed over the entire surface, and a conductive film is formed on other parts 3 on the central part of the conductor film except for the mutually opposing parts 2. A method for forming an electronic component mounting land is provided, which includes a step of forming a second conductive film 6b.
［作 用コ
上記本発明による電子部品搭載ランドとその形成方法に
よれば、第３図のように、電子部品５が電子部品ｔ′６
載ランド６上の縁部３にズしでマウントされても、該電
子部品！’６ Ｍランド６の凹部２に転がり込み、ある
いは嵌まり込むことによって、第２図のように中央に位
置決めされる。そしで、四部２に塗布された半田ペース
ト４によって、電子部品搭載ランド６上に電子部品５が
平面的な電子部品搭載ランドに比べて、より強固に固定
される。[Function] According to the electronic component mounting land and its forming method according to the present invention, as shown in FIG.
Even if it is mounted on the edge 3 on the mounting land 6, the electronic component! '6 By rolling or fitting into the recess 2 of the M land 6, it is positioned at the center as shown in FIG. Then, the electronic component 5 is more firmly fixed on the electronic component mounting land 6 by the solder paste 4 applied to the four parts 2 compared to a flat electronic component mounting land.
また、電子部品搭載ランド６に塗布された半田ペースト
４は、該電子部品搭載ランド６の縁部３に塗布された■
よりも、窪んだ四部２に塗布された伍が多い。このため
、次工程においてリフロー炉内で半田付けされる場合に
、半［ロペーストの持つ表面張力によって電子部品５を
引きつける力が、電子部品搭載ランド６の縁部３に塗布
された半田ペースト４より、電子部品搭載ランド６の凹
部２に塗布された半［■ペースト４の方が強い。その結
果としで、第３図のように、電子部品５が電子部品！Ｖ
ｒ戦ランド６上の縁部３に多少ズしでマウントでも、半
田１ベーストの持つ密着性により、電子部品５が、電子
部品搭載ランド６の凹部２に塗布された半田ペースト４
によって引きつけられ、第２図のようにその位置が自ず
と修正される。Furthermore, the solder paste 4 applied to the electronic component mounting land 6 is applied to the edge 3 of the electronic component mounting land 6.
There are more gou coated on the four concave parts 2. Therefore, when soldering is performed in a reflow oven in the next process, the force that attracts the electronic component 5 due to the surface tension of the semi-solid paste is stronger than the solder paste 4 applied to the edge 3 of the electronic component mounting land 6. , the half paste 4 applied to the recess 2 of the electronic component mounting land 6 is stronger. As a result, as shown in Figure 3, the electronic component 5 is an electronic component! V
Even if the electronic component 5 is mounted with some misalignment on the edge 3 on the land 6, the adhesion of the solder 1 base will allow the electronic component 5 to stick to the solder paste 4 applied to the recess 2 of the electronic component mounting land 6.
, and its position is automatically corrected as shown in Figure 2.
以上のような作用を奏する第一の手段による電子部品搭
載ランドは、本発明の第二の手段により、複数回の導体
形成工程の中で同時に、しかも比較的ｎ単に形成するこ
とができ、特別多くの工程を必要としない。By means of the second means of the present invention, the land for mounting electronic components according to the first means that exhibits the above-mentioned effects can be formed at the same time in a plurality of conductor forming steps, and moreover, in a relatively simple manner. Does not require many steps.
［実 施 例コ
次に、図面を参照にしながら、本発明の実施例を工程に
従って説明する。[Example] Next, an example of the present invention will be described step by step with reference to the drawings.
（実施例１）
まず、第４図のように、アルミナ基板ａ」二に導体（Ａ
ｇ−Ｐｄ）をスクリーン印刷し、導体パターン１及び電
子部品搭載・ランド６の形成区域の全面に第一の導電膜
６ａを形成した。その後、図示されてはいないが、導体
のクロス部分に絶縁性のクロスガラスを印刷によって形
成した。続いて、前記クロスガラスを印刷した部分、及
び第４図のように電子部品搭載ランド６の下層部としで
形成した上記第一の導電膜６ａの」二に、第５図のよう
に、その中央部分の互いの延長線がほぼ一致する部分を
除いて、第二の導電膜６ｂを形成した。その結果、電子
部品搭載ランド６の下部の対向する部分に、凹状の溝２
が一対形成された。(Example 1) First, as shown in Fig. 4, a conductor (A
g-Pd) was screen printed to form a first conductive film 6a on the entire surface of the formation area of the conductor pattern 1 and the electronic component mounting/land 6. Thereafter, although not shown, insulating cross glass was formed on the cross portions of the conductors by printing. Next, as shown in FIG. 5, on the part where the cross glass was printed and the first conductive film 6a formed as the lower layer of the electronic component mounting land 6 as shown in FIG. A second conductive film 6b was formed except for the central portion where the extension lines substantially coincided with each other. As a result, a concave groove 2 is formed in the opposing lower part of the electronic component mounting land 6.
A pair was formed.
（実施例２）
両面に膜厚３５μｍでＣｕ膜が形成されたガラスエポキ
シ基板８を用意し、図示されてはいないが、スルーホー
ル部分及びリード線種大部分に挿入孔を設ける。その後
、無電解Ｃｕメツキを全面に施し、さらに、電解Ｃｕメ
ツキを全面に施した。以上の工程により、スルーホール
内周面、リード線種大穴内周面及び基板ａの主面にＣｕ
膜からなる第一の導電膜６ａを形成した。(Example 2) A glass epoxy substrate 8 on which a Cu film with a thickness of 35 μm is formed on both sides is prepared, and although not shown, insertion holes are provided in the through-hole portion and most of the lead wire types. Thereafter, electroless Cu plating was applied to the entire surface, and electrolytic Cu plating was further applied to the entire surface. Through the above steps, Cu is applied to the inner circumferential surface of the through hole, the inner circumferential surface of the large hole of the lead wire type, and the main surface of the substrate a.
A first conductive film 6a made of a film was formed.
続いて、′ｙＦＳ６図のように、電子部品搭・戒ランド
６の縁部３となる部分と導体パターン１となる部分を除
いて、上記第一の導電膜６ａ上にメツキレジストを塗布
し、Ｃｕメツキを施した。Subsequently, as shown in Fig.'yFS6, a plating resist is applied on the first conductive film 6a except for the portion that will become the edge 3 of the electronic component tower/prevention land 6 and the portion that will become the conductor pattern 1. Cu plating was applied.
これにより、上記メツキレジストの塗布されなかった部
分に、導体パターン１と電子部品ｒ４ｉＩｉｌｉランド
６の縁部３を形成する第二の導電膜６ｂが７０μｍの膜
厚で形成される。As a result, the second conductive film 6b, which forms the conductor pattern 1 and the edge 3 of the electronic component land 6, is formed with a film thickness of 70 μm on the portion where the plating resist is not applied.
さらに、第７図のように、上記工程で形成された導体パ
ターンｌと電子部品搭載ランド６のパターン全面にエツ
チングレジストを塗布し、基板ａ上のＣｕ膜をエツチン
グする。これによって、最初に基板ａの全面に亙って形
成された第一の導電膜６ａがパターン化され、対向する
凹状の溝２を仔する電子部品搭載ランド６が形成された
。Furthermore, as shown in FIG. 7, an etching resist is applied to the entire surface of the conductor pattern 1 and the electronic component mounting land 6 formed in the above steps, and the Cu film on the substrate a is etched. As a result, the first conductive film 6a, which was initially formed over the entire surface of the substrate a, was patterned, and an electronic component mounting land 6 having opposing concave grooves 2 was formed.
上記２つの実施例のようにしで作製された電子部品ｔ３
ｉｆ！ランド６上に半田ペースト４を塗布し、その上
に、リードレス電子部品５を自動マウンｉ・機を使用し
でマウントした。この時、第３図のように電子部品搭載
ランド６の縁部３−ににズしでマウントされた場合であ
っても、次の半田付けされる工程において、電子部品塔
・戒ランド６の凹部２に塗布された半田ペースト４の持
つ表面張力と密普性によって、いずれもマウントズレを
修正することができた。Electronic component t3 made using Hoshi as in the above two examples
If! Solder paste 4 was applied onto land 6, and leadless electronic component 5 was mounted thereon using an automatic mounting machine. At this time, even if the electronic component is mounted on the edge 3- of the electronic component mounting land 6 as shown in FIG. Due to the surface tension and compactness of the solder paste 4 applied to the recess 2, mounting misalignment could be corrected in both cases.
上記各実施例で示した所望の目的を達成できる電子部品
搭載ランド６の凹状の溝２の形状は、図面に示すような
形状に限られる訳ではない。The shape of the concave groove 2 of the electronic component mounting land 6 that can achieve the desired objectives shown in each of the above embodiments is not limited to the shape shown in the drawings.
さらに、本発明は、電子部品ｒ４ｉ！！ランド６上にマ
ウントされるリードレス電子部品５の形状としで、実施
例で使用した円筒形電子部品に限られることなく、角型
電子部品でも同様な効果が期待できることは言うまでも
ない。Furthermore, the present invention provides an electronic component r4i! ! It goes without saying that the shape of the leadless electronic component 5 mounted on the land 6 is not limited to the cylindrical electronic component used in the embodiment, and similar effects can be expected with a rectangular electronic component.
［発明の効果コ
以上説明した通り、本発明による電子部品搭載ランド６
によれば、リードレス電子部品５を該電子部品搭載ラン
ド６上にマウントする際、電子部品搭載ランド６の中央
部分に形成された四部２の存在によってマウントズレを
起し難く、しかも、マウントズレがあっても、半田付け
を行なう工程で、電子部品搭載ランド６の凹部２に塗布
された半田ペースト４の表面張力、！−密着性によって
マウントズレが修正される。さらに、電子部品搭載ラン
ド６の凹部２にマウントされたリードレス電子部品５は
、電子部品搭載ランド６の凹部２」二に塗布された半田
ペースト４によって安定的に固定されるため、より接合
強度が増すと（１う効果を得ることができる。[Effects of the Invention] As explained above, the electronic component mounting land 6 according to the present invention
According to the above, when mounting a leadless electronic component 5 on the electronic component mounting land 6, the presence of the four parts 2 formed at the center of the electronic component mounting land 6 makes it difficult to cause mounting displacement, and moreover, the mounting displacement is prevented. Even if there is, the surface tension of the solder paste 4 applied to the recess 2 of the electronic component mounting land 6 during the soldering process. -Mount misalignment is corrected by adhesion. Furthermore, since the leadless electronic component 5 mounted in the recess 2 of the electronic component mounting land 6 is stably fixed by the solder paste 4 applied to the recess 2 of the electronic component mounting land 6, the bonding strength is increased. When increases, an effect of 1 can be obtained.
また、本発明による形成方法によれば、従来の工程数を
増やすことなく、比較的簡単に、しかも廉価に電子部品
ｒ６Ｉｒｉｌ！ランドを提供することができる。Moreover, according to the forming method of the present invention, electronic components r6Iril can be formed relatively easily and inexpensively without increasing the number of conventional steps. Land can be provided.
第１図（ａ）は、本発明の電子部品搭載ランドの概要を
示す平面図、第１図（ｂ）は、前記のＡ−Ａ断面図、第
２図（ｎ）は、本発明の電子部品Ｆｈ栽ラうド上にリー
ドレス電子部品を正常にマウントした状態を示す平面図
、第２図（ｂ）は、前記のＡ−Ａ断面図、第３図（ａ）
は、本発明の電子部品搭載ランド」二にリードレス電子
部品をズしでマウンドした状態を示す平面図、第３図（
ｂ）は、前記のＡ−Ａ断面図、第４図１（ｎ）は、本発
明の実施例１において電子部品搭載ランドの下部としで
第一の導電膜と導体パターンを形成した状態を示す平面
図、第４図（ｂ）は、前記のＡ−Ａ断面図、第５図（ａ
）は、前記工程後、第一の導電膜の上にさらにＵ字状の
第二の導電膜を形成し、電子部品搭載ランドを縁部と四
部に区分した状態を示す平面図、第５図（ｂ）は、前記
のＡ−Ａ断面図、第６図（ａ）は、本発明の実施例２に
おいて導体パターンと電子部品搭載ランドの縁部を形成
した状態を示す平面図、第６図（ｂ）は、前記のＡ−Ａ
断面図、第７図（ａ）は、上記工程後、ｒｕ電子部品搭
載ランド下部の対向する部分に、凹状の溝が一対形成さ
れた状態を示す平面図、第７図（ｂ）は、前記のＡ−Ａ
断面図、第８図は、従来の電子部品搭載ランドの概要を
示す平面図、第９１λ１（Ｏ）は、従来の電子部品Ｗｒ
ｉ！ｌ！ランド上にリードレス電子部品をズしでマウン
トした状態を示す平面図、第９図（ｂ）は、前記のＡ−
Ａ断面図、第１Ｏ図（ａ）は、従来例の改善例において
、電子部品搭載ランド上にリードレス電子部品を正常に
マウントした状態を示す平面図、第１０図（ｂ）は、前
記のＡ−Ａ断面図、第１１図（ａ）は、前記の電子部品
搭載ランド上にリードレス電子部品をズしでマウントズ
レた状態を示す平面図、第１１図（ｂ）は、前記のＡ−
Ａ断面図。
■・・・導体パターン ２・・・電子部品搭載ランドの
凹部 ３・・・電子部品搭載ランドの縁部 ４・・・半
田ペースト ５・・・リードレス電子部品６・・・電子
部品搭載ランド ６８・・・第一の導電ｒｆ＆ｅｂ・・
・第二の導電膜 ７・・・切り欠は部ａ・・・回路基板
特 許 出 願 人 太陽誘電株式会社代 理
人 弁理士 北條 和山手
続
補
正
書
事件の表示
昭和６３年特許願第３０３２５６号
発明の名称
電子部品搭載ランドとその形成方法
３、？ｉ正をする者
事件との関係 特許出願人
住 所 東京都台東区上野６丁目１６番２０号氏
名 太 Ｆ１４ 誘 電 株 式 会
社４、代理人
住 所 茨城県水戸市五軒町三丁目３番４０号補正命
令の日付
（自
発）
図面の浄書・別紙の通り
（内容に変更なし）FIG. 1(a) is a plan view showing an overview of the electronic component mounting land of the present invention, FIG. 1(b) is the above-mentioned AA sectional view, and FIG. FIG. 2(b) is a plan view showing the state in which the leadless electronic component is normally mounted on the component Fh storage board, and FIG. 3(a) is the sectional view taken along line A-A.
FIG.
b) is the above-mentioned AA sectional view, and FIG. 4 1(n) shows the state in which the first conductive film and conductor pattern are formed as the lower part of the electronic component mounting land in Example 1 of the present invention. The plan view, FIG. 4(b), is the above-mentioned AA sectional view, FIG.
) is a plan view showing a state in which a U-shaped second conductive film is further formed on the first conductive film after the above step, and the electronic component mounting land is divided into an edge and four parts, FIG. 6(b) is the above-mentioned AA sectional view, FIG. 6(a) is a plan view showing a state in which the conductor pattern and the edge of the electronic component mounting land are formed in Example 2 of the present invention, FIG. (b) is the above A-A
7(a) is a sectional view, and FIG. 7(b) is a plan view showing a state in which a pair of concave grooves are formed in opposing parts of the lower part of the ru electronic component mounting land after the above process. A-A of
A sectional view, FIG. 8 is a plan view showing an outline of a conventional electronic component mounting land, and No. 91λ1(O) is a conventional electronic component mounting land.
i! l! FIG. 9(b) is a plan view showing a state in which the leadless electronic component is mounted on the land by sliding it.
10(a) is a sectional view of A, and FIG. 10(a) is a plan view showing a state in which a leadless electronic component is normally mounted on an electronic component mounting land in an improved example of the conventional example, and FIG. 11(a) is a plan view showing a state in which the leadless electronic component is mounted on the electronic component mounting land, and FIG. 11(b) is a sectional view taken along the line A-A. −
A sectional view. ■...Conductor pattern 2...Concavity of electronic component mounting land 3...Edge of electronic component mounting land 4...Solder paste 5...Leadless electronic component 6...Electronic component mounting land 68 ...First conductive rf&eb...
・Second conductive film 7...The cutout is part a...Circuit board patent applicant: Taiyo Yuden Co., Ltd. Agent
Person Patent Attorney Hojo Wayama Procedural Amendment Case Display No. 1988 Patent Application No. 303256 Name of the invention Electronic component mounting land and its formation method 3.? Relationship to the i-correction case Patent applicant address: 6-16-20 Ueno, Taito-ku, Tokyo
Name: Futoshi F14 Yuden Co., Ltd. Company 4, Agent address: 3-3-40 Gokenmachi, Mito City, Ibaraki Prefecture Date of amendment order (self-imposed) As per the engraving of the drawing and attached sheet (no change in content)
Claims (2)
らなる電子部品搭載ランドにおいて、上記導体膜の中央
部分に、凹状の溝を互いに対向するよう設けたことを特
徴とする電子部品搭載ランド。(1) An electronic component mounting land consisting of a pair of conductor films formed facing each other on an insulating substrate, wherein a concave groove is provided in the center of the conductor film so as to face each other. Mounted land.
ことにより、上記絶縁基板上に対向する一対の電子部品
搭載ランドを形成する方法において、電子部品搭載ラン
ドの全面に亙って導電膜を形成する第一の導電膜形成工
程と、上記導体膜の中央部分の互いに対向する部分を除
いて、その上の他の部分に導体膜を形成する第二の導電
膜形成工程を有することを特徴とする電子部品搭載ラン
ド形成方法。(2) In a method of forming a pair of opposing electronic component mounting lands on the insulating substrate by passing through the process of forming a conductor film on the insulating substrate multiple times, the entire surface of the electronic component mounting land is conductive. A first conductive film forming step of forming a film, and a second conductive film forming step of forming a conductive film on other parts of the conductive film except for the central part facing each other. A method for forming an electronic component mounting land characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63303256A JPH02148884A (en) | 1988-11-30 | 1988-11-30 | Electronic component mounting land and formation thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63303256A JPH02148884A (en) | 1988-11-30 | 1988-11-30 | Electronic component mounting land and formation thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02148884A true JPH02148884A (en) | 1990-06-07 |
Family
ID=17918763
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63303256A Pending JPH02148884A (en) | 1988-11-30 | 1988-11-30 | Electronic component mounting land and formation thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02148884A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06174496A (en) * | 1992-09-18 | 1994-06-24 | Honda Motor Co Ltd | Optical encoder |
| CN104703406A (en) * | 2013-12-09 | 2015-06-10 | 三菱电机株式会社 | Electronic component mounting device and semiconductor device including the same |
| JP2016178202A (en) * | 2015-03-20 | 2016-10-06 | 古河電気工業株式会社 | Junction structure for circuit board and electronic component, electronic circuit board, and manufacturing method of circuit board |
-
1988
- 1988-11-30 JP JP63303256A patent/JPH02148884A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06174496A (en) * | 1992-09-18 | 1994-06-24 | Honda Motor Co Ltd | Optical encoder |
| CN104703406A (en) * | 2013-12-09 | 2015-06-10 | 三菱电机株式会社 | Electronic component mounting device and semiconductor device including the same |
| JP2015115342A (en) * | 2013-12-09 | 2015-06-22 | 三菱電機株式会社 | Electronic component packaging device, and semiconductor device comprising the same |
| US9723718B2 (en) | 2013-12-09 | 2017-08-01 | Mitsubishi Electric Corporation | Electronic component mounting device and semiconductor device including the same |
| DE102014222601B4 (en) | 2013-12-09 | 2022-05-12 | Mitsubishi Electric Corporation | Device with mounted electronic components and semiconductor device with the same |
| JP2016178202A (en) * | 2015-03-20 | 2016-10-06 | 古河電気工業株式会社 | Junction structure for circuit board and electronic component, electronic circuit board, and manufacturing method of circuit board |
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