JPH05129767A - Printed wiring board - Google Patents

Printed wiring board

Info

Publication number
JPH05129767A
JPH05129767A JP29029091A JP29029091A JPH05129767A JP H05129767 A JPH05129767 A JP H05129767A JP 29029091 A JP29029091 A JP 29029091A JP 29029091 A JP29029091 A JP 29029091A JP H05129767 A JPH05129767 A JP H05129767A
Authority
JP
Japan
Prior art keywords
mounting
wiring board
printed wiring
solder
solder bridge
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP29029091A
Other languages
Japanese (ja)
Inventor
Toshio Saotome
利夫 早乙女
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP29029091A priority Critical patent/JPH05129767A/en
Publication of JPH05129767A publication Critical patent/JPH05129767A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/11Printed elements for providing electric connections to or between printed circuits
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3447Lead-in-hole components

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

PURPOSE:To enhance a printed wiring board in soldering reliability by a method wherein solder bridges are prevented from occurring between mounting lands. CONSTITUTION:A printed wiring board 11 is provided with an insertion hole 12 where a lead terminal of a component such as an IC or the like is inserted and a mounting land 13 provided around the insertion hole 12, where solder bridge preventing parts 15 are provided to, at least, one of the mounting lands 13 provided adjacent to each other.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、IC等の極めて小さい
ピッチ間隔でリード端子をもつ部品を実装するのに適し
たプリント配線基板に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed wiring board suitable for mounting components such as ICs having lead terminals at extremely small pitch intervals.

【0002】[0002]

【従来の技術】以下、従来のIC等の極めて小さいピッ
チ間隔でリード端子をもつ部品を実装するプリント配線
基板、例えばリード端子のピッチ間隔が1.778mm
であるDIP(Dual In−line Packg
e)型シュリンクICを実装するプリント配線基板につ
いて図5とともに説明する。
2. Description of the Related Art A printed wiring board on which components having lead terminals are mounted at extremely small pitch intervals, such as conventional ICs, for example, lead terminals having a pitch interval of 1.778 mm.
DIP (Dual In-line Packg)
A printed wiring board on which the e) type shrink IC is mounted will be described with reference to FIG.

【0003】従来のプリント配線基板は、絶縁基板1に
DIP型シュリンクICのリード端子(図示せず)を挿
入する挿入孔2を設け、該挿入孔2の周辺に上記DIP
型シュリンクICのリード端子(図示せず)を半田付け
する円形の実装ランド3を設け、該実装ランド3を複数
有するとともに該複数の実装ランド3を残して全面にソ
ルダーレジストと呼ばれる半田付抵抗層4を印刷して形
成し、更に一方の実装ランド3と他方の実装ランド3の
狭間部に半田ブリッジ防止用半田付抵抗層5を印刷して
形成してなるものである。
In a conventional printed wiring board, an insertion hole 2 for inserting a lead terminal (not shown) of a DIP type shrink IC is provided in an insulating substrate 1, and the DIP is provided around the insertion hole 2.
A circular mounting land 3 for soldering a lead terminal (not shown) of a die-type shrink IC is provided, and a soldering resistance layer called solder resist having a plurality of mounting lands 3 and leaving the plurality of mounting lands 3 all over. 4 is formed by printing, and a solder bridge preventing soldering resistance layer 5 is further formed by printing between the mounting land 3 on one side and the mounting land 3 on the other side.

【0004】尚、上記構成において、挿入孔2の中心間
距離6はDIP型シュリンクICのリード端子(図示せ
ず)のピッチ間隔と同様の1.778mmであり、該挿
入孔2の孔径7を0.7mm、実装ランド3のランド径
8を1.5mmとし、一方の実装ランド3と他方の実装
ランド3間の間隔9を0.278mmとしてなるもので
ある。
In the above structure, the center-to-center distance 6 of the insertion hole 2 is 1.778 mm, which is the same as the pitch interval of the lead terminals (not shown) of the DIP type shrink IC, and the hole diameter 7 of the insertion hole 2 is The land diameter 8 of the mounting land 3 is 0.7 mm, and the space 9 between the one mounting land 3 and the other mounting land 3 is 0.278 mm.

【0005】上記のように構成してなるプリント配線基
板に、DIP型シュリンクICを実装する場合は、該D
IP型シュリンクICのリード端子(図示せず)を挿入
孔2に挿入し、次に該DIP型シュリンクICのリード
端子(図示せず)を実装ランド3に半田ディップにて半
田付けするものであるが、一方の実装ランド3と他方の
実装ランド3の狭間部の半田ブリッジ防止用半田付抵抗
層5によって半田を隔離し、上記一方の実装ランド3と
他方の実装ランド3間の半田ブリッジを防止してなるも
のである。
When a DIP type shrink IC is mounted on the printed wiring board having the above structure, the D
A lead terminal (not shown) of the IP type shrink IC is inserted into the insertion hole 2, and then a lead terminal (not shown) of the DIP type shrink IC is soldered to the mounting land 3 by solder dip. However, the solder is separated by the solder bridge preventing soldering resistor layer 5 between the one mounting land 3 and the other mounting land 3 to prevent the solder bridge between the one mounting land 3 and the other mounting land 3. It will be done.

【0006】[0006]

【発明が解決しようとする課題】しかしながら、従来の
プリント配線基板においては、半田ブリッジ防止用半田
付抵抗層の位置がずれて実装ランドを覆って印刷した場
合、該実装ランドにおける半田付け性が劣悪となった
り、また、上記半田ブリッジ防止用半田付抵抗層の印刷
が不完全な場合、しばしば上記実装ランド間の半田ブリ
ッジが発生するなど、半田付けの信頼性が乏しいという
問題がある。
However, in the conventional printed wiring board, when printing is performed by covering the mounting land with the solder bridge preventing soldering resistance layer displaced in position, the solderability on the mounting land is poor. In addition, when printing of the solder bridge preventing soldering resistance layer is incomplete, a solder bridge between the mounting lands often occurs, resulting in poor soldering reliability.

【0007】[0007]

【課題を解決するための手段】本発明にかかるプリント
配線基板は、実装ランドの少なくとも一方に半田ブリッ
ジ防止部を備えてなるものである。
A printed wiring board according to the present invention comprises a solder bridge prevention portion on at least one of mounting lands.

【0008】[0008]

【作用】本発明にかかるプリント配線基板は、実装ラン
ドに備えた半田ブリッジ防止部により、上記実装ランド
間の距離を十分に維持することができるため、確実に上
記実装ランド間の半田ブリッジを防止することができ
る。
In the printed wiring board according to the present invention, the solder bridge prevention portion provided on the mounting lands can maintain a sufficient distance between the mounting lands, so that the solder bridges between the mounting lands can be reliably prevented. can do.

【0009】[0009]

【実施例】以下、本発明のIC等の極めて小さいピッチ
間隔でリード端子をもつ部品を実装するプリント配線基
板、例えばリード端子のピッチ間隔が1.788mmで
あるDIP(Dual In−line Packg
e)型シュリンクICを実装するプリント配線基板の一
実施例について図1乃至図3とともに説明する。
EXAMPLES A printed wiring board for mounting components having lead terminals at extremely small pitch intervals such as the IC of the present invention, for example, a DIP (Dual In-Line Packg) in which the pitch intervals of the lead terminals are 1.788 mm.
An embodiment of a printed wiring board on which the e) type shrink IC is mounted will be described with reference to FIGS.

【0010】本発明のプリント配線基板は、絶縁基板1
1にDIP型シュリンクICのリード端子(図示せず)
を挿入する挿入孔12を設け、該挿入孔12の周辺に上
記DIP型シュリンクICのリード端子(図示せず)を
半田付けする実装ランド13を設け、該実装ランド13
を複数有するとともに該複数の実装ランド13を残して
全面にソルダーレジストと呼ばれる半田付抵抗層14を
印刷して形成し、更に一方の実装ランド13及び他方の
実装ランド13のそれぞれの互いに近接する部分に上記
半田付抵抗層14を印刷して形成した半田ブリッジ防止
部15を備えてなるものである。
The printed wiring board of the present invention is an insulating substrate 1.
1 is a lead terminal of the DIP type shrink IC (not shown)
Is provided with a mounting land 13 for soldering a lead terminal (not shown) of the DIP-type shrink IC, and the mounting land 13 is provided around the insertion hole 12.
And a plurality of mounting lands 13 are left, and a soldering resistance layer 14 called a solder resist is printed and formed on the entire surface, and the one mounting land 13 and the other mounting land 13 are adjacent to each other. Is provided with a solder bridge prevention portion 15 formed by printing the soldering resistance layer 14 thereon.

【0011】尚、本発明の一実施例においては、実装ラ
ンド13は横一列に近接して並んでいるものであるの
で、半田ブリッジ防止部15は該実装ランド13の両隣
りの実装ランド13と近接する部分に180°の間隔に
て備えられてなるものである。また、上記構成における
寸法値は、挿入孔12の中心間距離16がDIP型シュ
リンクICのリード端子(図示せず)のピッチ間隔と同
様の1.778mmであり、該挿入孔12の孔径17を
0.7mm、実装ランド13のランド径18を1.5m
mとし、一方の実装ランド13と他方の実装ランド13
間の間隔19は0.278mmである。
In one embodiment of the present invention, the mounting lands 13 are arranged side by side in a row, so that the solder bridge prevention portion 15 is connected to the mounting lands 13 on both sides of the mounting land 13. It is provided at intervals of 180 ° in the adjacent portions. Further, the dimension value in the above configuration is such that the center distance 16 of the insertion holes 12 is 1.778 mm, which is the same as the pitch interval of the lead terminals (not shown) of the DIP type shrink IC, and the hole diameter 17 of the insertion holes 12 is 0.7 mm, the land diameter 18 of the mounting land 13 is 1.5 m
m, one mounting land 13 and the other mounting land 13
The space 19 between them is 0.278 mm.

【0012】上記のように構成してなるプリント配線基
板に、DIP型シュリンクICを実装する場合は、該D
IP型シュリンクICのリード端子(図示せず)を挿入
孔12に挿入し、次に該DIP型シュリンクICのリー
ド端子(図示せず)を実装ランド13に半田ディップに
て半田付けするものであるが、一方の実装ランド13及
び他方の実装ランド13のそれぞれの互いに近接する部
分に備えた半田ブリッジ防止部15により、上記実装ラ
ンド13間の距離を十分に維持することができるため、
該実装ランド13間の半田ブリッジを防止してなるもの
である。
When a DIP type shrink IC is mounted on the printed wiring board having the above-mentioned structure, the D
A lead terminal (not shown) of the IP type shrink IC is inserted into the insertion hole 12, and then a lead terminal (not shown) of the DIP type shrink IC is soldered to the mounting land 13 by solder dip. However, since the solder bridge prevention portions 15 provided in the portions of the one mounting land 13 and the other mounting land 13 that are close to each other can sufficiently maintain the distance between the mounting lands 13.
The solder bridge between the mounting lands 13 is prevented.

【0013】次に、半田ブリッジ防止部15の実装ラン
ド13の法線方向長さ20を0.3mmとした場合にお
ける該半田ブリッジ防止部15の実装ランド13の接線
方向長さ21に対する半田ブリッジの発生率を図3に示
すように、上記半田ブリッジ防止部15の実装ランド1
3の接線方向長さ21が0mmのときすなわち上記半田
ブリッジ防止部15を設けないときは100%(128
箇所の実装ランド13間のうち128箇所)半田ブリッ
ジが発生するのに対し、上記半田ブリッジ防止部15の
実装ランド13の接線方向長さ21が0.1mmのとき
で約20%(128箇所の実装ランド13間のうち23
箇所)半田ブリッジが発生し、上記半田ブリッジ防止部
15の実装ランド13の接線方向長さ21が0.2mm
のときに半田ブリッジ発生率は0%(128箇所の実装
ランド13間のうち0箇所)となり、確実に半田ブリッ
ジを防止できることがわかる。
Next, when the length 20 in the normal direction of the mounting land 13 of the solder bridge prevention portion 15 is set to 0.3 mm, the solder bridge to the tangential length 21 of the mounting land 13 of the solder bridge prevention portion 15 is set. As shown in FIG. 3, the mounting land 1 of the solder bridge prevention portion 15
When the tangential length 21 of 3 is 0 mm, that is, when the solder bridge preventing portion 15 is not provided, 100% (128
While solder bridges are generated between 128 of the mounting lands 13 at the locations, about 20% (128 of the solder lands) when the tangential length 21 of the mounting land 13 of the solder bridge prevention portion 15 is 0.1 mm. 23 out of 13 mounting lands
Location) A solder bridge occurs, and the tangential length 21 of the mounting land 13 of the solder bridge prevention portion 15 is 0.2 mm.
In this case, the solder bridge occurrence rate was 0% (0 out of 128 mounting lands 13), and it can be seen that the solder bridge can be reliably prevented.

【0014】また、上記一実施例は、半田付抵抗層を実
装ランドのそれぞれの互いに近接する部分に印刷して形
成することによって半田ブリッジ防止部を備えて半田ブ
リッジを防止するものであるが、上記半田抵抗層を上記
従来例と同様に印刷して形成する場合について、以下、
本発明のプリント配線基板の他の実施例を図4とともに
説明する。
Further, in the above-mentioned one embodiment, the soldering resistance layer is provided by printing the soldering resistance layers on the portions of the mounting land adjacent to each other to prevent the soldering bridge. Regarding the case where the solder resistance layer is formed by printing as in the conventional example,
Another embodiment of the printed wiring board of the present invention will be described with reference to FIG.

【0015】尚、上記一実施例と同一部分は同一符号を
使用し、その説明を省略する。
The same parts as those in the above-described embodiment are designated by the same reference numerals, and the description thereof will be omitted.

【0016】本発明のプリント配線基板は、エッチング
等により導電パターンを形成する際、一方の実装ランド
13及び他方の実装ランド13のそれぞれの互いに近接
する部分を切り欠いてなる半田ブリッジ防止部22を備
えてなるものであり、該半田ブリッジ防止部22によ
り、上記実装ランド13間の距離を十分に維持すること
ができるため、該実装ランド13間の半田ブリッジを防
止してなるものである。
In the printed wiring board of the present invention, when the conductive pattern is formed by etching or the like, the solder bridge prevention portion 22 is formed by notching the portions of the one mounting land 13 and the other mounting land 13 which are close to each other. Since the solder bridge prevention portion 22 can maintain a sufficient distance between the mounting lands 13, the solder bridge preventing portions 22 prevent the solder bridges between the mounting lands 13.

【0017】[0017]

【発明の効果】本発明のプリント配線基板は、実装ラン
ドに備えた半田ブリッジ防止部により、上記実装ランド
間の距離を十分に維持することができるため、確実に上
記実装ランド間の半田ブリッジを防止することができ、
半田付けの信頼性を向上させることが可能である。
In the printed wiring board of the present invention, the solder bridge prevention portion provided on the mounting lands can maintain a sufficient distance between the mounting lands, so that the solder bridges between the mounting lands can be securely connected. Can be prevented,
It is possible to improve the reliability of soldering.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明のプリント配線基板の一実施例を示す要
部拡大説明図である。
FIG. 1 is an enlarged explanatory view of a main part showing an embodiment of a printed wiring board according to the present invention.

【図2】本発明のプリント配線基板の一実施例を示す概
略平面説明図である。
FIG. 2 is a schematic plan view showing an embodiment of the printed wiring board of the present invention.

【図3】本発明のプリント配線基板の一実施例の半田ブ
リッジ防止部の実装ランドの接線方向長さに対する半田
ブリッジ発生率を示す説明図である。
FIG. 3 is an explanatory diagram showing a solder bridge generation rate with respect to a tangential length of a mounting land of a solder bridge prevention portion of one embodiment of a printed wiring board of the present invention.

【図4】本発明のプリント配線基板の他の実施例を示す
要部拡大説明図である。
FIG. 4 is an enlarged explanatory view of a main part showing another embodiment of the printed wiring board according to the present invention.

【図5】従来のプリント配線基板を示す要部拡大説明図
である。
FIG. 5 is an enlarged explanatory view of a main part showing a conventional printed wiring board.

【符号の説明】[Explanation of symbols]

11 絶縁基板 12 挿入孔 13 実装ランド 15,22 半田ブリッジ防止部 11 Insulating Substrate 12 Insertion Hole 13 Mounting Land 15, 22 Solder Bridge Preventing Section

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 絶縁基板にIC等の部品のリード端子を
挿入する挿入孔を設け、該挿入孔の周辺に実装ランドを
設け、該実装ランドを複数有するとともに該実装ランド
が互いに近接してなるプリント配線基板において、該複
数の実装ランドの少なくとも一方に半田ブリッジ防止部
を備えたことを特徴とするプリント配線基板。
1. An insulating substrate is provided with an insertion hole into which a lead terminal of a component such as an IC is inserted, a mounting land is provided around the insertion hole, and a plurality of mounting lands are provided and the mounting lands are close to each other. A printed wiring board comprising a solder bridge prevention portion on at least one of the plurality of mounting lands.
JP29029091A 1991-11-07 1991-11-07 Printed wiring board Pending JPH05129767A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP29029091A JPH05129767A (en) 1991-11-07 1991-11-07 Printed wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP29029091A JPH05129767A (en) 1991-11-07 1991-11-07 Printed wiring board

Publications (1)

Publication Number Publication Date
JPH05129767A true JPH05129767A (en) 1993-05-25

Family

ID=17754229

Family Applications (1)

Application Number Title Priority Date Filing Date
JP29029091A Pending JPH05129767A (en) 1991-11-07 1991-11-07 Printed wiring board

Country Status (1)

Country Link
JP (1) JPH05129767A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002193687A (en) * 2000-12-26 2002-07-10 Nippon Tokushu Toryo Co Ltd Recoating method for extrusion-molded concrete roof- tile
JP2006114587A (en) * 2004-10-13 2006-04-27 Tohoku Ricoh Co Ltd Printed circuit board

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002193687A (en) * 2000-12-26 2002-07-10 Nippon Tokushu Toryo Co Ltd Recoating method for extrusion-molded concrete roof- tile
JP2006114587A (en) * 2004-10-13 2006-04-27 Tohoku Ricoh Co Ltd Printed circuit board

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