JPH0416944Y2 - - Google Patents

Description

[Detailed description of the invention] "Industrial application field" This invention rotates the directional direction of a directional antenna with a figure-8 directional pattern, and automatically determines the direction of minimum sensitivity of the directional pattern from the received output of the antenna. The present invention relates to a direction finder that detects the arrival direction of received radio waves and determines a sense of the arrival direction.

``Prior art'' In conventional direction finders of this type, in order to detect the minimum sensitivity point, the so-called silencing point, the received output of the figure-8 directional antenna is detected, and the polarity of the detected output is reversed, but if the detection output exceeds a predetermined level. The area was detected and its center was set as the point of minimum sensitivity. This is shown, for example, in Japanese Patent Publication No. 55-34910.
According to the conventional method of detecting the minimum sensitivity point, the minimum sensitivity point is originally the point where the reception level is almost zero, so it is often obscured by noise and is not clear, making it difficult to correctly detect the minimum sensitivity point. There were times when things became difficult. For this reason, there were cases in which the arrival direction of radio waves could not be detected correctly.

Furthermore, in the past, the sense of direction of arrival was determined as follows. That is, the sense antenna outputs are combined only around the maximum sensitivity difference of the directional antennas, the combined signal is sampled around the maximum sensitivity, and the sense is determined from the polarity of the sampled value. However, this sense decision cannot make a correct decision if the detection output level fluctuates.

Furthermore, various timings for finding the minimum sensitivity and determining the sense are set using frequency dividers, AND circuits, and OR circuits.
It is conceivable to make it using a circuit, a monostable multivibrator, etc., but the hardware for this would be relatively complicated, and adjustment would be troublesome, and changing the timing would also be difficult.

The purpose of this invention is to provide a direction finder that can accurately detect the minimum sensitivity point, the so-called silencing point, can also correctly determine the sense, and can easily generate various timings.

"Means for Solving the Problem" According to this invention, the directional direction of the figure-8 directional pattern antenna is rotated, the received output of the antenna is detected, and the phase difference is set to a constant value in synchronization with the rotation of the directional direction. First and second gate signals for the silencing point, which are shifted, are generated for each period of the envelope of the received detection output, and the received detection output is gated by these gate signals in the phase comparator circuit, and these gate outputs are integrated. It is differentially integrated in a circuit, and the integrated output is polarized and reset in synchronization with the gate signal. The control means simultaneously shifts the phases of the first and second gate signals for the silencing point in accordance with the determined polarity so that the integral output becomes zero, and the first,
The center of the second gate signal is automatically made to coincide with the minimum.

The output of the sense antenna is combined with the received output of the directional antenna only near its maximum sensitivity point, and the detected output of the combined signal is detected by the sense determination means.
It is gated by first and second gate signals for sensing, and the outputs of these gates are integrated by an integrator with opposite polarities, and a sense decision is made based on the polarity of the integrated output.

The first and second gate signals for silencing point and the first and second gate signals for sensing are each generated by a time-series signal generator including a memory. The memory is read out every clock, and repeated approximately in synchronization with the rotation of the readout antenna pointing direction, and the first and second gate signals for the silencing point are created based on the readout output of the memory. In other words, the first and second gate signals for the silencing point are each one in one word of the memory.
If these two bit outputs assigned to bits and being read out are directly used as the first and second gate signals for the silencing point, or by using the 1-bit output read from the memory, the silencing point can be determined from this point. First and second gate signals are generated. The first and second gate signals for sensing are each assigned one bit in one word of the memory and stored in the memory, and each of the first and second gate signals consists of two signals, the first and second gate signals. The interval between the center of each signal ahead of the 2-gate signal and the center of the signal after each of the first and second gate signals is one-half of the total number of addresses read out at one time in the antenna orientation direction of the memory. It is said that The center of the signal after the first gate signal for sense and the center of the signal after the second gate signal for sense are each a quarter of the total address with respect to the center between the first and second gate signals for silencing point. It is shifted by an amount corresponding to 1 of .

``Example'' Hereinafter, an example of the direction finder according to this invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the entire direction finder according to this invention. The directional direction of the antenna 11 having a figure-8 directional characteristic is rotated. For this reason, in this embodiment, a clock pulse generator 12 is provided, whose output clock pulses are frequency-divided by a frequency divider 13, and a motor 15 is rotated by the frequency-divided output via a drive circuit 14. The goniometer 16 is rotated by the rotation of the motor 15, and the received output of the antenna 11 is supplied to the goniometer 16, so that a received output with a rotated figure-8 directivity pattern is obtained as shown in FIG. 2A. This minimum sensitivity point, the so-called silencing point, appears twice in one rotation of the directional characteristic, and the phase of the received output is inverted for each minimum sensitivity point. In FIG. 2A, one phase is indicated by "+" and the other phase is indicated by "-".

This rotational directivity reception output is combined with the output of the sense antenna circuit 18 in a combining circuit 17. This sense antenna circuit 18 is provided with a 90-degree phase circuit, and the sense antenna output is made to have the same phase as one of the received outputs of the directional antenna 11. For example, an output of a constant level as shown in FIG. 2B is generated. can get. Therefore, when the output of the goniometer 16 and the output of the sense antenna circuit 18 are combined,
As shown by the dotted line in FIG. 2C, the composite signals are added in the same phase portion and subtracted in the antiphase portion, so that one maximum sensitivity point and one minimum sensitivity point appear for each rotation in the antenna directivity direction.

In direction finding, first the minimum sensitivity point of the received output shown in FIG. 2A is detected without combining the outputs of the sense antenna. That is, the output of the combining circuit 17 is received and detected by the receiver 19, and the received and detected output has an output level that changes along the envelope of FIG. 2A, as shown in FIG. 2C. This detection output is supplied to the balanced modulator 21 through the bias addition circuit 114, and the detection output, sine signal, and cosine signal are each balanced-modulated. In this case, the polarity of the detected output is inverted and a signal as shown in FIG. 2D is used. In other words, balanced modulation is performed so that the amplitude of the balanced modulation output becomes maximum at the minimum sensitivity point. To achieve this equilibrium state, in this example, the output of the clock pulse generator 12 is counted by the address counter 22, and the memory of the waveform generator 23 is read out using the count value of the address counter 22 as an address. The waveform generator 23 stores waveforms in which sin and cos waveforms are intermittent at a constant period, and the readout output of the sin and cos waveforms from the waveform generator 23 is as follows.
It is converted into an analog signal in the DA converters 24 and 25, but at that time it is multiplied by the output of the receiver 19, and the received detection output is supplied as a reference voltage to the DA converters 24 and 25, for example, and as a result, sin and cos
An analog signal obtained by multiplying the intermittent signal by the reception detection output is output, and the analog outputs of these DA converters 24 and 25 are supplied to resonance circuits 26 and 27, respectively, to obtain a balanced modulation output, and the balanced modulation output is For example, it is applied to a vertical balance circuit and a horizontal balance circuit in the cathode ray tube display 28, respectively.

On the other hand, the reference direction pulse generator 2 is driven by the motor 15.
9 is rotationally driven so that the pointing direction of the directional antenna 11 coincides with a reference direction, for example, the bow direction of the ship on which the directional antenna 11 is mounted, a reference direction pulse is generated, and the address counter 22 is activated by the reference pulse. It will be reset. As a result,
A so-called propeller-shaped display is displayed on the display 28, and the longitudinal direction of the propeller display is directed toward the direction of minimum reception sensitivity.

In this device, the output of the receiver 19 is gated by two mutually out-of-phase gate signals for the silencing point that are synchronized with the rotation of the pointing direction of the directional antenna, and these gate outputs are differentially processed by an integrating circuit. It is integrated. That is, in this example, a time-series signal generator 31 is provided to obtain a gate signal. This time series signal generator 31 includes a memory, for example a so-called read-only memory, and the clock pulses from the clock pulse generator 12 are controlled by a leading/lag controller 32.
The signal is supplied to the address counter 33 for counting, and the memory in the time-series signal generator 31 is read out according to the count contents of the address counter 33.
As will be described later, the clock pulse is frequency-divided by half by the lead/lag controller 32 and supplied to the address counter 33.

The time series signal generator 31 is configured as shown in FIG. 3, for example. The memory (ROM) 121 is read using the count of the address counter 33 as an address. The address (address) of the memory 121 is the fourth
As shown in the figure, the addresses range from 0 to 1800, and each address is read out sequentially every time the antenna orientation direction rotates by 0.2 degrees. At each address, a high level of the signal is stored as "1" and a low level is stored as "0". Memory 121 has 8 bits per word.
B ₀ to B ₇ , and the bit B ₀ has the address 0,
225, 450, 675, 900, 1125, 1350, 1575, 1800,
In other words, if it is 0 degrees from address 0, 0 degrees, 45 degrees, 90 degrees
Pulses are stored at addresses corresponding to degrees, 135 degrees, 180 degrees, 225 degrees, 270 degrees, 315 degrees, and 360 degrees.

This bit output _B0 is supplied to a decode counter 122 and counted as shown in FIG. The decode counter 122 sequentially outputs one pulse to eight output terminals _Q0 to _Q7 , as shown in FIG. 5, each time the bit output _B0 is input. its output
Q ₀ and Q ₄ are supplied to the OR circuit 123, and the first _gate signal for the silencing _point shown in FIG. Then, the second gate signal for the silencing point shown in FIG. 5F is obtained. Output Q ₂ and Q ₆ are OR circuit 125
, the outputs Q ₃ and Q ₇ are respectively supplied to the OR circuit 126 . A reset pulse shown in FIG. 5L is output from the OR circuit 126 to the terminal 52.

Therefore, when the antenna pointing direction is the reference direction (bow direction, 0 degrees), address 0 is read out.
The first gate signal E is generated from the terminal 34 when the antenna orientation direction is between 0° and 45° and between 180° and 225°, and between 45° and 90° and between 225° and 270°. A second gate signal F is generated from the terminal 35. In this way, the first gate signal E and the second gate signal F are out of phase with each other, and their pulse width is 1/4 of the rotation period of the antenna directivity direction (1/2 or less of the minimum output sensitivity period of the receiver 19). ), the pulse width is shorter than 90° in terms of the pointing direction rotation angle, and in this example, the pulse width is 45°. Although the trailing edge of the first gate signal E and the leading edge of the second gate F coincide with each other, they may be spaced apart from each other or may overlap with each other. Such first and second gate signals E and F are obtained at terminals 34 and 35 of the time-series signal generator 31, respectively. These first and second gate signals for the silencing point are supplied as control signals to a first gate circuit 37 and a second gate circuit 38 in the phase comparator circuit 36, respectively, as shown in FIG.

On the other hand, the output of the receiver 19 is supplied to the first gate circuit 37 and the second
As shown in FIG. D, the polarity is inverted and the signal is supplied to the second gate circuit 38. These first gate circuits 3
7. The second gate circuit 38 outputs each received output only during the period of the gate signal. These two outputs are combined to form a signal as shown in FIG. 2G, and the combined signal is integrated by an integrating circuit 41.
The integrated output has a waveform as shown in FIG. 2H. In other words, in this example, when the input is positive, the output of the integrating circuit increases linearly, and when the input becomes negative, the integral output decreases linearly from that value, and the increase or decrease is the absolute value of the integral input. The larger the value, the faster the process will be performed.

The integrated output of the integrating circuit 41 is output to the variable gain amplifier 42.
The signal is amplified and supplied to the sample and hold circuit 43 as a signal shown in FIG. 2I. The output of the integrating circuit 41 is sampled and held in a sample hold circuit 43 using a sampling pulse shown in FIG. 2J. This sampling pulse is obtained from the terminal 44 by matching the output of the OR circuit 125 with the bit output _B0 and the AND circuit 131 in FIG. 3, and this sampling pulse is generated immediately after the second gate signal F. . As shown in FIG. 2K, the output of the sample and hold circuit 43 takes a positive or negative value or zero depending on the relative phase between the gate signals E and F and the minimum sensitivity point of the received detection output.

In the left half of FIG. 2, the gate signals E and F are delayed with respect to the minimum sensitivity point of the received detection output, and the output of the sample and hold circuit 43 generates a negative output according to the delay state. The larger the delay, the larger the negative value output. Conversely, gate signal E,
If F is leading with respect to the minimum sensitivity point of the output of the receiver 19, a positive output is produced from the sample and hold circuit 43 as shown in the right half of FIG.

The output of the sample and hold circuit 43 is input to a determination circuit 45, and the generation phases of the gate signals E and F are controlled according to the determined result so that the output of the sample and hold circuit 43 approaches zero. For example, for a delayed phase, the judgment circuit 45
A positive output is generated at the output terminal 46 of the determination circuit 45, and a positive output is generated at the output terminal 47 of the determination circuit 45 for the leading phase. The discrimination outputs of these output terminals 46 and 47 are supplied to gates 48 and 49, respectively. The gates 48 and 49 are controlled by the output of the signal presence detection circuit 51, and the gates 48 and 49 are controlled by the output of the signal presence/absence detection circuit 51.
However, if no signal reception is detected, gates 48 and 49 are closed.

The signal presence/absence detection circuit 51 is supplied with the output of the receiver 19, for example, and if there is a portion of the received detected waveform exceeding a predetermined value, it determines that there is a signal and outputs the gates 48, 49.
Outputs high level “1” to Gates 48, 49
The output of is supplied to a lead/lag controller 32. Second
As shown on the left side of the figure, when the gate signals E and F are behind the minimum sensitivity point of the received detection output, the gate signals E and F are advanced. For this purpose, the lead/lag controller 32 adds a pulse to the clock pulse from the clock pulse generator 12 and supplies it to the address counter 33. Conversely, if the gate signals E and F are ahead of the minimum sensitivity point, the clock pulses supplied to the address counter 33 are thinned out. The insertion of these pulses and the thinning out of clock pulses are performed more frequently as the absolute value of the output of the sample and hold circuit 43 becomes larger.

After sampling and holding in the sample and hold circuit 43, a reset pulse shown in FIG. In the case where the clock pulses from the clock pulse generator 12 are as shown in FIG. 2M, if the gate signals E and F are delayed from the minimum sensitivity point, the clock pulses as shown in the left part of FIG. A pulse is inserted to control the gate signals E and F to advance in phase, and therefore the output of the sample and hold circuit 43 approaches zero. On the other hand, when the gate signals E and F are ahead of the minimum sensitivity point, the clock pulse M is thinned out and supplied to the address counter 33 as shown in the right part of FIG. The generated phase becomes delayed, and the positive value of the output of the sample and hold circuit 43 also becomes smaller and approaches zero.

Gate signals E and F are approximately equal to the minimum sensitivity point.
When the point shifts by 90° and coincides with the maximum sensitivity point, the areas of the received detection output gated by gate signal E and the received detection output gated by gate signal F become equal, and the integrated output of the integrating circuit 41 (at the time of sampling pulse L) becomes equal. ) becomes zero, and the gate signal E,
F ends up in a state where the phase coincides with the maximum sensitivity point of the received output. From this point, the gate signal E,
If F is near the maximum sensitivity point of the detection output, the first
In the figure, the gain of the variable gain amplifier 42 is increased to increase the pull-in speed, and the gate signal E,
F is synchronized to the point of minimum sensitivity.

For this purpose, for example, a retraction control circuit 54 is provided. In the pull-in control circuit 54, the output of the receiver 19 and the output of the polarity inversion circuit 39 are gated in gate circuits 55 and 56, respectively, and the gate outputs are added together and supplied to an integration circuit 57. Gate signals for gate circuits 55 and 56 are obtained from time-series signal generator 31. That is, in FIG. 3, the outputs of the OR circuits 123 and 124 are branched and supplied to the OR circuit 127, and from the output terminal 58, as shown in FIG. A signal is generated which is at a high level during the gate signal E and the second gate signal F (90° period) and is at a low level during the next 90° period, which causes the gate circuit 5
5 as a gate signal P. A part of the gate signal P at the terminal 58 is inverted by the inverter 59 and supplied to the gate circuit 56 as a signal as shown in FIG. 6Q.

The combined value of the outputs of the gate circuits 55 and 56 becomes a signal as shown in FIG.
The integrated output is in the state shown in FIG. 6S. The output of the integrating circuit 57 is smoothed by a smoothing circuit 61, and the output is as shown in FIG. 6T. As shown in the figure, when the phase difference between the gate signals E and F and the minimum sensitivity point is large, the output of the integrating circuit 57 becomes positive, and therefore the output of the smoothing circuit 61 also becomes positive, and this voltage is transferred to the variable gain amplifier 42. is supplied as a gain control signal to The larger the positive value of this gain control signal, the larger the gain of the amplifier 42 is. Therefore, the output of the integrating circuit 41 is greatly amplified, and if the phase difference between the minimum sensitivity point and the gate signals E and F for the silencing point is large, the output is greatly amplified by the amplifier 42 and the level sampled by the sample hold circuit 43 is also large. Therefore, the gate signals E and F follow the minimum sensitivity point at a faster speed.

The variable gain amplifier 42, the determination circuit 45, and the lead/lag controller 32 are configured as shown in FIG. 7, for example. That is, the variable gain amplifier 42 is configured using an operational amplifier 62, whose input side and output side are connected by a feedback resistor 63, and whose inverting input side is connected by a feedback resistor 63.
The output of the smoothing circuit 61 is supplied to the gate of the FET 64 which is grounded through the FET 64 . FET64
A positive voltage is applied to the gate of the FET 64, and the larger the positive voltage, the smaller the conduction resistance of the FET 64 and the larger the gain of the variable gain amplifier 42.

The clock pulse M from the clock pulse generator 12 is supplied to the frequency divider 70a in the lead/lag controller 32, and its 1/2 frequency divided output (FIG. 8A) is differentiated by the differentiator 70b, and its falling differential is The output (FIG. 8B) is supplied to the address counter 33 through an OR gate 70c and an AND gate 70d and counted. The 1/4 frequency divided output (FIG. 8C) of the frequency divider 70a is supplied to gates 69a and 69b. The determination outputs of gates 48 and 49 are supplied to the other inputs of gates 69a and 69b. When the gate signals E and F match the phase of the minimum sensitivity point, the outputs of the gates 48 and 49 are both at a low level, and the output of the gate 69a is also at a low level, and this low level is the output of the inverter 71a.
The signal is set at a high level and is supplied to the AND gate 70d.

The error voltage K from the sample-and-hold circuit 43 is integrated by an integrating circuit 65 within the determination circuit 45. The integrated output is compared with a negative reference voltage and a positive reference voltage by comparators 66 and 67, respectively. If the error voltage is positive, that is, if the gate signals E and F are too far ahead of the minimum sensitivity point, the output of the comparator 66 will be at a high level when the output of the integrating circuit 65 becomes larger in the negative direction than the negative reference voltage. Then,
This passes through terminal 46 and gate 48 to gate 69.
supplied to a. Therefore, the gate 69a is connected to the frequency divider 7.
The 1/4 frequency divided output of 0a (FIG. 8C) passes through and is applied to an AND gate 70d via an inverter 71a. As can be understood from FIG. 8, every other clock pulse (FIG. 8(b)) supplied to the address counter 33 is cut off by the 1/4 frequency division output (FIG. 8(c)). As a result, the generation phases of gate signals E and F are delayed.

On the other hand, when the gate signals E and F lag behind the minimum sensitivity point and the output K of the sample and hold circuit 43 is negative, the output of the integrating circuit 65 rises on the positive side, and when the integrated output exceeds the positive reference voltage, the comparator The output of 67 becomes high level, and this high level is supplied to gate 69b through terminal 47 and gate 49. Therefore, the 1/4 frequency divided output (FIG. 8 C) passes through the gate 69b, is differentiated by the differentiating circuit 71b, and its falling differential output (FIG. 8 D) is supplied to the address counter 33 through the OR gate 70c. It is counted.
Therefore, the number of clock pulses from the clock pulse generator 12 increases, and the phases of the gate signals E and F are advanced. gate 69
The outputs of a and 69b are supplied to an integrating circuit 65 through an OR gate 72, and the integrating circuit 65 is reset.

In this way, when the gate signals E and F for the silencing point follow and synchronize with the minimum sensitivity point, the output of the sense antenna circuit 18 is supplied to the synthesis circuit 17 for a short period near the maximum sensitivity in the reception output, and the sense signal is sensed at this point. Make a judgment.

In FIG. 1, the output of the smoothing circuit 61 is supplied to a voltage comparator 74, where it is compared with a constant level. 74
A high level is output from. That is, when the gate signals E and F for the silencing point almost match the minimum sensitivity point, the output of the smoothing circuit 61, that is, the output of the integrating circuit 57 becomes negative, and when this negative value becomes more negative than a certain value, this becomes a voltage. It is detected by the comparator 74. The output of this voltage comparator 74 is supplied to the gate 75, and the bit output _B4 of the memory 121 in the time-series signal generator 31 is supplied from the output terminal 76 to the sixth
It is supplied as a signal as shown in Figure Y. The center of this signal should originally be delayed by 90 degrees with respect to the centers of gate signals E and F, but the storage position of the memory 121 is shifted to provide a delay corresponding to the delay of the receiver 19, etc. There is. This bit output
The signal that passes through the gate 75 in B ₄ (Y in Figure 6) is converted into a sinusoidal signal by a low-pass wave generator 78, and its output is converted into a rounded waveform near the peak by a slice circuit 79. , this conversion output is sent to the sense antenna circuit 18 as a switching control signal b.
Supplied as. This switching control signal b
The sense antenna output is supplied to the combining circuit 17 only during the period . When listening to the received detection output,
If the switching control for synthesizing the sense antenna output is performed using a square wave, the switching control will produce a loud sound, but by using a waveform like a part of the sine wave, the sound can be significantly reduced. can. The slice circuit 79 passes only the input waveform having a set level V1 _or higher.

A first gate for sense that alternately generates a gate signal that coincides with the section (sense gate section) in which the sense antenna outputs are combined and a gate signal that approaches the sense gate section and deviates from it to one side, every minimum sensitivity period. A second gate signal d for sensing is generated which alternately generates a gate signal that coincides with the sense gate section and a gate signal that approaches the sense gate section and deviates from it to the other at every minimum sensitivity period. make. When the first gate signal for sensing c matches the sense period, the second gate signal for sense d does not match the sense period. For example, Figure 9c
As shown in , the first gate signal c for sensing is different from the gate signal that first coincides with the sense gate section where the sense is mixed with the same polarity as the directional antenna output, and then with the sense gate section where the sense is mixed with the opposite polarity, and and adjacent gate signals on the leading side are generated alternately. On the other hand, the second gate signal d for sensing alternately generates a gate signal adjacent to the same polarity mixed sense gate section on the leading side and a gate signal coincident with the opposite polarity mixed sense gate section, as shown in FIG. 9d. . These are stored in the memory 12 in the time series signal generator 31 in FIG. 1, as shown in FIGS. 3 and 4c and d.
1 bit outputs B ₂ and B ₃ are output terminals 81 and 82.
are generated as gate signals c and d, respectively. In other words, the first gate signal c for sensing is memory 1
21 bit B ₂ before address 675, and
The second gate signal d for sensing is stored in two locations near address 1575 and the second gate signal d in memory 121.
In B ₃ , the address interval between the two gate signals stored near address 675 and in front of address 1575, and the first gate signal for sensing c is stored, is the second gate signal for sensing d.
is larger than the address interval between the two stored gate signals, and for the address of the gate signal that is read out first in the first gate signal c for sensing, the address that is earlier in the second gate signal d for sensing is The address of the gate signal to be read out is a large value that is close to the address of the gate signal to be read out after the first gate signal for sensing c, and the address of the gate signal to be read out later in the second gate signal for sensing d. The addresses of the gate signals are small values that are close to each other, and the center of the address of both gate signals read before each of the first and second gate signals for sense, and the center of the address of both gate signals read after each. The interval is set to be half of the total number of addresses in the memory 121. Also, as is clear from FIG. 5, the first gate signal E for the silencing point is generated at 0° to 45° and 180° to 225°, and the second gate signal F for the silencing point is generated at 45° to 90° and 225°. °
270°, the address center 1575 (315°) of the gate signal to be read later in the first sense gate signal and the second sense gate signal
Each interval between the center 675 (135°) of the address of the gate signal that is read out first and the center 1125 (225°) between the first and second gate signals for the silencing point is the total number of addresses. It is one quarter of that, or 450.

These first and second sense gate signals c and d are input to gates 84 and 85 in the sense determination circuit 83, respectively, and these gate signals c and d control the output of the receiver 19 and the output of the polarity conversion circuit 39, respectively. Gate output. These gate outputs are combined with each other to form a signal as shown in FIG. 9e, and are supplied to the integrating circuit 86. The integrated output of the integrating circuit 86 is as shown in FIG. 9f, and in this example, the integrated output increases to the positive side for each of the first and second sensing gate signals c and d. That is, in the example of FIG. 9, the area of the positive output of gate c that matches the positive mixed sense gate (FIG. 6b) is larger than that of the negative output of gate d that does not match the sense gate immediately before it. It's getting bigger,
Also, the gate d matched with the reverse polarity mixed sense gate
The area of the negative output of gate c is smaller than that of the positive output of gate c that does not match the sense gate immediately before it. Therefore, the output of the integrating circuit 86 becomes positive, and each time the gate output is inputted thereto, the output of the integrating circuit 86 is sequentially added to the positive side. The output of the integrating circuit 86 is compared with a positive reference voltage and a negative reference voltage in voltage comparators 91 and 92, respectively. In the example of FIG. 9, when the output of the integrating circuit 86 exceeds the positive reference voltage +V _R , the output of the comparator 91 becomes high level as shown in FIG. 9j. The respective outputs of comparators 91 and 92 are latched into latch circuits 93a and 93b at a suitable timing that does not coincide with gates c and d, for example at the leading edge of gate F.

The reference direction pulse generator 29 generates a reference direction pulse as shown in FIG. It is reset by the signal pulse (FIG. 9o). As shown in FIG. 3, this reset pulse 0 is obtained by differentiating the bit output _B1 in a differentiating circuit 128 as shown in FIG. 4 _B1 , and this falling differential pulse is output. In other words, a reset pulse is generated corresponding to address 1125 (225°) in FIG. 4, and this reset pulse coincides with the center of gate signals E and F. The output of flip-flop 94 is as shown in FIG. A clock from the clock pulse generator 12 is supplied to the gate 96, and a clock pulse is obtained from the gate 96 from the reference pulse to the reset pulse 0 as shown in FIG.
It is counted at The reference direction pulse of the reference direction pulse generator 29 is input to the counter control section 98,
The counter control section 98 resets the display counter 97 immediately before the reference direction pulse is obtained, and latches the count contents of the display counter 97 in the latch circuit 99 before resetting.

As shown in FIGS. 3 and 4, the terminal 101 of the time-series signal generator 31, that is, the bit of the memory 121,
As shown in FIG. 9n from _B0 , a signal is generated which is at a high level between 135° and 315° and is at a low level during the rest. This is supplied to the gate 103 of the brightness erasing circuit 102, and is also inverted and supplied to the gate 104. On the other hand, each output of the latch circuits 93a and 93b of the sense determining circuit 83 is connected to the gates 103 and 104.
are supplied respectively. The outputs of gates 103 and 104 are sent to balanced modulator 10 through OR gate 105.
6, and the clock pulses from the clock pulse generator 12 are input to the balanced modulator 106.
Balanced modulation is performed at the output of OR gate 105.
The balanced modulation output is provided as a brightness control signal to the cathode ray tube display 28 so that a display appears on the display 28 only during each positive half cycle.
The count value latched in the latch circuit 99 is transferred to the sense correction circuit 107 by the latch circuits 93a and 93b.
is corrected by the output of and digitally displayed on the display 108. This modification will be discussed later.

FIG. 9 shows an example of operation when the arrival direction of radio waves is, for example, 45 degrees. There are two minimum sensitivity points in one rotation of the antenna pointing direction, and it is not known to which of them the gate signals E and F are synchronized. In Figure 9, Figure 9c
The one that matches the sense gate section in the first sense gate signal is the sense gate signal (Figure 6b)
This is a case where the positive polarity addition section matches the positive polarity addition section. On the other hand, if synchronization is performed with a 180° deviation, the state will be as shown in Fig. 10, and the first sense gate signal c will become the sense gate signal (Fig. 6 b) as shown in Fig. 10 c. This corresponds to the reverse polarity adder. In this case, the input to the integrating circuit 86 becomes as shown in FIG. 10e, and the integration result always becomes a negative value as shown in FIG. 10f. Therefore, the level of this integrated output increases sequentially in the negative direction. When this negative voltage becomes larger in the negative direction than the negative reference voltage -V _R in the negative voltage comparator 92, the output of the negative voltage comparator 92 becomes high level as shown in FIG. Latched. In this case, the period during which the gate 96 is open is 180° longer than in the case of FIG. 9, as shown in FIG. 10l. Therefore, in the sense correction circuit 107, the latch circuit 9
Based on the fact that a low level is input from 3a and a high level is input from latch circuit 93b, in this example, the count value 225 of counter 97 is plus or minus 180 and displayed on display 108 as 45°.

As shown in Figure 11, the direction of arrival of the received radio waves is
In the case of 225°, when the first sense gate signal c matches the positive addition part of the sense gate signal (FIG. 6b), the waveforms of each part become as shown in FIG. The output takes a positive value, and the output gradually increases in the positive direction. When this exceeds the reference voltage V _R , the output of the positive voltage comparator 91 becomes high level, which is latched by the latch circuit 93a and is counted by the counter 97. The numerical value is detected as the correct receiving direction. On the other hand, as shown in FIG. 12, when the direction of arrival of the received radio wave is 225 degrees and the reverse polarity adder of the sense gate matches the gate signal c, the output of the integrating circuit 86 is as seen from the state shown in FIG. increases in the negative direction, and the latch circuit 9
The output of 3b becomes high level, which is input to the sense correction circuit 107, and the count value of the counter 97 is added or subtracted by 180 degrees from 45 degrees, and is displayed as 225 degrees.

In short, when the output of the latch circuit 93a is at a high level, the direction of the minimum sensitivity point where the gate signals E and F at that time are synchronized is determined as the correct reception direction, and when the output from the latch circuit 93b is at a high level, the direction of the gate signal E at that time is determined as the correct reception direction. , F are synchronized in the direction opposite to the direction of the minimum sensitivity point (direction 180 degrees different) to determine the correct reception direction and sense.

For example, when the direction of arrival of the received radio wave is 0°, the deflection signal p in the X direction by the resonant circuit 27 in FIG. The direction deflection signal q becomes a signal in a state as shown in FIG. 13 q. In FIG. 13, - indicates an opposite phase to +. On the other hand, the output of the OR circuit 105 becomes the signal shown in FIG. 13r. Therefore, the output of the balanced modulation circuit 106 is the 13th
As shown in Figure s, the phase between 90° and 270° and the other sections are opposite in polarity. Therefore 0°
The lower half of the display (180° direction) when receiving nearby direction.
is erased by the output of the balanced modulation circuit 106, and while the 180° direction is being received, the 180° direction of the display is erased,
As shown in FIG. 14, a display indicating the zero degree direction is obtained. In other words, the dotted line display 112 in FIG. 14 is erased.

On the other hand, when a radio wave arrives from a direction of 180°, the output r of the OR gate 105 becomes a high level at 90° to 270°, as shown in FIG. 15r, and the output of the balanced modulator 106 becomes as shown in FIG. 90° to
Positive phase at 270°. As a result, the display in the 0° direction is erased, and the display in the 180° direction is obtained as shown in FIG. In FIG. 3, in the time-series signal generator 31, the bit output _B7 of the memory 121 is obtained from the terminal 109 as a pulse at address 1800 as shown in FIG. Counter 122 is reset.

In the above description, the motor 15 that rotates the directional direction of the directional antenna is driven using the clock pulse of the clock pulse generator 12 as a reference, but it is also possible to rotate the so-called code plate in synchronization with the rotation of the directional direction of the antenna without using such a clock pulse. For example, the antenna direction from the code plate is
It may be configured to obtain one pulse every 0.1° rotation, and this pulse may be used as the clock pulse of the above embodiment. In addition to using a goniometer, the directional antenna may be rotated directly. The count contents of the address counter 33 are read out by the reference direction pulse from the reference direction pulse generator 29, and twice the value is inputted to the latch circuit 99 and displayed on the display 108, and the flip-flop 9
4. The gate 96 and display counter 97 can be omitted. By making the address counter 33 count 3,600 times in one rotation of the antenna pointing direction, it is possible to display the count value of the address counter 33 as a direction without doubling it. When the contents of the address counter 33 are used for display and an inexpensive asynchronous counter 33 is used, it is necessary to read the counter 33 when the operation within the counter 33 is not propagating. The display counter 97 has a maximum count value of 360, and even a synchronous type can be used at low cost. A digital display system using the display 108 or an analog display system using a cathode ray tube display may be omitted.

When the sense antenna outputs are combined, as shown in FIG. 14, in addition to the detection direction display, a small propeller display 113 shown by a dotted line in a direction 90 degrees from this appears. In order to erase this display 113, for example, a bias addition circuit 114 is inserted on the input side of the balanced modulator 21 in FIG.
(Fig. 3), the bit output B ₅ (Fig. 4 B ₅ ) is supplied from the terminal 129, and the received detection output (Fig. 6 C ₁ ) is supplied.
What is necessary is to make the level of the sense antenna superimposed portion sufficiently large so that this portion is cut off within the balanced modulator 21. The memory 121 may be added to the time-series signal generator 31 and the timing signals E, F, J, L, P, Q, etc. may also be read directly from the memory and generated.

``Effect of the invention'' As mentioned above, according to the direction finder of this invention, even if the minimum sensitivity point is buried in noise, the minimum sensitivity point can be determined by the average value of the amplitude values before and after the minimum sensitivity point. can be detected correctly. In addition, since the sense determination is made by comparing the area of the part taken out coincident with the sense gate section and the part taken out outside the sense gate section of the same width, the level of the detection output varies. However, the sense can be determined accurately without being influenced by this.

Moreover, for this purpose, first and second gate signals c and d for sensing are used, but in order to generate these gate signals c and d by a time series signal generator 31 using a memory 121, a frequency dividing circuit and a monostable multivibrator are used. It can be configured with a smaller circuit scale than when generating gate signals c and d using, for example, a circuit with good stability, and changes in the pulse width and phase can be made by rewriting or replacing the memory 121. It is relatively easy to perform, and it is possible to mass-produce products that work reliably. Furthermore, as shown earlier, when determining the sense, the sense gate signal b
When synthesizing the sense signal using a rounded waveform like a half-wave of a sine wave, receiver 1
When listening to the output of No. 9, the sense gate signal does not become loud, and there is no possibility that it will be difficult to listen to.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing an example of the direction finder according to this invention, Fig. 2 is a time chart for explaining how to automatically determine the minimum sensitivity point,
FIG. 3 is a block diagram showing a specific example of the time-series signal generator 31, FIG. 4 is a diagram showing an example of storage in the memory 121, and FIG. 5 is a time chart showing a part of the operation of FIG. Figure 6 shows the retraction speed control circuit 54.
7 is a diagram showing a specific example of the determination circuit 45, lead/lag controller 32, and variable gain amplifier 42. FIG. 8 is a time chart for explaining the operation. , No. 9
Figures 12 to 12 are time charts showing examples of various states of the sense determination operation, Figure 13 is a time chart for explaining the brightness modulation operation, and Figure 14 is 0°.
Figure 15 showing an example of display for arriving radio waves in direction.
The figure is a time chart for explaining the brightness modulation operation when a radio wave is received from the opposite direction to that in the case of FIG. 13, and FIG. 16 is a diagram showing an example of the display. 11...Directional antenna, 12...Clock pulse generator, 15...Motor, 16...Goniometer, 17...Synthesizer, 18...Sense antenna circuit, 21...Balanced modulator, 19...Receiver, 2
8... Cathode ray tube display, 36... Phase comparator, 3
1...Time series signal generator, 32...Lead/lag controller, 33...Address counter, 37, 38...
Gate circuit, 42... Variable gain amplifier, 43...
Sample hold circuit, 45... Judgment circuit, 54
... Retraction speed control circuit, 83 ... Sense determination circuit, 97 ... Display counter, 84, 85 ...
Gate, 86... Integrator, 87... Sampling addition circuit, 91... Positive voltage comparator, 92... Negative voltage comparator, 108... Display, 121... Memory.

Claims (1)

[Claims for Utility Model Registration] Rotating the directional direction of the figure-8 directional pattern antenna,
The reception output of the antenna is detected and the minimum sensitivity of the antenna directional characteristic is detected to detect the direction of arrival of the received radio wave, and the antenna reception signal is combined with the sense antenna reception signal near its maximum sensitivity, and the combined number is In a direction finder that determines the sense of the arrival direction of received radio waves from The output phase comparator circuit determines the polarity of the output of the phase comparator circuit in synchronization with the first and second gate signals for the silencing point, resets the phase comparator circuit, and performs the following according to the determination result. The first for the silencing point by shifting the readout phase of the memory with respect to the rotation in the pointing direction.
The phase of the second gate signal is shifted so that the output of the phase comparator circuit becomes small, and the first gate signal for the silencing point is
a control means for causing the second gate signal to follow the minimum sensitivity point of the antenna reception output; and a control means for extracting the detected output of the composite signal using the first and second gate signals for sensing, and converting the two extracted outputs to opposite polarities. a sense determining means which integrates with an integrator, inverts the polarity of the input to the integrator each time the minimum sensitivity point of the antenna directivity is received, and determines the sense based on the polarity of the integrated output; The memory is read out, and the readout is repeated almost in synchronization with the rotation of the pointing direction, and the silencing point memory has the same width and the phase is shifted by a certain value for each period of the envelope of the received output. 1. A second gate signal is generated, and two bits in each word of the memory are assigned to the first and second sense gate signals, and the two gate signals are separated in the address direction and stored. The interval between the addresses of the two gate signals of the first gate signal for sensing is equal to that of the second gate signal for sensing.
The address of the gate signal that is larger than the interval between the addresses of the two gate signals of the gate and which is read out first in the first gate signal for sensing, is read out first in the second gate signal for sensing. The address of the gate signal that is read later is a large value that is close to the address of the gate signal that is read later in the first gate signal for sense, and the address of the gate signal that is read later in the second gate signal for sense. The addresses of are small values that are close together,
The interval between the center of the address of both gate signals read first and the center of the address of both gate signals read later is half of the total number of addresses that are repeatedly read from the memory, and is read after the first gate signal for sensing. The intervals between the center of the address of the gate signal, the center of the address of the gate signal read out before the second gate signal for sensing, and the center between the first and second gate signals for the silencing point are each equal to the total number of addresses mentioned above. A direction finder characterized by comprising: a time-series signal generator corresponding to an interval of one-fourth of the above.