JPH0327075B2 - - Google Patents

Description

[Detailed Description of the Invention] "Industrial Application Field" This invention rotates the antenna directivity direction of a figure-8 directional antenna, and combines the antenna reception signal with the sense antenna reception signal only in the vicinity of its maximum sensitivity. The present invention relates to a direction finder that detects the arrival direction of received radio waves from the combined signal and determines a sense of the arrival direction.

``Prior art'' A conventional direction finder of this type is, for example, the
As shown in No. 34910 "Direction Finder", the combined part of the sense antenna reception signal in the detection output of the combined signal is sampled, and the sense is determined from the polarity. However, such a decision may not be able to make a correct decision if the detection output level fluctuates.

An object of the present invention is to provide a direction finder that can always sense a positive value even if the level of the received detection output fluctuates.

"Means for Solving the Problem" According to the present invention, from the detected output of the composite signal, a part in which the sense antenna reception signal is combined and a part in which the combination is not performed are extracted by a gate means, and the extracted two parts are extracted by a gate means. Integrate two outputs with opposite polarity using an integrator. The two outputs of the integrator are supplied with opposite polarities every envelope period of the detected output. A sense decision is made based on the polarity of the output of this integrator.

Embodiments Hereinafter, embodiments of the direction finder according to the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the entire direction finder according to the present invention. The directional direction of the antenna 11 having a figure-8 directional characteristic is rotated. For this reason, in this embodiment, a clock pulse generator 12 is provided, whose output clock pulses are frequency-divided by a frequency divider 13, and a motor 15 is rotated by the frequency-divided output via a drive circuit 14. The goniometer 16 is rotated by the rotation of the motor 15, the receiving output of the antenna 11 is supplied to the goniometer 16, and the receiving output obtained by rotating the figure-8 directivity pattern is obtained as the output of the goniometer 16 as shown in FIG. 2A. . This point of minimum sensitivity is 1 of the directional characteristic.
It appears twice in the rotation, and the phase of the received output is reversed for each point of minimum sensitivity. In FIG. 2A, one phase is indicated by "+" and the other phase is indicated by "-".

This rotational directivity reception output is combined with the output of the sense antenna circuit 18 in a combining circuit 17. This sense antenna circuit 18 is provided with a 90-degree phase circuit, and the sense antenna output is made to have the same phase as one of the reception outputs of the directional antenna 11, so that an output of a certain level as shown in FIG. 2B, for example, can be obtained. It will be done. Therefore, when the output of the goniometer 16 and the output of the sense antenna circuit 18 are combined,
The composite signals are added in the same phase and subtracted in the opposite phase, as shown by the dotted line in FIG.

In direction finding, first the minimum sensitivity point of the received output shown in FIG. 2A is detected without combining the outputs of the sense antenna. That is, the output of the combining circuit 17 is received and detected by the receiver 19, and the received and detected output has an output level that has changed along the envelope line of FIG. 2A, as shown in FIG. 2C. A sine signal and a cosine signal are balanced-modulated in a balanced modulator 21 using this detection output. In that case, the polarity of the detected output is inverted and a signal as shown in FIG. 2D is used. In other words, balanced modulation is performed so that the amplitude at the minimum sensitivity point becomes maximum. In order to perform this balanced modulation, in this example, the output of the clock pulse generator 12 is counted by the address counter 22, and the count value of the address counter 22 is used as an address to generate the waveform generator 2.
3 memory is read out. The waveform generator 23 stores waveforms in which sin and cos waveforms are intermittent at a constant period.
The readout output of the intermittent cos waveform is sent to the DA converter 24, 2.
5, it is converted into an analog signal, but at that time, it is multiplied by the output of the receiver 19, and the received detection output is supplied as a reference voltage to the DA converters 24 and 25, for example, and as a result, the intermittent sin and cos signals and the received An analog signal multiplied by the detection output is output, and the analog outputs of these DA converters 24 and 25 are supplied to resonance circuits 26 and 27, respectively, to obtain a balanced modulation output, and the balanced modulation output is used, for example, on a cathode ray tube display 28. are respectively applied to the vertical balance circuit and horizontal balance circuit at . On the other hand, the reference direction pulse generator 29 is rotationally driven by the motor 15, and a reference direction pulse is generated every time the directional direction of the directional antenna 11 coincides with the reference direction, for example, the bow direction of the hull on which the directional antenna 11 is mounted. , the address counter 22 is reset by the reference pulse. As a result, a so-called propeller-shaped display is performed on the display 28, with the diameter direction of the propeller display facing the minimum reception sensitivity direction.

First, the configuration and operation for automatically finding the minimum sensitivity point will be explained. Therefore, the output of the receiver 19 is gated by two out-of-phase gate signals that are synchronized with the rotation of the pointing direction of the directional antenna, and these gate outputs are differentially integrated by an integrating circuit. . That is, in this example, a time-series signal generator 31 is provided to obtain a gate signal. This time-series signal generator 31 is a so-called read-only memory, and clock pulses from the clock pulse generator 12 are supplied to an address counter 33 through a lead/lag controller 32 and counted. The sequence signal generator 31 is read out. As will be described later, the clock pulse is frequency-divided by half by the lead/lag controller 32 and supplied to the address counter 33.

As shown in FIG. 3, the addresses of the time-series signal generator 31 are set from 0 to 1800, and each address is sequentially read out every time the antenna directivity rotates by 0.2 degrees. At each address, a high level of the signal is stored as "1" and a low level is stored as "0". The first and second gate signals are shown in Fig. 3E,
It is stored as shown in F. The first gate signal E has a high level "1" stored between addresses 675 and 900 and between addresses 1575 and 1800, and the second gate signal F has a high level "1" stored between addresses 0 and 225 and between addresses 900 and 1125. A high level "1" is stored between the two. Therefore, when the antenna pointing direction is the reference direction (bow direction, 0 degrees), when address 0 is read, the second gate is located between the antenna pointing direction of 0° to 45° and 180° to 225°. Signal F is generated and the angle is from 135° to
The first gate signal E is generated between 180° and between 315° and 360°.

In this way, the first gate signal E and the second gate signal F are out of phase with each other, and their pulse width is 1/4 of the antenna pointing direction rotation period (1/2 or less of the output minimum sensitivity period of the receiver 19). , the pulse width is shorter than 90° in terms of the rotation angle of the pointing direction, and in this example, the pulse width is 45°. Although the trailing edge of the first gate signal E and the leading edge of the second gate F coincide with each other,
The intervals may be separated from each other or may overlap each other. Such first and second gate signals E, F
are obtained at terminals 34 and 35 of time-series signal generator 31, respectively. These first and second gate signals are supplied as control signals to a first gate circuit 37 and a second gate circuit 38 in the phase comparator 36, respectively.

On the other hand, the output of the receiver 19 is supplied to the first gate circuit 37 and the second
As shown in FIG. D, the polarity is inverted and the signal is supplied to the second gate circuit 38. These first gate circuits 3
7. The second gate circuit 38 outputs each received output only during the period of the gate signal. These two outputs are combined to form a signal as shown in FIG. 2G, and the combined signal is integrated by an integrating circuit 41.
The integrated output has a waveform as shown in FIG. 2H. In other words, in this example, when the input is positive, the output of the integrating circuit increases linearly, and when the input becomes negative, the integral output decreases linearly from that value, and the increase or decrease is the absolute value of the integral input. The larger is, the faster the process is performed.

The integrated output of the integrating circuit 41 is output to the variable gain amplifier 42.
The signal is amplified and supplied to the sample and hold circuit 43 as a signal shown in FIG. 2I. The output of the integrating circuit 41 is sampled and held in a sample hold circuit 43 using a sampling pulse shown in FIG. 2J. This sampling pulse is obtained from the terminal 44 of the time-series signal generator 31, as shown in FIG. 3J, and is generated immediately after the second gate signal F. As shown in FIG. 2K, the output of the sample and hold circuit 43 takes a positive or negative value or zero depending on the relative phase between the gate circuits E and F and the minimum sensitivity point of the received detection output.

In the left half of FIG. 2, the gate signals E and F are delayed with respect to the minimum sensitivity point of the received detection output, and the output of the sample and hold circuit 43 generates a negative output according to the delay state. The larger the delay, the larger the negative value output. Conversely, gate signal E,
If F is leading with respect to the minimum sensitivity point of the output of the receiver 19, a positive output is produced from the sample and hold circuit 43, as shown in the right half of FIG.

The output of the sample and hold circuit 43 is input to a determination circuit 45, and the generation phases of the gate signals E and F are controlled according to the determined result so that the output of the sample and hold circuit 43 approaches zero. For example, a positive output is generated at the output terminal 46 of the determination circuit 45 for a delayed phase, and a positive output is generated at the output terminal 47 of the determination circuit 45 for an advanced phase. The discrimination outputs of these output terminals 46 and 47 are supplied to gates 48 and 49, respectively. The gates 48 and 49 are controlled by the output of the signal presence/absence detection circuit 51, and the gates 48 and 49 are opened when a signal is being received, but when no signal reception is detected, the gates 48 and 49 are opened.
Close 49.

The signal presence/absence detection circuit 51 is supplied with the output of the receiver 19, and when the reception level is above a predetermined value, the gate 48,
A high level "1" is output to 49. gate 48,
The output of 49 is supplied to lead/lag controller 32.
As shown on the left side of FIG. 2, when the gate signals E and F are behind the minimum sensitivity point of the received detection output, the gate signals E and F are advanced. Therefore, in the lead/lag controller 32, the clock pulse generator 12
The address counter 33 is supplied with a pulse in addition to the clock pulse. Conversely, gate signals E, F
is ahead of the minimum sensitivity point, the clock pulses supplied to the address counter 33 are thinned out.

The insertion of these pulses and the thinning out of clock pulses are performed more frequently as the absolute value of the output of the sample and hold circuit 43 becomes larger.

After sampling and holding in the sample and hold circuit 43, a reset pulse shown in FIG. In the case where the clock pulses from the clock pulse generator 12 are as shown in FIG. 2M, if the gate signals E and F are delayed from the minimum sensitivity point, the clock pulses as shown in the left part of FIG. A pulse is inserted to control the gate signals E and F to advance in phase, and therefore the output of the sample and hold circuit 43 approaches zero. On the other hand, when the gate signals E and F are ahead of the minimum sensitivity point, the clock pulse M is thinned out and supplied to the address counter 33 as shown in the right part of FIG. The generated phase becomes delayed, and the positive value of the output of the sample and hold circuit 43 also becomes smaller and approaches zero.

Gate signals E and F are approximately equal to the minimum sensitivity point.
When they coincide with the maximum sensitivity point, the areas of the reception detection output gated by gate signal E and the reception detection output gated by gate signal F become equal, and the integral output of the integration circuit 41 (sampling pulse L ) becomes zero, and the gate signals E and F are brought into a state where the phases match the maximum sensitivity point of the received output. From this point of view, when the gate signals E and F are near the maximum sensitivity point of the detection output, the gain of the variable gain amplifier 42 is increased to increase the pull-in speed as shown in FIG. 1, and the gate signals E and F are at the minimum sensitivity point. synchronize to the point.

For this purpose, for example, a pull-in control circuit 54 is provided. In the pull-in control circuit 54, the output of the receiver 19 and the output of the polarity inversion circuit 39 are gated in gate circuits 55 and 56, respectively, and the gate outputs are added together and supplied to an integration circuit 57. Gate signals for gate circuits 55 and 56 are obtained from time-series signal generator 31. That is, as shown in FIG. 3P, from the output terminal 58, in this example, a signal is generated which is at a high level during the first gate signal E and the second gate signal F (90° period) and is at a low level during the next 90° period. is generated and supplied to the gate circuit 55 as a gate signal P. The gate signal P at the terminal 58 is inverted by the inverter 59 and becomes the signal Q in FIG.
The signal is supplied to the gate circuit 56 as a signal as shown in FIG.

The combined value of the outputs of the gate circuits 55 and 56 becomes a signal as shown in FIG.
The integrated output is in the state shown in FIG. 4S. The output of the integrating circuit 57 is smoothed by a smoothing circuit 61, and the output is as shown in FIG. 4T. As shown in the figure, when the phase difference between the gate signals E and F and the minimum sensitivity point is large, the output of the integrating circuit 57 becomes positive, and therefore the output of the smoothing circuit 61 also becomes positive, and this voltage is transferred to the variable gain amplifier 42. is supplied as a gain control signal to The larger the positive value of this gain control signal, the larger the gain of the amplifier 42 is. Therefore, the output of the integrating circuit 41 is greatly amplified, and if the phase difference between the minimum sensitivity point and the gate signals E and F is large, the output is greatly amplified by the amplifier 42 and the level sampled by the sample and hold circuit 43 becomes large. Therefore, the gate signals E and F follow the minimum sensitivity point at a faster speed.

The variable gain amplifier 42, the determination circuit 45, and the lead/lag controller 32 are configured as shown in FIG. 5, for example. That is, the variable gain amplifier 42 is configured using an operational amplifier 62, whose input side and output side are connected by a feedback resistor 63, and whose inverting input side is connected by a feedback resistor 63.
Grounded through FET64. The output of the smoothing circuit 61 is supplied to the gate of the FET 64. FET6
A positive voltage is applied to the gate of FET 4, and the larger the positive voltage, the smaller the conduction resistance of FET 64 and the larger the gain of variable gain amplifier 42.

The clock pulse M from the clock pulse generator 12 is supplied to the frequency divider 70a in the lead/lag controller 32, and its 1/2 frequency divided output (FIG. 6A) is differentiated by the differentiating circuit 70b. The output (FIG. 6b) is supplied to the address counter 33 through an OR gate 70c and an AND gate 70d and counted. The 1/4 frequency divided output (FIG. 6C) of the frequency divider 70a is supplied to gates 69a and 69b. The determination outputs of gates 48 and 49 are supplied to the other inputs of gates 69a and 69b. When the gate signals E and F match the phase of the minimum sensitivity point, the outputs of the gates 48 and 49 are both at a low level, and the output of the gate 69a is also at a low level, and this low level is the output of the inverter 71a.
The signal is set at a high level and is supplied to the AND gate 70d.

The error voltage K from the sample-and-hold circuit 43 is integrated by an integrating circuit 65 within the determination circuit 45. The integrated output is compared with a positive reference voltage and a negative reference voltage by comparators 66 and 67, respectively. If the error voltage is positive, that is, if the gate signals E and F are too far ahead of the minimum sensitivity point, the output of the comparator 66 will be at a high level when the output of the integrating circuit 65 becomes larger in the positive direction than the positive reference voltage. Then,
This passes through terminal 46 and gate 48 to gate 69.
supplied to a. Therefore, the gate 69a is connected to the frequency divider 7.
The 1/4 frequency divided output of 0a (FIG. 6C) passes through and is applied to an AND gate 70d via an inverter 71a. Therefore, as understood from FIG. 6, the clock pulse supplied to the address counter 33 (FIG. 6b) is divided into 1/4 by the 1/4 frequency division output (FIG. 6c).
It gets cut off every now and then. As a result, gate signals E, F
The generation phase of is delayed.

On the other hand, when the gate signals E and F lag behind the minimum sensitivity point and the output K of the sample and hold circuit 43 is negative, the output of the integrating circuit 65 rises on the negative side, and when the integrated output exceeds the negative reference voltage, the comparator The output of 67 becomes high level, and this high level is supplied to gate 69b through terminal 47 and gate 49. Therefore, the 1/4 frequency divided output (FIG. 6 C) passes through the gate 69b, which is differentiated by the differentiating circuit 71b, and its falling differential output (FIG. 6 D) is supplied to the address counter 33 through the OR gate 70c. It is counted.
Therefore, the number of clock pulses from the clock pulse generator 12 increases, and the phases of the gate signals E and F are advanced. gate 69
The outputs of a and 69b are supplied to an integrating circuit 65 through an OR gate 72, and the integrating circuit 65 is reset.

In this way, the gate signals E and F are placed at the minimum sensitivity point.
When tracking synchronization is achieved, the output of the sense antenna circuit 18 is supplied to the synthesis circuit 17 for a short period near the maximum sensitivity in the received output, and the sense is determined at this portion.

In FIG. 1, the output of the smoothing circuit 61 is supplied to a voltage comparator 74, where it is compared with a constant level. 74
A high level is output from. That is, when the gate signals E and F almost match the minimum sensitivity point, the output of the smoothing circuit 61, that is, the output of the integrating circuit 57 becomes negative, and when this negative value becomes more negative than a certain value, this becomes the output of the voltage comparator 74. Detected in The output of this voltage comparator 74 is supplied to a gate 75.
A signal as shown in FIG. 4Y is supplied from the output terminal 76 of the time-series signal generator 31. As shown in FIG. 3Y, this signal has a pulse center delayed by 90 degrees with respect to the rise of the gate signal F. Therefore, when gate signals E and F coincide with the minimum sensitivity point, a gate pulse is outputted from gate 75 as shown in FIG. A delay is applied to obtain a delayed output as shown in FIG. 4a, which is converted by the waveform conversion circuit 79 into a rounded waveform like a half-wave of a sine wave as shown in FIG. 4b. This output is sent to the sense antenna circuit 18.
The sense antenna output is supplied to the combining circuit 17 only during this period. The waveform conversion circuit 79 is constituted by, for example, a waveform generator.

In the present invention, the sense determination circuit 83 extracts the part where the sense antenna reception signal is synthesized from the detection output of the receiver 19 and the part where the sense antenna reception signal is not synthesized, and the integrator 86 integrates the part with the opposite polarity. do. Furthermore, the supply to the integrator 86 is inverted at each point of minimum sensitivity. Therefore, in this example, the detection output of the receiver 19 and the polarity conversion circuit 3
9 are gated by gates 84 and 85, respectively, and these gate outputs are combined and supplied to an integrator 86. The following gate signals are used to control the gates 84 and 85.

In other words, the gate signal that coincides with the section (sense gate section) in which this sense antenna output is combined,
Create a gate signal c that alternately generates gate signals that are shifted to one side with respect to the gate signal and that do not match the sense gate section, and that do not coincide with the sense gate section, and similarly for each minimum sensitivity point period. , a gate signal that coincides with the sense gate section and a gate signal that has the same phase shift in the same direction as the above-mentioned direction are alternately generated, but the gate signal whose cycle that coincides with the sense gate section is different from that of gate signal c. A signal d is generated. For example, as shown in Fig. 7c, the first gate signal coincides with the sense gate section where the senses are mixed with the same polarity, and the next gate signal is separated from the sense gate section where the reverse polarity is mixed, and the same width is adjacent to this on the leading side. The gate signal is generated alternately. On the other hand, as shown in FIG. 7d, a gate signal that is adjacent to the same polarity mixed sense gate section on the leading side and has the same width as the gate signal c, and a gate signal that coincides with the opposite polarity mixed sense gate section and has the same width. occur alternately. These are connected to the output terminal 81 of the time series signal generator 31 in FIG. 1, as shown in FIGS. 3c and 3d.
and 82, respectively.

These gate signals c and d are sent to the sense judgment circuit 83.
These gate signals c and d gate the output of the receiver 19 and the output of the polarity conversion circuit 39, respectively. These gate outputs are combined with each other to form a signal as shown in FIG. 7e, and are supplied to the integrating circuit 86. The integral output of the integrating circuit 86 is as shown in FIG. 7(f), and the integral output is sampled by the sampling pulse shown in FIG. 7(g) in the sampling/adding circuit 87, and added to the previous sample value. Thereafter, the integrating circuit 36 is reset by the reset pulse shown in FIG. 7h. These sampling pulses g and reset pulses h are obtained from output terminals 88 and 89 of the time series signal generator 31 shown in FIG. In the time series signal generator 31, the third
As shown in FIGS. g and h, a sampling pulse and a subsequent reset pulse are generated immediately after the slower gate signal among the gate signals c and d at intervals of 180 degrees.

The output of the sampling addition circuit 87 becomes a signal as shown in FIG. That is, in the example of Fig. 7, Fig. 7e
The area of the positive gate output that matches the same polarity mixed sense gate is larger than the negative gate output that does not match the previous sense gate, and also matches the opposite polarity mixed sense gate. The area of the negative gate output is smaller than that of the positive gate output that does not match the previous sense gate. Therefore, the output of the integrating circuit 86 becomes positive,
The output of the sampling addition circuit 87 is sequentially added to the positive side. The output of the sampling addition circuit 87 is sent to the voltage comparator 9.
1 and 92 with a positive reference voltage and a negative reference voltage, respectively. In the example of FIG. 7, when the output of the sampling addition circuit 87 exceeds the positive reference voltage +V _R , the output of the comparator 91 becomes high level as shown in FIG. 7j.

The reference direction pulse generator 29 generates a reference direction pulse as shown in FIG. It is reset by the signal pulse (o in Figure 7), that is, it is reset by the pulse that coincides with the center of the gate signals E and F at one of the followed minimum sensitivity points, the 0 side in Figure 3. . The output of flip-flop 94 is the seventh
This output is provided to gate 96, as shown in FIG. A clock from the clock pulse generator 12 is supplied to the gate 96, and as shown in FIG.
Clock pulses are obtained until the address pulse, and are counted by a display counter 97. The reference direction pulse of the reference direction pulse generator 29 is input to the counter control section 98, and the counter control section 98 outputs the display counter 9 immediately before the reference direction pulse is obtained.
7, and before resetting, the count contents of the display counter 97 are latched in the latch circuit 99.

A signal is generated from the terminal 101 of the time-series signal generator 31, as shown in FIG. This signal is obtained from a storage signal as shown in FIG. 3n.
This is supplied to the gate 103 of the brightness erasing circuit 102, and is also inverted and supplied to the gate 104. On the other hand, each output of the positive voltage comparator 91 and the negative voltage comparator 92 of the sense determining circuit 83 is connected to the gate 10.
3 and 104, respectively. gate 10
The output of 3,104 is supplied to a balanced modulator 106 through an OR gate 105, the clock pulse of the clock pulse generator 12 is input to the balanced modulator 106, and the output of the OR gate 105 performs balanced modulation. Its balanced modulation output is the cathode ray tube display 2.
8 as a volatility control signal so that an indication appears on the display 28 only in each positive half cycle thereof. The count value latched in the latch circuit 99 is sent to the comparators 91 and 9 in the sense correction circuit 107.
2 is corrected and digitally displayed on the display 108. This modification will be discussed later.

FIG. 7 shows an example of operation when the arrival direction of radio waves is, for example, 45 degrees. There are two minimum sensitivity points in one rotation of the antenna directivity direction, and it is not known to which of them the gate signals E and F are synchronized. In Figure 7, Figure 7c
This is a case where the sense gate section in the gate signal coincides with the positive addition section of the sense gate signal. On the other hand, if synchronization is achieved with a 180° deviation, the state will be as shown in FIG. 8, and the gate signal c will match the opposite polarity adder of the sense gate, as shown in FIG. 8c. In this case, the input to the integrating circuit 86 becomes as shown in FIG. 8e, and the integration result always becomes a negative value as shown in FIG. 8f. Therefore, the output of the sampling addition circuit 87 is as shown in FIG.
As shown in , the level gradually increases in the negative direction. When this negative voltage becomes larger in the negative direction than the negative reference voltage -V _R in the negative voltage comparator 92, the output of the negative voltage comparator 92 becomes high level as shown in FIG. 8o. In this case, the period during which the gate 96 is open is 180° longer than in the case of FIG. 7, as shown in FIG. 8l. Therefore, in the sense correction circuit 107, the comparator 91 to the low level comparator 9
Based on the input of the high level from 2, in this example, the count value 225 of the counter 97 is plus or minus 180 and displayed on the display 108 as 45 degrees.

As shown in Fig. 9, when the direction of arrival of the received radio wave is 225 degrees, if the gate signal c matches the positive addition part of the sense gate, the waveform of each part will be the 9th.
The state shown in the figure is reached, and the output of the integrating circuit 86 takes a positive value, so the output of the sampling and adding circuit 87 gradually increases in the positive direction, and this becomes the reference voltage.
When V _R is exceeded, the output of the positive voltage comparator 91 becomes high level, and the count value of the counter 97 is detected as the correct receiving direction. On the other hand, as shown in Fig. 10, when the direction of arrival of the received radio wave is 225 degrees and the reverse polarity adder of the sense gate matches the gate signal c,
As can be seen from the state shown in FIG. 10, the output of the sampling addition circuit 87 increases in the negative direction, and this is input to the sense correction circuit 107, and the count value of the counter 97 is added or subtracted by 180 degrees to 45. being done
Displayed as 225°.

In short, when the output of the positive voltage comparator 91 is at a high level, the direction of the minimum sensitivity point where the gate signals E and F are synchronized at that time is considered the correct reception direction, and when the output of the negative voltage comparator 92 is at a high level, the direction at that point is the minimum sensitivity point where the gate signals E and F are synchronized. The direction opposite (180 degrees different direction) from the direction of the minimum sensitivity point where the gate signals E and F are synchronized determines the correct reception direction and sense. Here, special care is taken to avoid malfunctions due to the cumulative addition in the sampling and addition circuit 87, but even if the output of the integrator 86 is directly compared with the voltage comparators 91 and 92 at the sampling timing of the cumulative addition. good. For example, when the direction of arrival of the received radio wave is 0°, the displayed image shows that the deflection signal p in the X direction by the resonant circuit 27 in FIG. 1 is a signal in the state shown in p in FIG. The vertical deflection signal q from 26 becomes a signal in a state as shown in FIG. 11q. In FIG. 11, - indicates an opposite phase to +. On the other hand, the output of the OR circuit 105 becomes the signal shown in FIG. 11r. Therefore, the balanced modulation circuit 10
The output of No. 6 is as shown in Fig. 11s, and the phase between 90° and 270° and the other sections are opposite in polarity. Therefore, while receiving near the 0° direction, the lower half of the display (180° direction) is erased by the output of the balanced modulation circuit 106, and while receiving the 180° direction, the 180° direction of the display is erased. As shown in FIG. 12, a display indicating the zero degree direction is obtained. In other words, the dotted line display 112 in FIG. 12 is erased.

On the other hand, when a radio wave arrives from a direction of 180 degrees, the output r of the OR gate 105 becomes a high level at an angle of 90 degrees to 270 degrees, as shown in FIG. From 90° as shown
Positive phase at 270°. As a result, the display in the 0° direction is erased, and the display in the 180° direction is obtained as shown in FIG. In the time-series signal generator 31, a pulse is obtained from the terminal 109 at address 1800 as shown in FIG. 3P, and the address counter 33 is reset by this.

In the above, various signals are sent to the time series signal generator 3.
1, but instead of using such a signal generation circuit, there is a counting circuit that counts clock pulses, various frequency-divided signals obtained during counting by the counting circuit, appropriate combinations of these frequency-divided signals, and their A monostable multivibrator driven by the output of can be used to produce signals of various phases and pulse widths corresponding to those shown in FIG. Furthermore, in the above description, the motor that rotates the directional direction of the directional antenna is driven using the clock pulse of the clock pulse generator 12 as a reference.
Without using such a clock pulse, a so-called code plate is rotated in synchronization with the rotation of the antenna pointing direction, and the antenna pointing direction is determined from the code plate.
It may be configured to obtain one pulse every 0.1° rotation, and this pulse may be used as the clock pulse of the above embodiment. In addition to using a goniometer, the directional antenna may be rotated directly.

In FIG. 1, the delay device 78 may be omitted, and the memory address of the sense gate signal Y of the time-series signal generator 31 may be shifted by a value corresponding to the delay. The gate signal X in the time series signal generator 31 is omitted,
Gate signal X is generated by the composite signal of gate signals E and F.
You can also make one. The count contents of the address counter 33 are read out by the reference direction pulse from the reference direction pulse generator 29, and the double value is inputted to the latch circuit 99 and displayed on the display 108. 9
7 can be omitted. In this case, the value obtained by subtracting that value from 360° will be displayed. The address counter 33 changes with one rotation of the antenna pointing direction.
By counting 3600, it is possible to display the count value of the address counter 33 as a direction without doubling it. When the contents of the address counter 33 are used for display and an inexpensive asynchronous counter 33 is used, it is necessary to read the counter 33 when the operation within the counter 33 is not propagating. The display counter 97 has a maximum count value of 360, and even a synchronous type can be used at low cost.
A digital display system using the display 108 or an analog display system using a cathode ray tube display may be omitted.

When the sense antenna outputs are combined, as shown in FIG. 12, in addition to the detection direction display, a small propeller display 113 shown by a dotted line in a direction 90 degrees from this appears. To erase this display 113, for example, a bias addition circuit 114 is installed on the input side of the balanced modulator 21.
is inserted, the output of the gate 75 (Z in FIG. 4) is supplied to the bias adder circuit 114, and the level of the sense antenna superimposed portion of the received detection output (C ₁ in FIG. 4) is made sufficiently large. is the balanced modulator 2
It is sufficient if it is cut off within 1.

In FIG. 1, the sampling and addition circuit 87 may be omitted and the output of the integrator 86 may be directly supplied to the positive voltage comparator 91 and the negative voltage comparator 92. In this case, for example, in FIG. 7, the input of the integrator 86 (FIG. 7 e) is zero, that is, the outputs of the positive voltage comparator 91 and the negative voltage comparator 92 are latched at appropriate timings other than the gate signals c and d. It is sufficient to latch it into the circuit and supply the latch output to the sense correction circuit 107 and the brightness cancellation circuit 102. The latch timing for this latch circuit is determined by the time series signal generator 31.
You can get it from

"Effects of the Invention" As described above, according to the present invention, the areas of the portion taken out coincident with the sense gate section and the portion taken out of the same width but outside the sense gate section are compared. Even if the detection output level of the receiver 19 fluctuates, sense determination can always be made accurately without being affected by this. Further, according to the present invention, sense can be determined for each minimum sensitivity point period based on the polarity of the output of the integrator ₈₆ .
Even when the reception level of received radio waves is large due to fading and fluctuates relatively quickly, sense determination can be performed correctly. Furthermore, as mentioned earlier, when generating various timing pulses using a read-only memory as the time-series signal generator 31, it is better to generate timing pulses using a frequency divider circuit and a monostable multivibrator. It has good stability, and it is relatively easy to change the pulse width or phase by rewriting or replacing the read-only memory, and it is possible to mass-produce devices that operate reliably. Furthermore, as shown earlier, when the waveform conversion circuit 79 uses a rounded waveform like a half-wave of a sine wave as the sense gate signal at the time of sense determination and synthesizes the sense signal, the receiver 19 Since the sense gate signal does not become loud when listening to the output of

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a direction finder according to the present invention, and FIG. 2 is a time chart for explaining automatically determining the minimum sensitivity point.
3 is a diagram showing a memory example of the time-series signal generator 31, FIG. 4 is a time chart for explaining the operation of the pull-in speed control circuit 54, and FIG. 5 is a diagram showing the determination circuit 45 and the lead/lag controller 32. , a diagram showing a specific example of the variable gain amplifier 42, FIG. 6 is a time chart for explaining its operation, FIGS. 7 to 10 are time charts showing examples of various states of sense determination operation, and FIG. The figure is a time chart for explaining the volatility modulation operation, Figure 12 is a diagram showing an example of display for incoming radio waves in the 0° direction, and Figure 13 is
FIG. 14 is a time chart for explaining the volatility modulation operation when radio waves are received from the direction opposite to that shown in FIG. 1, and FIG. 14 is a diagram showing an example of the display. 11: Directional antenna, 12: Clock pulse generator, 15: Motor, 16: Goniometer, 1
7: Synthesis circuit, 18: Sense antenna circuit, 2
1: Balanced modulator, 19: Receiver, 28: Cathode ray tube display, 36: Phase comparator, 31: Time series signal generator, 32: Lead/lag controller, 33: Address counter, 37, 38: Gate circuit , 42: Variable gain amplifier, 43: Sample and hold circuit, 45:
Judgment circuit, 54: Retraction speed control circuit, 83:
sense determination circuit, 97: display counter, 84,
85: Gate, 86: Integrator, 87: Sampling addition circuit, 91: Positive voltage comparator, 92: Negative voltage comparator, 108: Display.

Claims (1)

[Claims] 1. Rotating the antenna pointing direction of the figure-eight directional antenna, combining the antenna reception signal with a sense antenna reception signal near its maximum sensitivity, and detecting the arrival direction of the reception radio wave from the combined signal. In the direction finder, a gate means extracts from the detection output of the composite signal a portion in which the sense antenna signal is combined and a portion in which the sense antenna signal that approaches the same is not combined; and an integrator that receives the two outputs with opposite polarities, and inverts and integrates the input polarity each time the minimum sensing point of the antenna directivity is received, and when the output of the integrator has a predetermined polarity, A direction finder characterized in that the detected direction of arrival is displayed as it is, and when the output of the integrator has a polarity opposite to the predetermined polarity, the direction of arrival is set to a direction that is 180° different from the detected direction of arrival.