JPH04167536A - Formation method of opening part in metallic bump formation substance - Google Patents

Formation method of opening part in metallic bump formation substance

Info

Publication number
JPH04167536A
JPH04167536A JP2295772A JP29577290A JPH04167536A JP H04167536 A JPH04167536 A JP H04167536A JP 2295772 A JP2295772 A JP 2295772A JP 29577290 A JP29577290 A JP 29577290A JP H04167536 A JPH04167536 A JP H04167536A
Authority
JP
Japan
Prior art keywords
insulating film
etching
opening
photoresist
conductive film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2295772A
Other languages
Japanese (ja)
Other versions
JP2785474B2 (en
Inventor
Takayuki Yoshida
隆幸 吉田
Kenzo Hatada
畑田 賢造
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2295772A priority Critical patent/JP2785474B2/en
Publication of JPH04167536A publication Critical patent/JPH04167536A/en
Application granted granted Critical
Publication of JP2785474B2 publication Critical patent/JP2785474B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/50Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE:To enable an opening part having a smooth taper to be formed stably by a method wherein, after the formation of a vertical opening part on a part of insulating film using CF4 etching gas, the insulating film is further etched away while etching back the taper part of photoresist using CF4+O2 mixed gas. CONSTITUTION:An opening part 6 is vertically bonded by dry-etching process using CF4 etching gas as well as an individual insulating film 5 as a plating mask of a transfer bump formation substrate or using photoresist as an etching mask 9 on a part of the insulating film 5 and a conductive film 4. Next, a taper 10 is formed in the opening part 6 by dry-etching process using CF4+O2 mixed gas simultaneously etching away the etching mask 9 of photoresist and the insulating film 5 while etching back the opening part taper 8. Through these procedures, the opening part 6 having a smooth taper 10 can be formed stably.

Description

【発明の詳細な説明】 産業上の利用分野 本発明1よ 半導体の実装方式である転写バンブ方式に
用いるバンブを形成する金属突起形成基板の製造方法に
関するものであム 従来の技術 従来の金属突起形成基板の製造方法および転写バンブ実
装方法について、第3皿 第4図とともに説明すも ま
ず第3図において金属突起形成基板について説明すも 
絶縁基板31上に導電膜32を全面に形成すも 絶縁基
板31にはセラミツ久 ガラス等を用しく 導電832
には主にPt、ITOなどを用いも 次に この導電膜
32上にめっき用マスク33となる絶縁膜を全面に形成
し フォトレジストをエツチングマスクにして半導体素
子の電極に対応した位置にテーパーのついた開口部34
を形成すも このめっき用マスク33には一般にP−C
VD法等で形成された5ide、5isN4等の無機薄
膜を用し\ その膜厚は約500nmから11000n
程度としていも また 開口部の形成にはCF=、Oe
によるドライエツチング法が用いられも次L  めっき
用マスク33に形成した開口部34の導電膜32上番ミ
 導電膜32をめっき電極として電解めっき法により金
属突起(Au)35. 以後バンブと呼水 を形成すも 次に 第4図(a)に示すようにバンブ形成基板31上
に形成したバンブ35とフィルムキャリア41のインナ
ーリード42とを位置合わせし 第4図(b)に示すよ
うに加熱した加圧ツール43によって加圧することによ
ってバンブ35とインナーリード42とを接合すa そ
の抵 第4図(c)に示すように加圧ツール43を解除
しバンブ35をインナーリード42へ転写すa 次く 
第4図(d)に示すようにバンブ35つきインナーリー
ド42と半導体素子44のアルミ電極45とを位置合わ
せL/%  第4図(e)に示すように加圧ツール43
によって一括接合すムこの後第4図(f)に示すように
加圧を解除し半導体素子44の実装を完了すム な耘 第4図(C)において、バンブ35が転写された
基板31は再びバンブ形成のめつき基板として使用され
も 発明が解決しようとする課題 しかし 従来例においては以下のような問題点かあム 型形成されたバンブを転写するために(i、絶縁膜開口
部は滑らかなテーパーが形成されていることが必要であ
も しかし 従来絶縁膜が厚い場合または導電膜にTi
/Pt/Ti等3層膜を用いた場合、Tiをエツチング
しなければならないがTiはエツチングレートが遅いた
めフォトレジストのエツチングマスクが開口部の形成前
に無くなってしまうという問題があっ九 本発明(よ 金属突起形成基板の絶縁膜またはエッチレ
ートの遅い膜に安定してテーパーのついた開口部を形成
するための開口部形成方法を提供するものであも 課題を解決するための手段 上記の課題を解決するた数 本発明で(L 絶縁基板上
に導電膜を形成し 前記導電膜上に絶縁膜を形成し 前
記絶縁膜に半導体素子の電極と対応した位置にテーパー
を有する開口部を形成したフォトレジストのエツチング
用マスクを形成し 前記基板の周囲に石英板またはテフ
ロンシート等を配置したチャンバー内において、前記絶
縁膜単独または前記絶縁膜および導電膜の一部にフォト
レジストをエツチングマスクとしてCF、のエツチング
ガスによるドライエツチング法により絶縁基板に対して
垂直に開口部を形成したa  CF、、02・ の混合
ガスによりフォトレジストのテーパー部分を後退させな
がら更にエツチングすることにより前記絶縁膜単独また
は前記絶縁膜および導電膜の一部に滑らかなテーパーを
形成した微 02プラズマまたはレジスト剥離剤により
フォトレジストを除去した檄 前記開口部に電解めっき
法によりAU等の金属突起を形成することを特徴とする
金属突起形成基板への開口部の形成方法を用((金属突
起を離脱させた眞 前記開口部に繰り返し金属突起を形
成することを特徴とする方法を提供すム作用 本発明のごとく、転写用バンブ形成基板のめっき用マス
クとして用いる絶縁膜単独または前記絶縁膜および導電
膜の一部にフォトレジストをエツチングマスクとしてC
F、のエツチングガスによるドライエツチング法により
垂直に開口部を形成した後、CF、、02の混合ガスに
よりフォトレジストのテーパー部分を後退させながら更
にエツチングすることにより前記絶縁膜単独または前記
絶縁膜および導電膜の一部に前記絶縁膜や導電膜の膜厚
やエッチレートに依存することなく滑らかなテーパーを
有する開口部を安定して形成することができも 実施例 本発明の一実施例にかかる方法を第1皿 第2図ととも
に説明すも まず第1図において金属突起形成基板につ
いて説明すも 絶縁基板1上に導電膜2、3、4を全面
に形成すも 絶縁基板1にはセラミツ久 ガラス等を用
u%  導電膜2にはガラス等と化学結合をつくりやす
いTiを用1.X、次に この導電膜2上に電解めっき
の電極となる導電膜3を形成すム 導電膜3にはPtを
用いも導電膜3上にめっき用マスクとなる絶縁膜5と化
学結合を形成しやすい導電膜4を形成すも 導電M4は
Tiを用いも 導電膜の成膜にはスパッタ蒸着等を用い
も 絶縁膜5の形成はP−CVD法(プラズマCVD法
)等によりS i 5N=IIE (以下P−5iNと
書く。)を約650nm形成する(第1図(a))。こ
の抵 開口部にテーパー8を形成したフォトレジストを
エチングマスク9にして半導体素子の電極に対応した位
置に開口部6を形成すも フォトレジストは東京応化株
式会社製0MR83250cpを用賎 フオトリソ工程
終了後約160℃で加熱することにより開口部にテーパ
ー8を形成する(第1図(b))。テーパー8の角度は
加熱時間により調整すも 開口部6の形成には基板1の
周囲に石英板を配置したチャンバー内においてCF4ガ
スによるドライエツチング方によりP−3iNに絶縁基
板1に対して垂直に開口部6を形成する(第1図(C)
)。次いでCF、、02混合ガスによるドライエツチン
グ法によりフォトレジストのエツチングマスク9と絶縁
膜5を同時にエツチングすることによりフォトレジスト
のエツチングマスク9の開口部テーパー8を後退させな
がら絶縁膜5をエツチングすることにより開口部6にテ
ーパーlOを形成する(第1図(d))。テーパー10
の角度はフォトレジストのテーパー8の角度により調整
すa この後o2プラズマによりフォトレジストを除去
する(第1図(e))。
DETAILED DESCRIPTION OF THE INVENTION Industrial Application Field of the Invention The present invention 1 relates to a method for manufacturing a metal protrusion-formed substrate for forming bumps used in a transfer bump method which is a semiconductor mounting method.Prior art Conventional metal protrusions The manufacturing method of the formed substrate and the transfer bump mounting method will be explained with reference to the third plate and FIG.
Although the conductive film 32 is formed on the entire surface of the insulating substrate 31, it is preferable to use ceramic glass or the like for the insulating substrate 31.
Next, an insulating film to be used as a plating mask 33 is formed on the entire surface of the conductive film 32, and a photoresist is used as an etching mask to form a tapered film at a position corresponding to the electrode of the semiconductor element. Opening 34 with
This plating mask 33 is generally made of P-C.
Using inorganic thin films such as 5ide and 5isN4 formed by VD method etc., the film thickness is from about 500nm to 11000nm.
In terms of degree, CF=, Oe for the formation of the opening.
A dry etching method is used to form a metal protrusion (Au) on the upper surface of the conductive film 32 in the opening 34 formed in the plating mask 33 by electroplating using the conductive film 32 as a plating electrode. Thereafter, the bumps and priming are formed, and then the bumps 35 formed on the bump forming substrate 31 are aligned with the inner leads 42 of the film carrier 41 as shown in FIG. 4(a).FIG. 4(b) As shown in FIG. 4(c), the bump 35 and the inner lead 42 are bonded together by applying pressure with the heated pressure tool 43a.The pressure tool 43 is released as shown in FIG. Transfer to 42a Next
As shown in FIG. 4(d), the inner lead 42 with the bump 35 and the aluminum electrode 45 of the semiconductor element 44 are aligned L/%.As shown in FIG. 4(e), the pressure tool 43
After that, as shown in FIG. 4(f), the pressure is released and the mounting of the semiconductor element 44 is completed. Problems to be Solved by the Invention When used again as a plating substrate for bump formation, however, the conventional example has the following problems. It is necessary to form a smooth taper, however, when the conventional insulating film is thick or the conductive film is made of Ti.
When a three-layer film such as /Pt/Ti is used, Ti must be etched, but since Ti has a slow etching rate, there is a problem that the photoresist etching mask is used up before the opening is formed. The present invention provides an opening formation method for stably forming a tapered opening in an insulating film of a metal protrusion forming substrate or a film with a slow etch rate. In order to solve the problems, the present invention (L) forms a conductive film on an insulating substrate, forms an insulating film on the conductive film, and forms a tapered opening in the insulating film at a position corresponding to an electrode of a semiconductor element. CF-etching the photoresist as an etching mask on the insulating film alone or on a part of the insulating film and the conductive film in a chamber in which a quartz plate, a Teflon sheet, etc. is arranged around the substrate. An opening is formed perpendicularly to the insulating substrate by dry etching using an etching gas of . A method in which a smooth taper is formed on a part of the insulating film and the conductive film, and the photoresist is removed using plasma or a resist stripping agent.Metal protrusions such as AU are formed in the openings by electrolytic plating. The present invention provides a method for forming openings in a metal protrusion-forming substrate ((a method for forming metal protrusions repeatedly in the openings after the metal protrusions have been removed). A photoresist is applied as an etching mask to the insulating film alone or to a part of the insulating film and conductive film used as a plating mask for the bump-forming substrate.
After forming a vertical opening by a dry etching method using an etching gas of CF, etching is further performed while receding the tapered portion of the photoresist with a mixed gas of CF,. According to an embodiment of the present invention, an opening having a smooth taper can be stably formed in a part of the conductive film, regardless of the thickness or etch rate of the insulating film or the conductive film. The method will be explained with reference to the first plate and FIG. Use glass, etc. u% Use Ti for the conductive film 2, which easily forms chemical bonds with glass, etc. 1. X, Next, a conductive film 3 is formed on this conductive film 2 to become an electrode for electrolytic plating. Pt is used for the conductive film 3, but a chemical bond is formed on the conductive film 3 with an insulating film 5 which becomes a mask for plating. The conductive film 4 can be easily formed by using Ti for the conductive M4.The conductive film can be formed by sputter deposition, etc.The insulating film 5 can be formed by the P-CVD method (plasma CVD method), etc. IIE (hereinafter referred to as P-5iN) is formed to a thickness of about 650 nm (FIG. 1(a)). Using the photoresist with a taper 8 formed in the opening of this resistor as an etching mask 9, an opening 6 is formed at a position corresponding to the electrode of the semiconductor element.The photoresist used is 0MR83250cp manufactured by Tokyo Ohka Co., Ltd. After the photolithography process is completed, approximately A taper 8 is formed in the opening by heating at 160° C. (FIG. 1(b)). The angle of the taper 8 is adjusted by the heating time.To form the opening 6, the P-3iN is etched perpendicularly to the insulating substrate 1 by dry etching using CF4 gas in a chamber with a quartz plate placed around the substrate 1. Forming the opening 6 (Fig. 1(C)
). Next, the photoresist etching mask 9 and the insulating film 5 are simultaneously etched by a dry etching method using a CF, 02 mixed gas, thereby etching the insulating film 5 while retracting the opening taper 8 of the photoresist etching mask 9. A taper lO is formed in the opening 6 (FIG. 1(d)). taper 10
The angle of is adjusted by the angle of the taper 8 of the photoresist. After that, the photoresist is removed by O2 plasma (FIG. 1(e)).

次く 第1図(f)に示すように 開口部6に導電膜3
をめっき電極として電解めっき法により金属突起 バン
ブ7を形成すも 次に 第2図(a)に示すようにバンプ形成基板20上
に形成したバンブ7とフィルムキャリア21のインナー
リード22とを位置合わせし 第2図(b)に示すよう
に加熱した加圧ツール23によって加圧することによっ
てバンブ7とインナーリード22とを接合すム その眞
 第2図(c)に示すように加圧ツール23を解除しバ
ンブ7をインナーリード22へ転写すム 次へ 第2図
(d)に示すようにバンブ7つきインナーリード22と
半導体素子24のアルミ電極25とを位置合わせL 第
2図(e)に示すように加圧ツール23によって一括接
合すもこの後第2図(f)に示すように加圧を解除し 
半導体素子24の実装を完了すム バンブ7を離脱させ
た基板1に繰り返し電解めっき法によりバンブ7を形成
すも 発明の効果 本発明のごとく、転写用バンプ形成基板のめっき用マス
クとして用いる絶縁膜単独または前記絶縁膜および導電
膜の一部にフォトレジストをエツチングマスクとしてC
F、のエツチングガスによるドライエツチング法により
垂直に開口部を前記形成したム CF、、02の混合ガ
スによりフォトレジストのテーパー部分を後退させなが
ら更にエツチングすることにより前記絶縁膜単独または
前記絶縁膜および導電膜の一部に前記絶縁膜や導電膜の
膜厚やエッチレートに依存することなく、形成したバン
ブをスムーズに転写するために必要な滑らかなテーパー
を有する開口部を安定して形成することができ、半導体
装置の実装に十分に寄与するものであム
Next, as shown in FIG. 1(f), a conductive film 3 is placed in the opening 6.
Metal protrusions and bumps 7 are formed by electrolytic plating using the metal bumps 7 as plating electrodes.Next, as shown in FIG. As shown in FIG. 2(b), the bump 7 and the inner lead 22 are joined by applying pressure with the heated pressure tool 23. As shown in FIG. 2(c), the pressure tool 23 is Release the bump 7 and transfer it to the inner lead 22. Next Align the inner lead 22 with the bump 7 and the aluminum electrode 25 of the semiconductor element 24 as shown in FIG. 2(d) L as shown in FIG. 2(e). As shown in FIG. 2(f), the pressure is released after joining the plums all at once using the pressure tool 23.
After completing the mounting of the semiconductor element 24, bumps 7 are formed on the substrate 1 from which the bumps 7 have been removed by repeated electrolytic plating.Advantages of the InventionAs in the present invention, an insulating film used as a plating mask for a bump-forming substrate for transfer. C using a photoresist as an etching mask alone or on a part of the insulating film and conductive film.
The insulating film alone or the insulating film and To stably form an opening having a smooth taper necessary for smoothly transferring a formed bump in a part of a conductive film, regardless of the film thickness or etch rate of the insulating film or conductive film. It is a material that can fully contribute to the mounting of semiconductor devices.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例に用いたバンブ形成基板の形
成プロセス断面図 第2図は本発明におけるバンブのリ
ードへの転写工程と、バンブっきリードと半導体素子と
の接合工程を示す断面医第3図は従来におけるバンプ形
成基板の断面医第4図は同従来例のバンブとリードの接
合工程と、バンブつきリードと半導体素子の接合を示す
断面図であも 1・・・絶縁基jfi、2・・・第1層目導電lL 3
・・・第2層目導電11L4・・・第3層目導電風 5
・・・絶縁膜マス久 6・・・開口部 7・・・バンプ
 8・・・フォトレジスト開口部テーパー、 9・・・
フォトレジストのエツチングマス久 10・・・開口部
テーパー。 −〜すφI/)鵠ト働昏ミ
FIG. 1 is a cross-sectional view of the formation process of a bump-formed substrate used in an embodiment of the present invention. FIG. 2 shows the process of transferring bumps to leads and the process of bonding bump-plated leads to semiconductor elements in the present invention. Fig. 3 is a cross-sectional view of a conventional bump-forming substrate. Fig. 4 is a cross-sectional view showing the process of bonding bumps and leads and the bonding of bumped leads and semiconductor elements in the same conventional example. Group jfi, 2...first layer conductivity lL 3
...Second layer conductive 11L4...Third layer conductive wind 5
... Insulating film mass length 6... Opening 7... Bump 8... Photoresist opening taper, 9...
Photoresist etching mask length 10...Opening taper. -~suφI/) Mouse work

Claims (2)

【特許請求の範囲】[Claims] (1)絶縁基板上に導電膜を形成し、前記導電膜上に絶
縁膜を形成し、前記絶縁膜に半導体素子の電極と対応し
た位置にテーパーを有する開口部を形成したフォトレジ
ストのエッチング用マスクを形成し、前記基板の周囲に
石英板またはテフロンシート等を配置したチャンバー内
において、前記絶縁膜単独または前記絶縁膜および導電
膜の一部にフォトレジストをエッチングマスクとしてC
F_4のエッチングガスによるドライエッチング法によ
り絶縁基板に対して垂直に開口部を形成した後、CF_
4、O_2の混合ガスによりフォトレジストのテーパー
部分を後退させながら更にエッチングすることにより前
記絶縁膜単独または前記絶縁膜および導電膜の一部に滑
らかなテーパーを形成した後、O_2プラズマまたはレ
ジスト剥離剤によりフォトレジストを除去した後、前記
開口部に電解めっき法によりAu等の金属突起を形成す
ることを特徴とする金属突起形成基板への開口部の形成
方法。
(1) For photoresist etching, in which a conductive film is formed on an insulating substrate, an insulating film is formed on the conductive film, and a tapered opening is formed in the insulating film at a position corresponding to the electrode of a semiconductor element. In a chamber in which a mask is formed and a quartz plate or a Teflon sheet is arranged around the substrate, a photoresist is etched as an etching mask on the insulating film alone or on a part of the insulating film and the conductive film.
After forming an opening perpendicular to the insulating substrate by dry etching using an etching gas of F_4, CF_
4. After further etching the tapered portion of the photoresist using a mixed gas of O_2 to form a smooth taper on the insulating film alone or on a part of the insulating film and the conductive film, O_2 plasma or a resist stripping agent is applied. 1. A method for forming an opening in a metal protrusion-formed substrate, the method comprising: removing the photoresist, and then forming a metal protrusion of Au or the like in the opening by electrolytic plating.
(2)金属突起を離脱させた後、前記開口部に繰り返し
金属突起を形成することを特徴とする特許請求の範囲第
1項記載の金属突起形成基板への開口部の形成方法。
(2) The method for forming an opening in a metal protrusion-formed substrate according to claim 1, wherein the metal protrusion is repeatedly formed in the opening after the metal protrusion is removed.
JP2295772A 1990-10-31 1990-10-31 Method of forming an opening in a metal projection forming substrate Expired - Lifetime JP2785474B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2295772A JP2785474B2 (en) 1990-10-31 1990-10-31 Method of forming an opening in a metal projection forming substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2295772A JP2785474B2 (en) 1990-10-31 1990-10-31 Method of forming an opening in a metal projection forming substrate

Publications (2)

Publication Number Publication Date
JPH04167536A true JPH04167536A (en) 1992-06-15
JP2785474B2 JP2785474B2 (en) 1998-08-13

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JP2295772A Expired - Lifetime JP2785474B2 (en) 1990-10-31 1990-10-31 Method of forming an opening in a metal projection forming substrate

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