JPH04167296A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To suppress the electric energy consumption supplied from a power source and extend the service life of the power source by controlling the power source which is supplied to a main memory block which forms a main memory in conformity with a specified capacity required to the main memory. CONSTITUTION:N sets of power source control buffers 6 in a main memory (N stands for integer greater than 1) control the propriety of power supply in conformity with N sets of memory blocks 2 in the main memory 1 respectively and decides the location of a block 2 which stores no data in the main memory 1 based on the final address of input data. A buffer control section 5 transmits a specified control signal to a power source control buffer 6 responding to the block 2 in order to control the supply of a power source 7 to the block 2. This construction makes it possible to suppress the power consumption and extend the service life of the power source 7.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a semiconductor memory device.

[Conventional technology]

Conventionally, this type of semiconductor storage device has been equipped with a low power consumption mode to extend the life of the backup battery, which allows data to be retained for a long time without being accessed by the CPU. If you try,
By operating in the low power consumption mode, it is possible to suppress power consumption to about a few tenths.

[Problem to be solved by the invention]

Although the above-mentioned conventional semiconductor memory devices are equipped with low power consumption modes, current personal data input/output devices such as electronic notebooks, electronic telephone directories, and electronic phone dialers are not equipped with low power consumption modes. Semiconductor storage devices are becoming mainstream as storage devices. Furthermore, since storage capacity tends to increase, the number of semiconductor memory devices increases as the storage capacity increases, and the power consumption thereof also tends to increase accordingly. For this reason, there is a drawback that the life of the backup battery is shortened, and the battery replacement cycle is shortened in parallel with the increase in capacity.

[Means to solve the problem]

The semiconductor storage device of the present invention includes a main memory configured with N main memory blocks (N is an integer greater than 1), and a main memory that corresponds to each of the N main memory blocks. , N power control buffers that control whether or not power is supplied, and the main memory,
Power control for the main memory block in order to determine the location of the main memory block where no data is stored based on the final address of the input data, and to control the supply of power to the main memory block. and a buffer control section that sends a predetermined control signal to the buffer.

〔Example〕

Next, the present invention will be explained with reference to the drawings. FIG. 1 is a block diagram showing a first embodiment of the present invention. As shown in FIG. 1, the present embodiment includes a main memory 1 including a plurality of main memory blocks 2, a sub memory 3, a DMA control section 4, a buffer control section 5, and a plurality of main memory blocks 2. It is configured to include a plurality of power supply control buffers 6 corresponding to each of the main memory blocks 2, and a power supply 7. Further, FIG. 2 is a flow chart diagram showing the operating procedure of this embodiment. Below, Figure 1 and 2
The operation of this embodiment will be explained with reference to the drawings.

First, in the initial state, each register inside the buffer control unit 5 is cleared, and then 1 is added to the ST (sub memory top address) register. In this state, the initial value setting is completed and the system is ready to wait for data input from the host device.

When data is input via bus 201, the data is written to address ST inside sub-memory 3. If the data is not completed, 1 is added to the value of the ST register, and data input and sub-
Writing to the ST address of the memory 3 is performed repeatedly. When the end of data is detected, the value of the ST register is written to the SE (sub memory end address) register, and then the value of the ST register is written to the ME (main memory end address) register and the SE register. The values of are added to obtain a comprehensive final address (memory capacity), which is written to the AT (final address) register.

Next, in the buffer control unit 5, since the final address of the main memory 1 is determined from the value written in the AT register, the main memory block 2 corresponding to the address is extracted. And this main
Outputs the l1lal signal for releasing the power supply buffer 6 for the memory block 2. In response to this control signal, power supply to the corresponding main memory block 2 is started, and among the plurality of main memory blocks 2, only the corresponding main memory block 2 necessary for the operation of the main memory 1 is supplied with power. Power is supplied to ensure its operational state. That is, for main memory 1,
The minimum power required for operation is supplied.

Next, addresses for data transfer are set by adding 1 to each of the ST register and ME register. When the preparation process up to this stage is completed, the DMA control unit 4 transfers the data (ST address) written in the sub memory 3 to the address ME in the main memory 1. After this transfer is completed, the ST register and M
One is added to each of the E registers to address up, and data transfer continues. In this data transfer work, all data in sub memory 3 is transferred to address S.
This is repeated until it is transferred to address T. When all data transfer is completed, the data in the ST register is cleared and becomes 1.
is assigned, and the initial state of data input is restored. This operation is repeated until the input data is completed.

Next, a second embodiment of the present invention will be described. FIG. 3 is a block diagram showing a second embodiment of the present invention. As shown in FIG. 3, this embodiment includes a main memory 8 including a plurality of main memory blocks 9, a buffer control section 10, and a main memory block 9.
The power supply control buffer 12 includes a plurality of power supply control buffers 11 and a power supply 12, respectively corresponding to the power supply control buffers 11 and the power supply 12. Further, FIG. 4 is a flow chart diagram showing the operating procedure of this embodiment. The operation of this embodiment will be described below with reference to FIGS. 3 and 4.

As is clear from FIG. 3, the difference between this embodiment and the first embodiment is that this embodiment does not include a sub-memory and a DMA control section.

First, in the initial state, each register inside the buffer control section 10 is cleared. Next, it waits for data input from the host device, and when the data is input, the value of the LA register where the last address of main memory 8 is stored and the input address of the data that has just been input are stored. The sum of the values of the IA addresses is written to the WA address as the write address for the main memory 8.

Next, the buffer control unit 10 checks the address, but since the address is determined for each main memory block 9, it is necessary to use a new main memory block depending on the contents of the WA address. If it is determined whether or not the memory is to be expanded, a WAIT signal 101 is output and an alarm is issued to the host device. During that time, as in the case of the first embodiment, the buffer control unit IO
A control signal for canceling the power supply control buffer 11 is output, and this control signal causes the corresponding main memory
Power supply to the block 9 is started, and only the main memory block corresponding to the capacity value required for the operation of the main memory 1 out of the plurality of main memory blocks 9 is kept in an operating state.

Then, the W A T F signal 101 is canceled, the alarm for the host device is canceled, and the input data is written to the address WA. Even if
At the time of address check, if memory expansion is not required, the input data is immediately written to address WA. Then, if the data is not completed, further data input from the host device is awaited, and the same operation is repeated thereafter.

〔Effect of the invention〕

As explained above in detail, the present invention provides personal
Applied to data input/output devices, it controls the power supplied to the main memory blocks forming the main memory in accordance with the required capacity of the main memory, and reduces the power consumption of the supplied power. By suppressing this, it is possible to extend the life of the power supply.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 and FIG. 3 are block diagrams showing first and second embodiments of the present invention, respectively, and FIG. 2 and FIG.
FIG. 3 is a flow chart diagram showing the operating procedure in the first and second embodiments, respectively. In the figure, 1.8...Main memory, 2゜9...Main memory block, 3...
...Sub memory, 4...DMA control unit, 5.
10...--Buffer control unit, 6, 11...
- Power supply control buffer, 7, 12...Power supply.

Claims (1)

[Scope of Claims] A main memory configured with N main memory blocks (N is an integer greater than 1), and a power source corresponding to each of the N main memory blocks. N power supply control buffers that control whether or not to supply power, and determining the location of a main memory block in which no data is stored in the main memory based on the final address of input data, and A semiconductor memory device comprising: a buffer control section that sends a predetermined control signal to a power control buffer corresponding to the main memory block in order to control power supply.