JPH04163943A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the exposure of the metallic wiring at an isolated part by connecting the conductor on an interlayer film and the metallic layer on an interlayer film with each other by the metallic layer consisting of two layers. CONSTITUTION:The metallic wiring 4 as the conductor below an interlayer film 6a and the metallic layer 7 on the interlayer film 6a are connected by the metallic layer consisting of at least two layers, that is, a pillar 5 and a sputtered metallic layer 9. Hereby, it becomes possible to make a high pillar by usual photoresist mask and plating methods, and when the pillar is exposed by etching back the interlayer film, the metallic wiring at the isolated part can be prevented from being exposed. Accordingly, the shortage of the upper layer wiring can be prevented.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a semiconductor device having a multilayer wiring structure.

[Conventional technology]

FIG. 3 shows the cross-sectional structure of a conventional multilayer wiring in which layers are connected using pillars. In FIG.
A 0.5 to 1.0 μm layer of metal wiring 4 is formed through the metal wire 4 .

The pillar 5 has a height of 1.5 to 2.0 μm and a thickness of 1000 to 2.0 μm.
The metal wiring 4 and the metal wiring 8 are connected through a sputtered metal layer 7 of 2,000 layers.

The metal wiring 4 and the pillar 5 are formed by electroplating using a photoresist as a mask, using the metal layer 3 sputtered on the entire surface of the insulating film 2 as a power supply electrode. Further, unnecessary sputtered metal layer 3 is removed by etching using metal wiring 4 as a mask.

Pillar 5 is installed using a photoresist mask and electroplated.
When forming the pillar 5, the pillar 5 can be made external to the metal wiring 4, so the overlapping margin between the metal wiring 4 and the pillar 5 can be reduced.

The interlayer film 6 may be applied to the entire surface of the substrate in advance, and then etched back until the upper portions of the pillars 5 are exposed.

Sputtered metal layer 7 is a power supply electrode when metal wiring 8 is formed.

[Problem to be solved by the invention]

In conventional semiconductor devices, it is difficult to pattern minute holes of 1 μm or less in photoresist with a thickness of 3 to 4 μm, so it is extremely difficult to increase the height of pillars to 2 μm or more. , on an isolated pattern, it may be less than 1/2 of that on a dense pattern, so if the coated insulating film is etched back to expose the pillars on the dense pattern, the metal on the isolated pattern will be removed, as shown in Figure 4. There was a problem in that the wiring 4 was also exposed at the same time, resulting in a short circuit with the upper layer wiring.

An object of the present invention is to provide a semiconductor device in which exposure of metal wiring in an isolated pattern portion is prevented.

[Means to solve the problem]

In order to achieve the above object, in a semiconductor device according to the present invention, the coating film is an interlayer insulating film, and a multilayer wiring is formed using a pillar method for interlayer connection. The upper metal layer is connected to the upper metal layer through at least two metal layers.

[Function] By connecting the conductor in the lower interlayer layer and the metal layer in the upper layer of the interlayer film through a two-layer metal layer, exposure of the metal wiring in the isolated pattern portion is prevented.

〔Example〕

Next, the present invention will be described with reference to the drawings. 6 (Example 1) FIG. 1 is a sectional view showing Example 1 of the present invention.

In the figure, a layer with a thickness of 1000 mm is formed on the insulating film 2 of the semiconductor substrate 1.
Approximately 0 sputtered metal layer 3 is formed.

The sputtered metal layer 3 is used as a power supply electrode when forming the metal wiring 4 by the plating method, and after plating, etching is performed using the metal wiring 4 as a mask to remove the sputtered metal layer 3. At least the upper part of the metal wiring 4 needs to be exposed above the coating interlayer film 6.

Further, a sputtered metal layer 9 is formed on the metal wiring 4, and the sputtered metal layer 9 is formed by etching back the applied interlayer film 6 to expose the upper part of the metal wiring 4, and then sputtering over the entire surface of the substrate. This is a power supply electrode when forming a . Unnecessary sputtered metal layer 9 is removed by etching using pillar 5 as a mask.

It is desirable that the processing rate of the sputtered metal layer 9 be as large as possible compared to the metal of the pillar 5.

Furthermore, a coating interlayer film 6a is formed by coating between the pairs of adjacent pillars 5 and sputtered metal layers 9.
A sputtered metal layer 7 is formed on a in contact with the pillar 5. A metal wiring 8 is formed using this sputtered metal layer 7 as a power supply electrode.

As described above, the present invention replaces the metal wiring 4 as the lower conductor of the interlayer M6a and the upper metal layer 7 of the interlayer J16a with at least two metal layers (in the embodiment, the pillar 5
and a sputtered metal layer 9). This makes it possible to form pillars with a height of 2 μm or more using a regular photoresist mask and plating method, and prevents metal wiring in isolated areas from being exposed when the interlayer film is etched back to expose the pillars. It becomes possible.

(Example 2) FIG. 2 is a sectional view showing a second embodiment of the present invention.

In the figure, a MOS transistor is formed on a semiconductor substrate 1 by a diffusion layer 10 and a gate pole 72, and a gate t! f! A gate oxide film 611 is covered with a coated interlayer film 6 having a thickness such that 12 is not exposed. A contact hole 13 is provided at a required position on the diffusion layer 10, and a metal layer 9 with a thickness of about 1.0 μm is formed in this by sputtering.
is embedded. This metal layer 9 is sputtered over the entire surface of the coating 11!6 with contact holes made in advance, and after forming the pillar 5 using this as a power supply electrode, etching is performed using the pillar 5 as a mask to form a metal layer only in the contact area. Leave 9.

According to this embodiment, the same effects as in the first embodiment are obtained.

[Effects of the Invention] As explained above, in the present invention, pillars are formed of two or more metal layers, so pillars with a height of 2 μm or more can be formed using an ordinary photoresist mask and plating method, and the interlayer film can be etched back. When the pillar is exposed by doing so, it is possible to prevent the metal wiring in the isolated portion from being exposed, and it is possible to prevent a short circuit with the upper layer wiring.

[Brief explanation of the drawing]

FIG. 1 is a longitudinal sectional view showing a first embodiment of the present invention, FIG. 2 is a longitudinal sectional view showing a second embodiment of the present invention, and FIG. 3 is a longitudinal sectional view showing a conventional example. The sectional view, FIG. 4, is an ItlIuIF plane view showing the problems of the conventional example. 1... Semiconductor substrate 2... Insulating film 3.7.9
...Sputtered metal layer 4.8...Metal wiring 5...Pillar 6.6a.
...Coating interlayer film 10...Diffusion layer 11...Gate oxide film 12...Gate electrode 13...Contact hole Patent applicant NEC Corporation Representative Patent attorney Naka Kanno Figure 2'/ Figure 3

Claims (1)

[Claims] (1) In a semiconductor device in which a coating film is an interlayer insulating film and a multilayer wiring is formed using a pillar method for interlayer connection, a metal layer consisting of at least two layers, a conductor on the upper layer of the interlayer film and a metal layer on the upper layer of the interlayer film. A semiconductor device characterized by being connected by.