JPH04162626A - Manufacture of semiconductor device of multilayer interconnection structure - Google Patents

Abstract

PURPOSE:To enhance the coverage of an interconnection and to eliminate a restriction on the layout design regarding the position of a contact hole by a method wherein a first interlayer insulating film is applied, a spin-on-glass film is applied, a flattening treatment is executed, a second interlayer insulating film is applied and an upper-layer interconnection which is connected to a lower-layer interconnection at the contact hole part is formed. CONSTITUTION:A polysilicon interconnection 1 up to a second interlayer insulating film 6 are formed on a substrate 100; a photoresist film 10 is formed; the photoresist film 10 is patterned. The second interlayer insulating film 6, the SOG film 5 (the silica film) and the first interlayer insulating film 4 are etched down to a halfway part so as to be a taper shape by an isotropic etching operation. The photoresist film 10 is removed; after that, a silicon oxide film (an insulating film 7) is deposited by a CVD method. A photoresist film 11 is patterned; a contact hole is completed by an anisotropic etching operation. The photoresist film 11 is removed; in addition, an upper-layer interconnection 8 and a passivation film 9 are formed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming contact holes in a semiconductor device with a multilayer wiring structure.

[Conventional technology]

Part 2 about the conventional manufacturing method of multilayer wiring structure semiconductor device
This will be explained using cross-sectional views shown in FIGS. (d) to (c).

Polysilicon wiring 1 constituting a gate electrode on a substrate 100 in which elements such as MOS transistors are formed on a semiconductor substrate
．． BPSG film with contact holes2. Lower layer wiring such as first layer AJ film 3. Silicon oxide film (first
An interlayer insulating film 4) is sequentially deposited.

Coating and solidifying a silica film on the first interlayer insulating film 4,
A spin-on-glass (SOG) film 5 is formed by etching back, and a silicon oxide film (second interlayer insulating film 6) is deposited by a CVD method.A photoresist is formed by a well-known photolithography technique. membrane 12
A tapered portion of the contact hole is formed by isotropic etching (FIG. 2(a)).

Thereafter, as shown in FIG. 2(b), the formation of the contact hole is completed by anisotropic etching such as reactive ion etching.

Then, upper layer wiring 8 (second layer A, FF film) and passivation film 9 are deposited to obtain the semiconductor device shown in FIG. 2(c).

[Problem to be solved by the invention]

In this conventional method for manufacturing a multilayer wiring structure semiconductor device, since an SOG film is used for planarizing the interlayer film, SOGO2
When a contact hole is opened at a location where O3 exists, the second layer A
! When the two films are deposited, the glass forming agent, organic binder, absorbed moisture, etc. contained in the SOG film are released, and an insulating film is formed on the lower wiring 3. This slanted lower layer wiring 3 and the upper layer wiring can no longer be electrically connected to each other. That is, as shown in FIG. 3, if an attempt is made to taper the first interlayer insulating film 4 to prevent wiring breakage, the SOG film 5 will be exposed in the A section, so the taper will not be applied to the first interlayer insulating film 4. The first problem is that the etching cannot be performed to a size that covers the insulating film 4, resulting in poor wiring coverage.

Further, as shown in FIG. 4, when the pitch of the polysilicon wiring is reduced, the SOG film is exposed in the contact hole portion in the B portion. Therefore, it is necessary to prohibit the formation of contact holes in such locations, resulting in a second problem that the degree of freedom in layout is reduced.

[Means to solve the problem]

The method for manufacturing a multilayer wiring structure semiconductor device of the present invention includes a step of depositing a first interlayer insulating film after forming a lower layer wiring, and a step of depositing a spin-on glass film and performing a planarization process. A step of depositing a second interlayer insulating film, forming a hole with a bottom at a predetermined location in the abdomen of the first interlayer insulating film by isotropic etching, depositing an insulating film, and then etching the hole by anisotropic etching. The method includes the steps of: opening a contact hole in the hole portion to reach the lower layer interconnection; and forming an upper layer interconnection that connects the lower layer interconnection with the contact hole portion.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIGS. 1(a) to 1(d) are cross-sectional views shown in the order of steps for explaining one embodiment of the present invention.

First, as shown in FIG. 1(a), polysilicon interconnects 1 to second interlayer insulating films 6 are formed on a substrate 100, as in the conventional example.
A photoresist film 10 is provided, and the photoresist film 10 is patterned using a well-known photolithography technique. Next, by isotropic etching, the second interlayer insulating film 6, SOG film 5 (silica film), and first interlayer insulating film 4 are etched halfway into a tapered shape.

After removing the photoresist film 1O, as shown in FIG. 2(b), a silicon oxide film (insulating film 7
) is deposited to a thickness of, for example, 300A.

Using photolithography technology, the photoresist film 11 is patterned as shown in FIG. 2(C), and the contact hole formation is completed by anisotropic etching. Next, as shown in FIG. 1(d), the photoresist film 11 is removed, and an upper layer wiring 8 and a passivation film 9 are further formed.

〔Effect of the invention〕

As explained above, in the present invention, gas release from the SOG film can be suppressed by forming the tapered portion at the top of the contact hole and then covering the exposed SOG film with an insulating film. This has the effect of increasing wiring coverage and improving wiring coverage. Furthermore, even if the pitch of the underlying conductor is reduced, there is no restriction on the layout design of the contact hole positions.

[Brief explanation of the drawing]

FIGS. 1(a) to (d) are sectional views shown in the order of steps to explain an embodiment of the present invention, and FIGS. 2(a) to (c) are sectional views shown in the order of steps to explain a conventional example. Cross-sectional view, Figure 3,
FIG. 4 is a sectional view used to assist in explaining the problems of the conventional example. 1... Polysilicon wiring, 2... BPSG film, 3...
...lower layer wiring, 4...first interlayer insulating film, 5...S
OG film, 6... second interlayer insulating film, 7... insulating film,
8... Upper layer wiring, 9... Passivation film, 10
．． 11゜12...Photoresist film.

Claims (1)

[Claims] 1. A step of depositing a first interlayer insulating film after forming the lower layer interconnection, and a step of depositing a second interlayer insulating film after depositing a spin-on glass film and performing a planarization process. A step of depositing a film, and isotropic etching to form a hole with a bottom in the first interlayer insulating film portion at a predetermined location, and after depositing an insulating film, anisotropic etching is performed to form a hole with a bottom in the first interlayer insulating film portion. A method for manufacturing a multilayer wiring structure semiconductor device, comprising the steps of: opening a contact hole that reaches a lower layer wiring; and forming an upper layer wiring that connects the lower layer wiring through the contact hole. 2. The method for manufacturing a multilayer wiring structure semiconductor device according to claim 1, wherein the spin-on glass film is a silica film.