JPH04162451A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH04162451A JPH04162451A JP28614990A JP28614990A JPH04162451A JP H04162451 A JPH04162451 A JP H04162451A JP 28614990 A JP28614990 A JP 28614990A JP 28614990 A JP28614990 A JP 28614990A JP H04162451 A JPH04162451 A JP H04162451A
- Authority
- JP
- Japan
- Prior art keywords
- film
- insulating film
- aluminum
- hole pattern
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 9
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 230000001681 protective effect Effects 0.000 claims abstract description 7
- 238000000034 method Methods 0.000 claims description 10
- 238000000576 coating method Methods 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 15
- 229910052782 aluminium Inorganic materials 0.000 abstract description 15
- 238000010894 electron beam technology Methods 0.000 abstract description 7
- 229920003229 poly(methyl methacrylate) Polymers 0.000 abstract description 5
- 239000004926 polymethyl methacrylate Substances 0.000 abstract description 5
- 238000009826 distribution Methods 0.000 abstract description 4
- 230000005684 electric field Effects 0.000 abstract description 4
- 238000006073 displacement reaction Methods 0.000 abstract 2
- 238000005452 bending Methods 0.000 abstract 1
- 230000003292 diminished effect Effects 0.000 abstract 1
- 239000000463 material Substances 0.000 description 7
- NTIZESTWPVYFNL-UHFFFAOYSA-N Methyl isobutyl ketone Chemical compound CC(C)CC(C)=O NTIZESTWPVYFNL-UHFFFAOYSA-N 0.000 description 2
- UIHCLUNTQKBZGK-UHFFFAOYSA-N Methyl isobutyl ketone Natural products CCC(C)C(C)=O UIHCLUNTQKBZGK-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- VCTKAGXMHJMPLL-UHFFFAOYSA-N acetic acid;methyl 2-methylprop-2-enoate Chemical compound CC(O)=O.COC(=O)C(C)=C VCTKAGXMHJMPLL-UHFFFAOYSA-N 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 239000000460 chlorine Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000000609 electron-beam lithography Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の製造方法に関し、特に多層配線の
形成方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for forming multilayer wiring.
従来、半導体装置の製造工程において、半導体基板上に
荷電ビームを用いて、下層配線と上層配線を接続するた
めに、絶縁膜にホールを形成する場合以下のように行っ
てきた。まず下層配線を覆う絶縁膜上にレジスト膜を塗
布法で形成し、荷電ビームでホールパターンを描画した
後に貌像しレジストパターンを形成する。次にレジスト
パターンを保護膜として絶縁膜をエツチングしてホール
を形成する。最後にレジストパターンを剥離した後に上
層線を形成する。Conventionally, in the manufacturing process of a semiconductor device, a charged beam has been used on a semiconductor substrate to form a hole in an insulating film in order to connect a lower layer wiring and an upper layer wiring as follows. First, a resist film is formed by a coating method on an insulating film covering the lower wiring, and a hole pattern is drawn using a charged beam, and then the resist pattern is formed by imaging. Next, the insulating film is etched using the resist pattern as a protective film to form holes. Finally, after peeling off the resist pattern, upper layer lines are formed.
しかし、絶縁膜上のレジスト膜に荷電ビームを用いてホ
ールパターンを描画する場合、・絶縁膜とレジスト膜を
合計した厚みは数μｍに達する場合もある。このように
厚い絶縁膜上に電子ビームを照射してパターンを描画す
ると、絶縁膜内に電子が蓄積される。この蓄積された電
子によって電子ビームが反発を受は軌道が曲けられるの
て、目合わせずれが生じたり、フィールド接続ずれが生
じたりする。However, when drawing a hole pattern on a resist film on an insulating film using a charged beam, the total thickness of the insulating film and the resist film may reach several μm. When a pattern is drawn by irradiating an electron beam onto such a thick insulating film, electrons are accumulated within the insulating film. The electron beam is repelled by the accumulated electrons and its trajectory is bent, resulting in misalignment or field connection misalignment.
本発明はこのような問題点を解決するためになされたも
ので、絶縁膜上のレジスト膜にホールパターンを電子ビ
ームで描画する場合に、目合わせずれか小さく、フィー
ルドつなぎのずれが小さい描画が可能な半導体装置の製
造方法を提供することを目的にしている。The present invention has been made to solve these problems, and it is possible to draw a hole pattern on a resist film on an insulating film with a small alignment error and with a small deviation in field connection when drawing a hole pattern with an electron beam. The purpose of this research is to provide a method for manufacturing semiconductor devices that is possible.
本発明の半導体装置の製造方法は、下層配線を覆う絶縁
膜上にシールド層を形成する工程と、シールド層上にレ
ジスト膜を塗布法で形成し荷電ビームで露光し現像して
レジストパターンを形成する工程と、このレジストパタ
ーンを保護膜にして前記シールド層をエツチング後、前
記絶縁膜をエツチングして下層配線を露出させる工程と
、レジストパターンを除去した後前記下層配線に接続す
る上層配線を形成する工程とを含んで構成される。The method for manufacturing a semiconductor device of the present invention includes the steps of forming a shield layer on an insulating film covering lower wiring, and forming a resist film on the shield layer by a coating method, exposing it to a charged beam and developing it to form a resist pattern. a step of etching the shield layer using the resist pattern as a protective film, etching the insulating film to expose the lower layer wiring, and forming an upper layer wiring connected to the lower layer wiring after removing the resist pattern. The process includes the steps of:
本発明の方法によれは、レジスト膜と絶縁膜の間にシー
ルド層が形成されているので、荷電ビームで描画した場
合にも、絶縁膜内に蓄積した荷電粒子からの電界分布が
このシールド層によって終端されて、外部には漏れない
。この結果、電子ビームの軌道か曲げられないので目合
わせずれか小さく、フィールドつなぎのずれか小さい描
画か可能になる。シールド層として上層配線材料と同し
ものを使用すれば上層配線とシールド層のエツチングを
同時に行えるので、工程の増加をシールド層上ン
〔実施例〕
以下、本発明の実施例について図面を参照して説明する
。According to the method of the present invention, since a shield layer is formed between the resist film and the insulating film, even when writing with a charged beam, the electric field distribution from the charged particles accumulated in the insulating film is It is terminated by a terminal so that it does not leak to the outside. As a result, since the trajectory of the electron beam is not bent, it is possible to perform writing with small alignment errors and small field connection errors. If the same material as the upper layer wiring is used for the shield layer, the upper layer wiring and the shield layer can be etched at the same time. I will explain.
第１図（ａ）から（ｄ）は本発明の一実施例を説明する
ための半導体チップの断面図である。FIGS. 1(a) to 1(d) are cross-sectional views of a semiconductor chip for explaining one embodiment of the present invention.
まず第１図（ａ＞に示すように、下層配線１．３を覆う
ＰＳＧ膜等からなる絶縁膜１４上にシールド層として厚
さ５０ｎｍのアルミ膜１２をスパッタ法により形成する
。更に、ポジ型のレジスト膜１１としてＰＭＭＡ （ポ
リ・メ・チル・メタクリレート・アセテート〉を厚さ１
．０μｍスピン塗布する。次で、電子線描画装置により
下層配線の所望位置に目合わせを行いホールパターンを
描画する。描画中はアルミ膜をグランドに落として零電
位に保持しているので、絶縁膜中に蓄積された電子から
の電界分布がシールドされるので、電子ビームの軌道は
曲げられることはない。この結果、目合わせずれやフィ
ールド接続ずれのないレジストパターンを得ることがで
きる。その後、ＭＩＢＫ（メチル・イソブチル・ケトン
）により現像する。First, as shown in FIG. 1 (a), an aluminum film 12 with a thickness of 50 nm is formed as a shield layer on an insulating film 14 made of a PSG film or the like that covers the lower wiring 1.3 by sputtering. PMMA (poly methyl methacrylate acetate) is used as the resist film 11 to a thickness of 1
．． 0 μm spin coating. Next, an electron beam lithography device is used to align the lower wiring at a desired position and draw a hole pattern. During writing, the aluminum film is grounded and held at zero potential, so the electric field distribution from the electrons accumulated in the insulating film is shielded, so the trajectory of the electron beam is not bent. As a result, a resist pattern without misalignment or field connection misalignment can be obtained. Thereafter, it is developed with MIBK (methyl isobutyl ketone).
次に第１図（ｂ）に示すように、ＰＭＭＡのホールパタ
ーンを保護膜にして塩素系のカスを用いてアルミ膜１２
をドライエツチングする。次に第１図（ｃ）に示すよう
に、レジスト膜１１およびアルミ膜１２から形成された
ホールパターンを保護膜にして、フッ素系のガスにより
絶縁膜１４をドライエツチングする。最後に第１図（ｄ
）に示すように、上層配線１５としてアルミをスパッタ
形成する。シールド材料１２と上層配線材料１５は同一
材料のアルミを使用しているので、上層配線１５と同時
にシールド層１２のドライエツチングができる。Next, as shown in FIG. 1(b), the hole pattern of PMMA is used as a protective film and chlorine-based scum is used to form an aluminum film 12.
Dry etching. Next, as shown in FIG. 1(c), the insulating film 14 is dry-etched using a fluorine-based gas using the hole pattern formed from the resist film 11 and the aluminum film 12 as a protective film. Finally, Figure 1 (d
), aluminum is sputtered to form the upper layer wiring 15. Since the shield material 12 and the upper layer wiring material 15 are made of the same material, aluminum, the shield layer 12 can be dry etched at the same time as the upper layer wiring 15.
第２図はシールド層としてのア辰ミ膜の厚みに対する目
あわせずれを描いたもので′ある。シールド用のアルミ
膜を形成しない従来の方法では、目合わせずれが１．７
μｍあるのに対して、シールド用のアルミ膜を形成する
事により、その膜厚の増加とともに目合わせずれが減少
し、膜厚３０〇八以上で目合わせずれがほぼ一定の最小
になる。FIG. 2 depicts misalignment with respect to the thickness of the tatami film as a shield layer. In the conventional method that does not form an aluminum film for shielding, the misalignment is 1.7
By forming an aluminum film for shielding, the misalignment decreases as the film thickness increases, and when the film thickness is 30.8 μm or more, the misalignment becomes an almost constant minimum.
以上説明したように本発明によれば、レジスト膜と絶縁
膜の間にシールド層が形成されているので、荷電ビーム
で描画した場合に、絶縁膜中に蓄積された電子からの電
界分布が、このシールド層で終端される。この結果、電
子ビームの軌道が曲げられないので目合わせずれか小さ
く、フィールドつなぎのずれが小さい描画が可能になる
。更に、シールド膜としては配線材料と同一材料を使用
すれば、配線材料と同時にトライエラングできるので、
工程数の増加も抑えられる。As explained above, according to the present invention, since the shield layer is formed between the resist film and the insulating film, when drawing is performed with a charged beam, the electric field distribution from the electrons accumulated in the insulating film is It is terminated with this shield layer. As a result, since the trajectory of the electron beam is not bent, it is possible to perform writing with small misalignment and small misalignment of field connections. Furthermore, if the same material as the wiring material is used for the shield film, trial run can be performed at the same time as the wiring material.
An increase in the number of processes can also be suppressed.
第１図（ａ）がら（ｄ）は本発明の一実施例を説明する
ための半導体チップの断面図である。第２図はシールド
用アルミ膜の膜厚に対する目合わせずれの変化を示す図
である。
１１・・・レジスト膜、１２・・・アルミ膜、１３・・
・下層配線、１４・・・絶縁膜、１ら・・・上層配線。FIGS. 1(a) to 1(d) are cross-sectional views of a semiconductor chip for explaining one embodiment of the present invention. FIG. 2 is a diagram showing the change in misalignment with respect to the film thickness of the shielding aluminum film. 11...Resist film, 12...Aluminum film, 13...
・Lower layer wiring, 14...Insulating film, 1 et al....Upper layer wiring.
Claims (1)
と、シールド層上にレジスト膜を塗布法で形成し荷電ビ
ームで露光し現像してレジストパターンを形成する工程
と、このレジストパターンを保護膜にして前記シールド
層をエッチング後、前記絶縁膜をエッチングして下層配
線を露出させる工程と、レジストパターンを除去した後
前記下層配線に接続する上層配線を形成する工程とを含
むことを特徴とする半導体装置の製造方法。A process of forming a shield layer on an insulating film that covers the lower wiring, a process of forming a resist film on the shield layer by a coating method, exposing it to a charged beam and developing it to form a resist pattern, and converting this resist pattern into a protective film. After the shield layer is etched, the insulating film is etched to expose the lower wiring, and after the resist pattern is removed, an upper wiring is formed to connect to the lower wiring. A method for manufacturing a semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28614990A JPH04162451A (en) | 1990-10-24 | 1990-10-24 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28614990A JPH04162451A (en) | 1990-10-24 | 1990-10-24 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04162451A true JPH04162451A (en) | 1992-06-05 |
Family
ID=17700576
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP28614990A Pending JPH04162451A (en) | 1990-10-24 | 1990-10-24 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04162451A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103943599A (en) * | 2013-01-17 | 2014-07-23 | 中国科学院微电子研究所 | Interconnection structure and manufacture method thereof |
-
1990
- 1990-10-24 JP JP28614990A patent/JPH04162451A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103943599A (en) * | 2013-01-17 | 2014-07-23 | 中国科学院微电子研究所 | Interconnection structure and manufacture method thereof |
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