JPH04162112A - Multi-output power supply circuit - Google Patents

Multi-output power supply circuit

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Publication number
JPH04162112A
JPH04162112A JP28903390A JP28903390A JPH04162112A JP H04162112 A JPH04162112 A JP H04162112A JP 28903390 A JP28903390 A JP 28903390A JP 28903390 A JP28903390 A JP 28903390A JP H04162112 A JPH04162112 A JP H04162112A
Authority
JP
Japan
Prior art keywords
power supply
output
voltage
circuit
supply circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP28903390A
Other languages
Japanese (ja)
Other versions
JP2604497B2 (en
Inventor
Tetsuya Takahashi
哲也 高橋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC IC Microcomputer Systems Co Ltd
Original Assignee
NEC IC Microcomputer Systems Co Ltd
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Filing date
Publication date
Application filed by NEC IC Microcomputer Systems Co Ltd filed Critical NEC IC Microcomputer Systems Co Ltd
Priority to JP28903390A priority Critical patent/JP2604497B2/en
Publication of JPH04162112A publication Critical patent/JPH04162112A/en
Application granted granted Critical
Publication of JP2604497B2 publication Critical patent/JP2604497B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Continuous-Control Power Sources That Use Transistors (AREA)

Abstract

PURPOSE:To apply a voltage to one of two power supplies even though the other power supply does not rise up to a prescribed level by adding an overload detecting transistorTR and a current mirror circuit to the multi-output power supply circuit. CONSTITUTION:In this multi-output power supply circuit, the base and the emitter of an NPN TR 37 are connected to the base and the emitter of an NPN TR 9 respectively and the collector of the TR 37 is connected to the collector and the base of a PNP TR 38 serving as the input side of a current mirror circuit and also connected to the base of a PNP TR 39 respectively. Each emitter is provided with a circuit where the output of a PNP current mirror circuit connected to a power terminal 27 is connected to the output of a 1st comparator which decides the sequence of the 1st and 2nd power supply circuits. The overcurrent of the power supply circuit is detected by the TR 37 before the voltage V1 rises up to a prescribed level. Then the TR 14 and 15 are turned on and the output voltage V2 rises.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、集積化された複数出力を持つ電源回路に関し
、特に、電源電圧の上昇時に2つの出力を順序づけて立
上げるようにした複数出力電源回路に関する。
[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an integrated power supply circuit having multiple outputs, and particularly to a multiple output circuit in which two outputs are activated in sequence when the power supply voltage increases. Regarding power supply circuits.

〔従来の技術〕[Conventional technology]

第3図は、従来例の集積化された複数出力電源回路の回
路図、第4図は第3図の電源電圧と出力端電圧V、、v
2の関係を負荷が軽い場合および重い場合に示す特性図
である。
FIG. 3 is a circuit diagram of a conventional integrated multiple output power supply circuit, and FIG. 4 shows the power supply voltage and output terminal voltages V, v, in FIG.
FIG. 2 is a characteristic diagram showing the relationship of No. 2 when the load is light and when the load is heavy.

この複数出力電源回路は、出力電圧V、、V2の2つの
電源回路を持っている。第1の電源回路は、非反転入力
に基準電圧源11反転入力に出力端子2から抵抗3.4
と抵抗5で分割した帰還電圧を入力した第1の誤差増幅
器6と出力トランジスタのNPNトランジスタ7と電流
制限回路用の抵抗8.NPNトランジスタ9で構成され
、第2の電源回路は、非反転入力に基準電圧源11反転
入力に出力端子10から抵抗11と抵抗12で分割した
帰還電圧を入力した第2の誤差増幅器13と出力トラン
ジスタのNPN)ランジスタ14゜15と抵抗16とで
構成され、NPN)ランジスタ14,15はダーリント
ン接続され、コレクタを共通とし外付けPNPトランジ
スタ17のベース端子18に接続されている。
This multiple output power supply circuit has two power supply circuits with output voltages V, V2. The first power supply circuit connects a reference voltage source 11 to a non-inverting input and an output terminal 2 to a resistor 3.4 to an inverting input.
and a first error amplifier 6 to which the feedback voltage divided by the resistor 5 is input, an NPN transistor 7 as an output transistor, and a resistor 8 for the current limit circuit. The second power supply circuit is composed of an NPN transistor 9, and includes a reference voltage source 11 at its non-inverting input, a second error amplifier 13 which receives a feedback voltage divided by a resistor 11 and a resistor 12 from an output terminal 10 at its inverting input, and an output. The transistor is composed of NPN transistors 14 and 15 and a resistor 16, and the NPN transistors 14 and 15 are connected in Darlington and have a common collector connected to the base terminal 18 of an external PNP transistor 17.

さらに、圧力端子2と出力端子10を順序づけて立上げ
るために、反転入力に基準電圧源1.非反転入力に出力
端子2から抵抗3と抵抗4.5で分割した帰還電圧を入
力した第1の比較器19と、この比較器19の出力にエ
ミッタを接地したNPN トランジスタ20aベースを
接続し、コレクタは基準電圧源1から抵抗22を通しエ
ミッタ接地のNPN)ランジスタ24,25のベースと
エミッタ接地のNPN l−ランジスタ26のコレクタ
に接続した交点に接続し、NPNトランジスタ24のコ
レクタとNPNトランジスタ26のベースは、基準電圧
源1より抵抗21とダイオード接続されたNPN)ラン
ジスタ23を通しバイアスされ、NPN)−ランジスタ
25のコレクタを第2の誤差増幅器の出力に接続した第
1の電源回路を先に動作させる回路と、電源端子27の
電圧が上昇した後、出力端子2.10をショート状態と
するためのエミッタを出力端子10.ベースをベース端
子30.コレクタを出力端子2とした外付けPNP )
−ランジスタ29と、これを駆動するための出力端子1
0より抵抗31を通し、ベースに接続されたエミッタ接
地のNPN)ランジスタ32と電流制限用の抵抗33と
により構成されている。
Furthermore, in order to start up the pressure terminal 2 and the output terminal 10 in sequence, the reference voltage source 1. A first comparator 19 inputs a feedback voltage divided by a resistor 3 and a resistor 4.5 from the output terminal 2 to its non-inverting input, and the base of an NPN transistor 20a whose emitter is grounded is connected to the output of this comparator 19. The collector is connected from the reference voltage source 1 through a resistor 22 to the intersection between the bases of the emitter-grounded NPN transistors 24 and 25 and the collector of the emitter-grounded NPN l-transistor 26. The base of is biased from the reference voltage source 1 through a resistor 21 and a diode-connected NPN transistor 23, and the first power supply circuit is connected to the first power supply circuit, in which the collector of the NPN transistor 25 is connected to the output of the second error amplifier. After the voltage at the power supply terminal 27 increases, the emitter for shorting the output terminal 2.10 is connected to the output terminal 10.1. Connect the base to the base terminal 30. External PNP with collector as output terminal 2)
- transistor 29 and output terminal 1 for driving it
0 through a resistor 31, the base is connected to a grounded emitter NPN (NPN) transistor 32, and a current limiting resistor 33.

次に、この複数出力電源回路の動作を説明する6 出力端子2の電圧は、通常の定電圧回路と同様に基準電
圧源1と出力端子2の電圧を抵抗34と抵抗5で分割し
た電圧とを誤差増幅器6により比較し、一定出力とし、
また出力端子10の電圧も同様に一定出力となっている
。又、第1の電源回路を先に 動作させる回路は、NP
Nトランジスタ26.24でラッチ回路を構成し、電源
電圧上昇時にだけNPN)ランジスタ25が動作し、第
2の誤差増幅器の出力をロウレベルとして第2の電源回
路の動作を止め、出力端10をロウとしている。
Next, the operation of this multiple output power supply circuit will be explained.6 The voltage at the output terminal 2 is the voltage obtained by dividing the voltage at the reference voltage source 1 and the output terminal 2 by the resistor 34 and the resistor 5, as in a normal constant voltage circuit. are compared by the error amplifier 6 and set as a constant output,
Similarly, the voltage at the output terminal 10 is a constant output. Also, the circuit that operates the first power supply circuit first is the NP
NPN transistors 26 and 24 constitute a latch circuit, and the NPN transistor 25 operates only when the power supply voltage rises, sets the output of the second error amplifier to low level, stops the operation of the second power supply circuit, and lowers the output terminal 10 to low level. It is said that

第4図<a)のA区間のように電源電圧印加時、出力端
子2の抵抗分割の電圧は基準電圧1より低く第1の比較
器の出力はロウ、NPN)ランジスタ20も○FFのま
まで、NPN)ランジスタ25.24がNPNトランジ
スタ26より先にONとなり第2の誤差増幅回路の出力
をロウとし、出力端子10はロウとなり、かつ抵抗31
によりNPN)ランジスタ32はバイアスされないため
、外付けPNP)ランジスタ17もオフとした状態で、
第1の電源回路だけ動作をしている。
When the power supply voltage is applied as shown in section A in Figure 4<a), the voltage of the resistor divider of the output terminal 2 is lower than the reference voltage 1 and the output of the first comparator is low, and the NPN transistor 20 also remains FF. Then, the NPN) transistors 25 and 24 turn on before the NPN transistor 26, and the output of the second error amplifier circuit becomes low, the output terminal 10 becomes low, and the resistor 31
Since the NPN) transistor 32 is not biased, with the external PNP) transistor 17 also turned off,
Only the first power supply circuit is operating.

次に、第4図(a>のB区間のように電源電圧28が、
充分上昇し、出力端子2の抵抗分割した電圧が基準電圧
源1を超えると、第1の比較器の出力はハイに反転し、
NPN)ランジスタ20がオンとなり、NPN)ランジ
スタ25,24をオフとし、NPNトランジスタ26を
オンとすることによりラッチがかかり、電源電圧が下降
し、基準電圧源1の電圧が(1,4程度以下に)低くな
るまでNPN)ランジスタ26はON状態で、ラッチ状
態を保持し続ける。この時、NPN)ランジスタ25が
オフすると、第2の電源回路が正常動作となり、出力端
子10を一定電圧とし、抵抗31よりNPN )−ラン
ジスタ32をオンとして飽和させ、抵抗33で制限され
る電流を引き、外付けPNP)−ランジスタ29をオン
として飽和させ出力端子2の電圧を出力端子10の電圧
より飽和電圧だけ低い電圧まで上昇させ、出力端子2゜
’10のV、、V2の電圧を等しくします。
Next, as shown in section B of FIG. 4 (a>), the power supply voltage 28 is
When the voltage rises sufficiently and the resistor-divided voltage at output terminal 2 exceeds reference voltage source 1, the output of the first comparator is inverted to high.
NPN) transistor 20 is turned on, NPN) transistors 25 and 24 are turned off, and NPN transistor 26 is turned on, thereby latching the power supply voltage and lowering the voltage of reference voltage source 1 to about (1.4 or less). NPN) The transistor 26 remains in the ON state and continues to hold the latched state until the NPN) becomes low. At this time, when the NPN) transistor 25 is turned off, the second power supply circuit operates normally, and the output terminal 10 is set to a constant voltage, and the resistor 31 turns on the NPN) transistor 32 to saturate it, and the current is limited by the resistor 33. , the external PNP) - transistor 29 is turned on and saturated, and the voltage at the output terminal 2 is increased to a voltage lower than the voltage at the output terminal 10 by the saturation voltage, and the voltage at the output terminal 2゜'10 is Make them equal.

この時、C区間のように出力端子10が異常となり過電
流が流れると、過電流を抵抗34により検出し、保護回
路35により誤差増幅器13の出力をロウとし、出力端
子10の■2が下降したとき、第1の電源回路の出力端
子2の電位も下降するが、抵抗3.4と抵抗5による分
割比で決まる出力電圧を保持し、第1.第2の電源回路
は独立に動作する。
At this time, when the output terminal 10 becomes abnormal and an overcurrent flows as in section C, the overcurrent is detected by the resistor 34, the output of the error amplifier 13 is set to low by the protection circuit 35, and the voltage 2 of the output terminal 10 falls. At this time, the potential of the output terminal 2 of the first power supply circuit also decreases, but the output voltage determined by the division ratio of the resistor 3.4 and the resistor 5 is maintained. The second power supply circuit operates independently.

D区間のように電源電圧が下がって電圧v2に近づくと
、第2の電源回路は負帰還がかからなくなり、出力端子
10のV2は電源電圧からPNPトランジスタ17の飽
和電圧分子がった電圧となり、■1はv2からPNPト
ランジスタ29の飽和電圧分子がった電圧で加工する。
When the power supply voltage decreases and approaches voltage v2 as in section D, negative feedback is no longer applied to the second power supply circuit, and V2 at the output terminal 10 becomes a voltage that is the numerator of the saturation voltage of the PNP transistor 17 from the power supply voltage. , (1) is processed using a voltage that is the numerator of the saturation voltage of the PNP transistor 29 from v2.

この様に、この電源回路は、電源投入時に、この出力端
子2,10のV 1 、 V 2を順番に出力できるの
で、マイコン・メモリ等を使ったシステムの電源回路と
して電源投入時の誤動作を防止することができる。
In this way, this power supply circuit can sequentially output V 1 and V 2 from the output terminals 2 and 10 when the power is turned on, so it can be used as a power supply circuit for a system using a microcomputer, memory, etc. to prevent malfunctions when the power is turned on. It can be prevented.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の複数出力電源回路は、電源電圧が上昇す
る時に第1の電源回路を先に動作させる回路を内蔵して
いるため、第1の電源回路が動作し、出力端子2の■1
が規定の電圧まで上昇したとき、第2の電源回路が動作
するようになっているので、第41g(b)のように、
出力端子2が過負荷により規定の電圧まで上昇しないと
き、電源電圧が充分立上がっても第2の電源回路は動作
せず、出力端子10の■2はロウ状態のままとなり、出
力端子10に接続した負荷となる回路に電圧を供給でき
なくなるという欠点がある。
The conventional multiple output power supply circuit described above has a built-in circuit that operates the first power supply circuit first when the power supply voltage rises, so the first power supply circuit operates and
Since the second power supply circuit is designed to operate when the voltage rises to a specified voltage, as in No. 41g(b),
When the output terminal 2 does not rise to the specified voltage due to overload, the second power supply circuit does not operate even if the power supply voltage rises sufficiently, and the output terminal 10 (2) remains in the low state, and the output terminal 10 The disadvantage is that voltage cannot be supplied to the connected load circuit.

本発明の目的は、このような欠点を除き、一方の電源が
規定値まで上昇しない時にも他方の電源に電圧を出力で
きるようにした複数出力電源回路を提供することにある
SUMMARY OF THE INVENTION An object of the present invention is to eliminate such drawbacks and provide a multi-output power supply circuit that can output voltage to the other power supply even when one power supply does not rise to a specified value.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の複数出力電源回路の構成は、第1の出力電圧を
第1の帰還回路により抵抗分割した電圧と基準電圧との
差を増幅して第1の出力トランジスタを駆動することに
よりその出力電圧を得る第1の電源回路と、この第1の
電源回路と同様の構成で並列に設けられ第2の出力電圧
を第2の出力トランジスタを駆動して得る第2の電源回
路と、前記第1の帰還回路からの電圧と前記基準電圧と
を比較器により比較し、その出力をラッチ回路を介して
前記第2の出力トランジスタのベースに供給することに
より1に源電圧上昇時に前記第1の電源回路を先に動作
させる電源制御回路とを備えた複数出力電源回路におい
て、前記第1の電源回路の過電流を検出する第1のトラ
ンジスタと、この第1のトランジスタの出力により駆動
されこの第1のトランジスタと逆導電型の第2.第3の
トランジスタからなるカレントミラー回路とを設け、こ
のカレントミラー回路の出力を前記比較器の出力端に接
続して前記第2の電源回路を前記第1の電源回路と独立
に駆動できるようにしたことを特徴とする。
The configuration of the multiple output power supply circuit of the present invention is such that the difference between the voltage obtained by dividing the first output voltage by the first feedback circuit and the reference voltage is amplified and the output voltage is increased by driving the first output transistor. a first power supply circuit that obtains a second output voltage by driving a second output transistor; The voltage from the feedback circuit and the reference voltage are compared by a comparator, and the output thereof is supplied to the base of the second output transistor through a latch circuit. A multi-output power supply circuit including a power supply control circuit that operates the circuit first, a first transistor that detects an overcurrent in the first power supply circuit, and a first transistor that is driven by the output of the first transistor. A second transistor of opposite conductivity type. and a current mirror circuit consisting of a third transistor, and the output of the current mirror circuit is connected to the output terminal of the comparator so that the second power supply circuit can be driven independently of the first power supply circuit. It is characterized by what it did.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図は本発明の一実施例の集積化された複数出力電源
回路の回路図、第2図は第1図の電源電圧と出力電圧V
、、V2との関係を示す特性図で、第2図(a)は出力
端子2に接続された負荷が軽い場合、第2図(b)は負
荷が重い場合の図である。
Fig. 1 is a circuit diagram of an integrated multiple output power supply circuit according to an embodiment of the present invention, and Fig. 2 shows the power supply voltage and output voltage V of Fig. 1.
,,V2, and FIG. 2(a) is a diagram when the load connected to the output terminal 2 is light, and FIG. 2(b) is a diagram when the load is heavy.

この電源回路は、従来例の回路に対して、NPNトラン
ジスタ9のベース・エミッタに各々ベース・エミッタを
接続したNPN)ランジスタ37と、このNPN)ラン
ジスタ37のコレクタ側をカレントミラーの入力側であ
るPNPトランジスタ38のコレクタ・ベースとPNP
 )ランジスタ39のベースとに接続し、各エミッタは
電源端子27に接続したPNPタイプのカレントミラー
の出力を第1.第2の電源回路の順序づけを決める第1
の比較器の出力に接続した回路を付備している。
This power supply circuit differs from the conventional circuit in that it includes an NPN transistor 37 whose base and emitter are connected to the base and emitter of an NPN transistor 9, and the collector side of this NPN transistor 37 is the input side of a current mirror. Collector-base of PNP transistor 38 and PNP
) to the base of the transistor 39, and each emitter connects the output of a PNP type current mirror connected to the power supply terminal 27 to the first . The first circuit determines the ordering of the second power supply circuit.
It is equipped with a circuit connected to the output of the comparator.

この回路の動作は、従来例と同様であるが、電源投入時
に第2図(b)のA区部のように出力端子2が異常とな
り過電流が流れたり、マイコン等により瞬間大電流を引
かれて電圧vlが規定の電圧まで上昇しないとき、第2
の電源回路の過電流をNPNトランジスタ37で検出し
、第1の比較器19の出力をハイとし、NPN)−ラン
ジスタ20がオンとなり、NPNトランジスタ25゜2
4がオフし、NPNトランジスタ26がオンしてラッチ
状態となり、第2の誤差増幅器13の出力がハイとなり
、NPN)ランジスタ14,15がオンし出力端10の
■2が立上がる。なお、その後の動作は従来例と同じで
ある。
The operation of this circuit is the same as that of the conventional example, but when the power is turned on, the output terminal 2 becomes abnormal and an overcurrent flows, as shown in section A in Figure 2 (b), or a microcomputer or the like causes a momentary large current to flow. When the voltage vl does not rise to the specified voltage due to
The NPN transistor 37 detects an overcurrent in the power supply circuit of
4 is turned off, the NPN transistor 26 is turned on and becomes a latch state, the output of the second error amplifier 13 becomes high, the NPN transistors 14 and 15 are turned on, and the voltage 2 of the output terminal 10 rises. Note that the subsequent operation is the same as in the conventional example.

〔発明の効果〕〔Effect of the invention〕

以上、説明したように本発明は従来の複数出力電源回路
に、第1の電源回路の過負荷を検出するNPN)ランジ
スタとカレントミラー回路のPNPトランジスタを付加
することにより、電源投入時に出力端子が異常となり過
電流が流れたり、マイコン等により瞬間大電流が流れ、
V6が第1の電源が規定の電圧まで上昇しない場合でも
、第2の電源回路を動作させ、出力電圧を上昇させるこ
とができ、後続の回路に電圧を供給できる効果がある。
As explained above, the present invention adds an NPN (NPN) transistor for detecting overload of the first power supply circuit and a PNP transistor of the current mirror circuit to the conventional multiple output power supply circuit, so that when the power is turned on, the output terminal is If an abnormality occurs and an overcurrent flows, or a microcontroller causes a momentary large current to flow,
Even if V6 does not rise to the specified voltage of the first power supply, the second power supply circuit can be operated to increase the output voltage, which has the effect of supplying voltage to subsequent circuits.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例の複数出力電源回路の回路図
、第2図(a>、(b)は第1図の電源電圧と出力端子
V、、V2との関係を負荷の軽い場合と重い場合で示す
特性図、第3図は従来の集積化された複数出力電源回路
の一例の回路図、第4図(a)、(b)は第3図の電源
電圧と出力端電圧V、、V2との関係を負荷の軽い場合
と重い場合とで示す特性図である。 1・・・基準電圧源、2.10・・・電源出力端子(V
+ 、V2 >、5〜5,8.11,12.16゜21
.22,31,33,34.40・・・抵抗、6.13
・・・誤差増幅器、7,9,14,15゜20.24〜
26,32.37・・・NPNトランジスタ、17.2
3,29,38.39・・・PNPトランジスタ、18
.30・・・ベース端子、19・・・比較器、27・・
・電源端子、28・・・電源電圧源、35・・・過電流
保護回路、36・・・接地端子。
Fig. 1 is a circuit diagram of a multiple output power supply circuit according to an embodiment of the present invention, and Fig. 2 (a>, (b) shows the relationship between the power supply voltage and the output terminals V, V2 in Fig. Figure 3 is a circuit diagram of an example of a conventional integrated multiple output power supply circuit, Figures 4 (a) and (b) are the power supply voltage and output terminal voltage in Figure 3. It is a characteristic diagram showing the relationship with V,, V2 when the load is light and when the load is heavy. 1... Reference voltage source, 2.10... Power supply output terminal (V
+, V2>, 5~5, 8.11, 12.16°21
.. 22, 31, 33, 34.40...Resistance, 6.13
...Error amplifier, 7, 9, 14, 15°20.24~
26, 32.37...NPN transistor, 17.2
3,29,38.39...PNP transistor, 18
.. 30... Base terminal, 19... Comparator, 27...
- Power supply terminal, 28...Power supply voltage source, 35...Overcurrent protection circuit, 36...Grounding terminal.

Claims (1)

【特許請求の範囲】[Claims] 第1の出力電圧を第1の帰還回路により抵抗分割した電
圧と基準電圧との差を増幅して第1の出力トランジスタ
を駆動することによりその出力電圧を得る第1の電源回
路と、この第1の電源回路と同様の構成で並列に設けら
れ第2の出力電圧を第2の出力トランジスタを駆動して
得る第2の電源回路と、前記第1の帰還回路からの電圧
と前記基準電圧とを比較器により比較し、その出力をラ
ッチ回路を介して前記第2の出力トランジスタのベース
に供給することにより電源電圧上昇時に前記第1の電源
回路を先に動作させる電源制御回路とを備えた複数出力
電源回路において、前記第1の電源回路の過電流を検出
する第1のトランジスタと、この第1のトランジスタの
出力により駆動されこの第1のトランジスタと逆導電型
の第2、第3のトランジスタからなるカレントミラー回
路とを設け、このカレントミラー回路の出力を前記比較
器の出力端に接続して前記第2の電源回路を前記第1の
電源回路と独立に駆動できるようにしたことを特徴とす
る複数出力電源回路。
a first power supply circuit that obtains the output voltage by amplifying the difference between a voltage obtained by dividing the first output voltage by a first feedback circuit and a reference voltage and driving the first output transistor; a second power supply circuit which is provided in parallel with the same configuration as the first power supply circuit and obtains a second output voltage by driving a second output transistor; and a voltage from the first feedback circuit and the reference voltage. and a power supply control circuit that operates the first power supply circuit first when the power supply voltage rises by comparing the output with a comparator and supplying the output to the base of the second output transistor through a latch circuit. In the multi-output power supply circuit, a first transistor detects an overcurrent in the first power supply circuit, and second and third transistors are driven by the output of the first transistor and have a conductivity type opposite to that of the first transistor. A current mirror circuit consisting of a transistor is provided, and the output of the current mirror circuit is connected to the output terminal of the comparator so that the second power supply circuit can be driven independently of the first power supply circuit. Features multiple output power supply circuit.
JP28903390A 1990-10-26 1990-10-26 Multiple output power supply circuit Expired - Fee Related JP2604497B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP28903390A JP2604497B2 (en) 1990-10-26 1990-10-26 Multiple output power supply circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP28903390A JP2604497B2 (en) 1990-10-26 1990-10-26 Multiple output power supply circuit

Publications (2)

Publication Number Publication Date
JPH04162112A true JPH04162112A (en) 1992-06-05
JP2604497B2 JP2604497B2 (en) 1997-04-30

Family

ID=17737960

Family Applications (1)

Application Number Title Priority Date Filing Date
JP28903390A Expired - Fee Related JP2604497B2 (en) 1990-10-26 1990-10-26 Multiple output power supply circuit

Country Status (1)

Country Link
JP (1) JP2604497B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007011709A (en) * 2005-06-30 2007-01-18 Ricoh Co Ltd System power unit and its operation control method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007011709A (en) * 2005-06-30 2007-01-18 Ricoh Co Ltd System power unit and its operation control method

Also Published As

Publication number Publication date
JP2604497B2 (en) 1997-04-30

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