JPH04160879A - Communication method for video signal and synchronous detection circuit used therefor - Google Patents

Abstract

PURPOSE:To simplify the circuit constitution by detecting a phase of an operating timing of an image pickup device with respect to a synchronizing signal of a communication line and stopping the output of a 2nd video signal onto the communication line when the phase is a prescribed range or over. CONSTITUTION:A 1st video signal and a 2nd video signal are synthesized by a video signal processing unit 20 by replacing the 2nd video signal synchronously with a synchronizing signal superimposed on a signal of a communication line into part of the 1st video signal, and a 3rd video signal to display 1st and 2nd patterns on a screen is obtained. In this case, since a 2nd synchronizing signal is not outputted on the communication line 30 till the 2nd video signal is synchronized with a synchronizing signal on the communication line 30, the synchronizing signal on the communication line 30 is protected and malfunction is prevented. Thus, a so-called picture-in-picture system in which plural video images are displayed on one screen is realized with simple circuit constitution.

Description

Detailed Description of the Invention (a) Field of Industrial Application The present invention relates to a video signal communication method for displaying multiple playback screens on one screen by superimposing multiple video signals, and a communication method for synchronizing signals and circuit operations. The present invention relates to a synchronous detection circuit that determines synchronization.

(b) Prior Art FIG. 5 is a block diagram showing the configuration of a video signal processing circuit that superimposes a video signal for a child screen on a video signal for a main screen.

The video signal XN of the main screen is obtained, for example, from a television camera operating according to a predetermined synchronization signal, and is constructed by superimposing a video component on the synchronization signal. and,
The television camera (1) that obtains the video signal Y(, , ) of the child screen operates according to a synchronization signal created inside the television camera (1), and outputs the video signal Y(11) including the synchronization signal.

A TV camera that operates at its own timing in this way (
The video signal Y(1) output from the video signal X(
, ), the scanning timings do not match, and they cannot be superimposed as they are. Therefore, the screen control circuit (2) stores part of the video signal Y (11 in the field memory (3), and By reading the video signal X (11) from the field memory (3) according to the synchronization signal of the video signal Y., each scanning timing of the video signal χ (11
configured to match. Here, the video signal
The synchronization signal of N) is separated from the video signal X (11) in a synchronization separation circuit (4) and given to the screen control circuit (2).

Then, the video signals XN) and YfN are combined by a combining circuit (5) that selects either the video signal X(1) or the video signal Y(1) according to the selection pulse SP, and the video signal Z(
tl is obtained.

For example, as shown in FIG.
When superimposing a child screen of size n on the main screen, the selection pulse sp is set so as to replace the video signal X(,) with the video signal Y(1) during a period of 17n of vertical and horizontal scanning periods. . That is, in the vertical scanning period,
As shown in a), the selection pulse SP becomes L level during a period (V/n) of 1/n of the vertical scanning period (IV), and the synthesis circuit (5) is switched to the video signal Y(, ) side. Furthermore, in the horizontal scanning period, the selection pulse SP becomes L level during a period (H/n) of 1/n of the horizontal scanning period (IH), as shown in FIG. 7(b). By the way, the video signal ytt+ whose information amount in the vertical and horizontal directions is 1/n of the video signal This can be obtained by configuring the television camera (1) as follows.

According to the above configuration, a part of the parent screen can be replaced with a child screen, and two screens can be displayed simultaneously on one monitor.

(c) Problems to be Solved by the Invention However, in the above configuration, the video signal
Since it is necessary to store (,) in the field memory (3), an A/D converter is used to convert the video signal Y(11) into a digital value, and the digital value is converted back into the video signal Y(11). In general, A/D converters and D/A converters that process video signals require special circuit configurations because they require high-speed operation.
This may lead to higher costs.

Furthermore, since the overall circuit scale becomes large, it is difficult to incorporate it into a small television camera, and a separate device for processing the video signal is required, making the imaging system expensive.

(d) Means for Solving the Problems The present invention has been made to solve the above-mentioned problems, and the first feature is that a video signal processing device that receives a first video signal and a second video signal processing device that receives a first video signal; An imaging device that obtains a video signal is connected via a communication line, and the video signal processing device separates a synchronization signal component from the first video signal and superimposes it on the communication line, and the imaging device The second video signal is obtained in synchronization with the communication line and superimposed on the communication line, and the video signal processing device selectively combines the first video signal and the second video signal to display the same screen. In a video signal communication method for obtaining a third video signal for displaying a plurality of playback screens, the phase of the operation timing of the imaging device with respect to the synchronization signal of the communication line is detected, and the phase is detected when the phase exceeds a predetermined range. Sometimes, the second video signal may be stopped from being output to the communication line.

The second feature is that the first horizontal synchronizing signal and the second horizontal synchronizing signal are synchronized in a phase-locked loop that obtains a second horizontal synchronizing signal with the same period based on the first horizontal synchronizing signal having a constant period. A synchronous detection circuit that determines synchronization with a horizontal synchronizing signal, wherein the first horizontal synchronizing signal and the second horizontal synchronizing signal are detected during a blanking period of a vertical synchronizing signal obtained by dividing the frequency of the second horizontal synchronizing signal. a gate circuit that passes each synchronization signal when the blanking period with the horizontal synchronization signal matches, and a gate circuit that is reset every blanking period of the vertical synchronization signal;
a counting circuit that counts the synchronization signal that has passed through the gate circuit; and at least a 2-bit register circuit that takes in the output of the counting circuit at a predetermined timing within the blanking period of the vertical synchronization signal, the register circuit The object of the present invention is to determine synchronization between the first horizontal synchronizing signal and the second horizontal synchronizing signal by matching data of each focus.

(E) Effect According to the video signal communication method of the present invention, the second video signal synchronized with the synchronization signal superimposed on the communication line is replaced with a part of the first video signal, so that the first video signal is The signal and the second video signal are combined, and the first and second video signals are displayed on one screen.
A third video signal displaying the screen is obtained. At this time, since the second synchronization signal is not output onto the communication line until the second video signal is synchronized with the synchronization signal on the first communication line, the synchronization signal on the communication line is protected and malfunctions are prevented.

Further, according to the synchronous detection circuit of the present invention, it is determined that the circuit operation is synchronized with the synchronization signal when synchronization in the vertical scanning period and synchronization in the horizontal scanning period is confirmed. Therefore, if the timing coincides by chance over a short period of time, it is not determined that the timing is synchronized, but synchronization is confirmed only when the timing completely coincides.

(f) Example An embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a video signal processing circuit that employs the video signal communication method of the present invention.

The first video signal X(,) is obtained, for example, from an imaging device such as a television camera, and includes a synchronization signal component and a video component. Further, this video signal X (11) is not limited to a television camera, and may be a reproduced signal from a video signal recording medium or a received signal from TV Jimin broadcasting.

The synchronization separation circuit (11) separates the synchronization signal components superimposed on the video signals X, j, &, and creates a composite signal in which the vertical synchronization component and the horizontal synchronization component are mixed. This combo signal is connected to the base of a transistor (13) via a resistor (12), and is passed from the collector side of this transistor (13) via a resistor (14) and further via a capacitor (15) to remove the DC component. and is sent out to the communication line (30).

On the other hand, the video signal input from one communication line (30) is
It is input to the synthesis circuit (16) together with the first video signal X(t), and is selectively synthesized according to the selection pulse SP.
A video signal 2 (0,
) is the same as that in FIG. 1, and is switched and controlled at a predetermined timing for compositing screens.

Selection pulse S for switching and controlling this synthesis circuit (16)
P is generated by a selection pulse generation circuit (I7) that operates in response to horizontal and vertical scanning timing, and is synchronized with the video signal X(1). That is, the selection pulse generation circuit (17) is a basic clock for creating the synchronization separation circuit (vertical synchronization signal VD from I++, horizontal scanning period timing pulse HT obtained from the PLL circuit (18), and water synchronization signal) ID. Based on GK, video signal X (1)
A selection pulse SP synchronized with horizontal and vertical synchronization components is created. Here, in order to prevent the selection pulse SP from being supplied to the synthesis circuit (16) before the operation of the selection pulse generation circuit (17) is synchronized with the video signal x(I), the PLL circuit (]8) is The selection pulse generation circuit (17) until it locks.
) is provided with a lock detection circuit (19).

As described above, the synchronization separation circuit (11), the synthesis circuit (16)
), a selection pulse generation circuit (17), and the like constitute a video signal processing circuit (lo) that synthesizes a plurality of video signals.

An imaging device (20) connected to this video signal processing circuit (10) via a communication line (30) has one communication line (3
It obtains a video signal Y(1) synchronized with the synchronization signal of 0), and is equipped with a television camera (21) that operates with external synchronization. This TV camera (21) has a communication line (30)
The video signal Y, ) synchronized with the synchronization signal is obtained by synchronizing the scanning timing of the image sensor of the television camera (21) with the synchronization signal. There is.

The synchronization separation circuit (22) detects the synchronization signal on the communication line (30), generates a trigger pulse TR having a horizontal scanning period, and supplies this trigger pulse TR to the PLL circuit (23). The PLL circuit (23) creates a timing signal FIT of the horizontal scanning period based on the trigger pulse TR,
It is supplied to the synchronization signal synthesis circuit (24). Further, the synchronization signal synthesis circuit (24) receives the timing signal HT and the trigger pulse TR of the vertical scanning period component to generate a vertical synchronization signal VD and a horizontal synchronization signal HD. That is, the synchronization signal synthesis circuit (24) divides the timing signal HT into a predetermined number, for example, 252 or 25 in the case of the NTSC system.
The vertical scan period is configured to be determined by counting by three.

Then, the vertical synchronization signal VD and the horizontal synchronization signal 4+HD are supplied to the television camera (21).
The video signal Y (.) output from the is output to the communication line (30) via the capacitor (25). This video signal Y., is synchronized with the synchronization signal on the communication line (30). , the synchronization signal is a time-division communication line (30)
It will be superimposed on

By the way, if the operation of the television camera (21) is not synchronized with the synchronization signal when the imaging device (20) starts up or for some other reason, if the video signal Y (1) is superimposed on the communication line (30), Cannot be distinguished from synchronous signal (
As a result, the PLL circuit (23) stops operating.
Gate circuit (2) that stops the output of the television camera (21)
6) are provided, and a horizontal synchronizing signal HD and a trigger pulse TR are provided.
The output of the television camera (2I) is configured to be stopped in accordance with the output of a synchronous detection circuit (27) that detects synchronization with the television camera (2I). Therefore, the synchronization signal component will not be mixed with the video signal component due to the M tatami of the video signal Y (1),
Malfunction of the PLL circuit (23) is prevented.

As shown in Figure 1, if an imaging device (20) is connected to a video signal processing circuit (+10), one communication line (30)
As a result, the video signal X (video signal YB synchronized with 41) can be given to the video signal processing circuit (10), and this video signal
), a video signal Z (11) is obtained that displays the playback screen corresponding to the video signal X (1,) and the playback screen corresponding to the video signal YH on the same screen. The communication line for video signals can be simplified.

FIG. 2 is a block diagram showing the configuration of the synchronous detection circuit (19L (27)), and FIG. 3 is a timing diagram showing its operation.

The synchronous detection circuits (19) and (27) include, for example, a 3-bit counter (4I), a 2-bit shift register (4I), and a 2-bit shift register (4I).
2), OR game) f43) and NOR gate f44)
It detects that the PLL circuits (18) and (Z3) are locked by synchronizing the horizontal synchronizing signal HD and the trigger pulse TR. That is, the trigger pulse TR is input to the OR game (f42) together with the vertical synchronizing signal VD and the horizontal synchronizing signal HD, and each timing of the trigger pulse TR coincides with the horizontal synchronizing signal H within the blanking period of the vertical synchronizing signal VD.
○R game when it matches the blanking period of D) (
43) passes the trigger pulse TR' and the counter (
41). The counter (41) is 3
It is composed of flip-flops in stages and counts trigger pulses TR' after being reset according to the vertical synchronizing signal VD.If four or more trigger pulses TR' are input within the blanking period of the vertical synchronizing signal VD, the trigger pulse TR' is counted.
The output of the flip-flop in the second stage is inverted. The shift register (42) is composed of a two-stage flip-flop,
The output of the third stage flip-flop of the counter (41) is taken in at a timing according to the vertical enable signal VEN. Here, the vertical enable signal YEN is included in the composite signal of the television format, and is included in the blanking period of the vertical synchronization signal VD. specified period, e.g. NTSC
In the case of the blanking period 3 as shown in Figure 3,
It becomes L level during the period from H to 6H (IH is one vertical scanning period). Therefore, in the shift register (42), the trigger pulse TR' of 4 or more pulses is detected by the counter (4I
), the H level is taken into the first stage of the shift register (42).

Then, during the next blanking period of the vertical synchronization signal VD, the data of the first stage is transferred to the second stage, and the output of the third stage of the flip-flop of the counter (41) is newly transferred to the first stage. It is captured. The NOR gate (44) is configured to receive the data from the first and second stages of the shift register (42) and generate the detection signal RK, and thus generates the vertical synchronization signal VD twice in succession. When four or more trigger pulses TR' are input to the counter (41) during the blanking period, the detection signal RK becomes H level.

According to such synchronous detection circuits (19) and (27),
P when the horizontal synchronization signal HD and the trigger pulse TR are continuously synchronized within the blanking period of the vertical synchronization signal VD.
It can be detected that the LL circuits (18) and (23) are locked. Therefore, it is necessary to stop the operation of the selection pulse generation circuit (17) based on the detection signal RK and to stop the operation of the selection pulse generation circuit (17) based on the detection signal RK.
By stopping the superimposition of the signal on the communication line (30), it is possible to prevent malfunctions of the combining circuit (16) and the PLL circuit (23).

FIG. 4 is a block diagram showing the configuration of the 1 selection pulse generation circuit (17).

This selection pulse generation circuit (17) includes two sets of counters (51), (52) and decoders (53), (54), respectively.
It operates in response to a vertical synchronizing signal VD, a horizontal synchronizing signal HD, and a basic clock GK. A counter (51) operating in the vertical scanning period is reset by the vertical synchronizing signal VD, counts the horizontal synchronizing signal HD, and applies pressure in the horizontal scanning period to the decoder (53). This decoder (53
) decodes the output of the counter (51) and provides a timing signal of the vertical scanning period to the pulse synthesis circuit (55), which creates a selection pulse SPv of the vertical scanning component. On the other hand, a counter (52) operating in the horizontal scanning period is reset by the horizontal synchronizing signal HD, counts the basic clock, and provides an output of the basic tarok GK period to the decoder (54). The decoder (54) similarly decodes the output of the counter (52) and supplies a timing signal of the horizontal scanning period to the pulse synthesis circuit (56), which in turn generates the selection pulse SPM of the horizontal scanning component. create. Then, the OR gate (57) synthesizes the selection pulse SPv and the selection pulse SPH and supplies it to the synthesis circuit (16) as the selection pulse SP.

Although this embodiment exemplifies the case where one imaging device is connected to the video signal processing circuit, it is also possible to connect a plurality of imaging devices to the video signal processing circuit. Even in such a case, since each imaging device is connected to the video signal processing circuit through one communication line, the communication line does not become complicated.

(G) Effects of the Invention According to the present invention, a so-called picture-in-picture system that displays multiple images on one screen can be realized with an extremely simple circuit configuration, and the synchronization signal on the communication line is protected. Therefore, the operation of the PLL circuit is performed reliably. Therefore, it is effective for monitoring systems that need to process multiple images simultaneously.

Furthermore, since the video from the surveillance camera can be superimposed on the playback screen of a television broadcast or the like, it becomes possible to use a general television screen as a playback monitor of the doorbell camera.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a video signal processing circuit adopting the video signal communication method of the present invention, FIG. 2 is a block diagram of a synchronous detection circuit of the present invention, and FIG. 3 is a timing diagram showing the operation of FIG. 2. Fig. 4 is a block diagram of a selection pulse generation circuit, a circuit diagram of a conventional video signal processing circuit, Fig. 5 is a schematic diagram of a playback screen, Fig. 6 is a diagram showing the operation of Fig. 4, Fig. 7 fa) and f
b) is a timing diagram showing the operation of the circuit shown in FIG. 5; (1) (211...TV camera, (2)...
・Screen control circuit, (3)...Field memory, (
4) (II) (221... synchronous separation circuit, (5
1 (16)...Synthesis circuit, (101...Video signal processing circuit, (17)...Selection pulse creation circuit, +
18) (23)...PLL circuit, [9) f2
7)... Synchronous detection circuit, (24)... Synchronous signal synthesis circuit, (26)... Gate circuit. Figure 3 EN Figure 5 Figure 6 Figure 7 (a) (b) Pl

Claims (4)

[Claims] (1) A video signal processing device that receives a first video signal and a second
An imaging device that obtains a video signal is connected via a communication line, and the video signal processing device separates a synchronization signal component from the first video signal and superimposes it on the communication line, and the imaging device The second video signal is obtained in synchronization with the communication line and superimposed on the communication line, and the video signal processing device selectively combines the first video signal and the second video signal to display the same screen. The third screen that displays multiple playback screens
In the video signal communication method for obtaining the video signal, a phase difference in the operation timing of the imaging device with respect to the synchronization signal of the communication line is detected, and when the phase difference is beyond a predetermined range, the second video signal is detected. A video signal communication method characterized by stopping output of the signal to a communication line. (2) A selection signal synchronized with the first video signal is created based on the synchronization signal, and the first or second video signal is selectively combined in accordance with the selection signal. The video signal communication method according to item 1. (3) A phase difference between the selection signal and the synchronization signal is detected, and output of the selection signal to the synthesis circuit is stopped until the phase difference falls within a predetermined range. The video signal communication method described. (4) Synchronizing the first horizontal synchronizing signal and the second horizontal synchronizing signal in a phase-locked loop that obtains a second horizontal synchronizing signal with the same period based on the first horizontal synchronizing signal having a constant period. A synchronous detection circuit that determines blanking of the first horizontal synchronization signal and the second horizontal synchronization signal during a blanking period of the vertical synchronization signal obtained by dividing the frequency of the second horizontal synchronization signal. a gate circuit that passes each synchronization signal when the periods match; a counting circuit that is reset every blanking period of the vertical synchronization signal and counts the synchronization signals that have passed through the gate circuit; and a blanking circuit of the vertical synchronization signal. at least a 2-bit register circuit that takes in the output of the counting circuit at a predetermined timing within a period, and the first horizontal synchronization signal and the second horizontal synchronization signal are generated by matching the data of each bit of the register circuit. A synchronous detection circuit characterized by determining synchronization with a signal.