JPH04158442A - Instruction decoder - Google Patents

Abstract

PURPOSE:To assign many instruction codes with use of a small number of instruction codes by changing the instruction decoding method in accordance with the length of a write control signal. CONSTITUTION:An input signal, the inverse of WR is held in a shift register 11 for a period of time synchronous with a clock signal CLK. A selector 13 selects a decoder 14 in response to the width of the unit signal, the inverse of WR among the decoders 14 - 16 and decodes the input instructions D0 - D7 based on the active time information on the signal, the inverse of WR held in the register 11. Then each part of a microcomputer is controlled with the instructions D0 - D7 decoded by the decoder 14. Thus many instruction codes are assigned with a small number of instruction codes.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an instruction decoder, and particularly to an instruction decoder used in a microcomputer having a plurality of instruction word lengths.

[Conventional technology]

A conventional instruction decoder for a microcomputer having a plurality of instruction lengths includes an instruction register 31 and a decoder 34, as shown in the block diagram of FIG. 7(a) and (b) are timing diagrams showing the conventional 1-byte instruction operation, and FIG. 8(a) and (
9b) is a timing diagram showing the conventional 2-byte instruction operation, and FIGS. 9(a) and 9(b) are timing diagrams showing the conventional 3-byte instruction operation.

The instruction decoder shown in FIG. 6 is a circuit that inputs and processes instructions in units of 1 byte (8 bits).

First, the operation of processing a 1-byte instruction will be explained. 8-bit instruction Do~ input from the instruction input terminal
As shown in the timing diagrams of FIGS. 7(a) and 7(b), D7 indicates that the write control signal WR (hereinafter referred to as the WR double signal; the upper line indicates that it is a low level signal and is active) is in the active state. The instruction is input to the instruction register 32, and the instruction is held at the same time as the WR multiplication signal is released. This held instruction is sent to the decoder 34 and decoded. The decoded signals are sent to each part of the microcomputer and used for control purposes.

Next, the operation of processing a 2-byte instruction will be explained.

1st byte command Do~D input from command input terminal
7 is input to the instruction register 32 in the WR multiplication signal active state, as shown in the timing diagrams of FIGS. 8(a) and 8(b), and the instruction is held at the same time as the WR multiplication signal is released. The retained first byte instruction is input to the decoder 34 and decoded.

The decoded signal is sent to each part of the microcomputer and used for controlling the first byte.

Next, the second byte instruction is WR
It is held in the instruction register 32 at the same time as the double signal is released. The second byte instruction held is input to the decoder 34 and decoded. The decoded command is sent to each part of the microcomputer and used for controlling the second byte.

Next, the operation of processing the third byte instruction will be explained.

The first byte of the command input from the command input terminal, ~D
As shown in the timing diagrams of FIGS. 9(a) and 9(b), 7 is input to the command register 32 in the WR double signal active state, and is held in the command register 32 at the same time as the thin layer signal is released. The retained first byte instruction is input to the decoder 34 and decoded. The decoded instructions are sent to each part of the microcomputer and used for controlling the first byte.

Next, the second byte instruction is W1 in the same way as the first byte.
input to the command register 32 in the active state of the signal;
It is held in the instruction register 32 at the same time as the WR multiplication signal is released. The second byte instruction held is input to the decoder 34 and decoded. It is decoded and used as the second byte for control.

Next, the third byte instruction is also the same as the first byte and the second byte.
As in the case of the byte, the WR double signal is input to the instruction register 32 in the active state, and is held in the instruction register 32 at the same time as the counterfeit signal is released. The third byte instruction held is input to the decoder 34 and decoded. The decoded signal is sent to each part of the microcomputer and used for controlling the third byte.

As a conventional example, processing of 1-byte to 3-byte instructions has been described above, but devices having 4-byte or more instructions (fN, such as NEC's μPD70008) are also often used.

[Problem to be solved by the invention]

The above-described conventional instruction decoder has the disadvantage that the processing for controlling the write control signal becomes complicated because it is necessary to repeatedly activate and deactivate the write control signal every time a command is input.

[Means to solve the problem]

The instruction decoder of the present invention is an instruction decoder for a microcomputer that processes multiple instruction word lengths, and includes a register that holds an input instruction and a decoding means that decodes the input instruction. a time counting means for counting the number of seconds; a command storage means for temporarily holding an input command under the control of the write control signal; and a counted time value in the time counting means;
and decoding means for decoding and outputting an instruction inputted from the instruction storage means.

〔Example〕

Next, the present invention will be explained with reference to the drawings. FIG. 1 is a block diagram of a first embodiment of the invention. Also,
Figure 3 (a), (b) and (C), Figure 4 (a), (
b) and (C), and FIGS. 5(a), (b), and (C) are timing diagrams showing the operation of this embodiment.

As shown in FIG. 1, this embodiment uses a clock signal C
A shift register 11 that indicates the time length of the write control signal WR in synchronization with LK, an instruction register 12 that temporarily holds input instructions, a selector 13 that is controlled by the value of the shift register 11, and and selected decoders 14, 15 and 16.

In this embodiment, a shift register 11 is used to select a selector 1.
3, and the output of the instruction register 12 is sent to a decoder 14,
This is an embodiment in which one of the decoders 15 or 16 is selected and switched to decode.
This circuit processes instructions in units of bytes (8 bits).

First, the operation of processing a command when a signal with a WR times the basic pulse width is input will be described.

The command input from the command terminal, ~D7, is shown in FIG.
), (b) and (C), the WR double signal is input to the instruction register 12 in the active state,
At the same time as the Wπ signal is released, the instruction is transferred to the instruction register 12.
is maintained. The input WR multiplied signal time length is held in the shift register 11 for a time synchronized with the clock signal CLK. Based on the WR multiplied signal active time information held in the shift register 11, the selector 13 selects an input command. ~D7, decoder 14
, unit WR from decoder 15 and decoder 16
Select the decoder 14 as the decoder corresponding to the signal width and issue the command. ~D7 is output. The instructions Do to D7 are decoded by the corresponding decoder 14, and each part of the microcomputer is controlled by the decoded instructions.

Next, the operation of processing a command when a write control signal WR having twice the basic pulse width is input will be described.

The commands Do to D7 input from the command terminal are shown in FIG.
), (b) and (c), the WR double signal is input to the instruction register 12 in the active state,
At the same time as the Wπ signal is released, the instruction is transferred to the instruction register 12.
is maintained. The input WR multiplied signal time length is held in the shift register 11 for a time synchronized with the clock signal CLK. Based on the WR multiplied signal active time information held in the shift register 11, the selector 13 transfers the input instructions Do to D7 to the decoder 14.
, from among decoder 15 and decoder 16, twice W
Decoder 15 is selected as the decoder corresponding to the R signal width, and the command is issued. ~D7 is output. This corresponding decoder 15 receives the command. ~D7 are decoded, and each part of the microcomputer is controlled by the decoded instructions.

Next, the operation of processing a command when a write control signal Wπ having a width three times the basic pulse width is input will be described.

Command input from the command input terminal. ~D7 is shown in Figure 5 (
As shown in a), (b) and (C), the instruction is input to the instruction register 12 in the active state of the WR multiplication signal, and is held in the instruction register 12 at the same time as the Wπ signal is released. The input WR multiplied signal time length is held in the shift register 11 for a period of time synchronized with the clock signal CL.

Based on the WR multiplied signal active time information held in the shift register 11, the selector 13 selects the input command ~D7 from the decoder 14, decoder 15, and decoder 16 as a triple WR signal width. The decoder 16 is selected as the decoder corresponding to the command. - Output Dfu. This corresponding decoder 16 receives the command. ~
D7 is decoded, and the decoded instructions control each part of the microcomputer.

Next, a second embodiment of the present invention will be described. FIG. 2 is a block diagram of a second embodiment of the invention, and
Figure 3 (a), (b) and (C), Figure 4 (a), (
b) and (c) and FIGS. 5(a), (b) and (C) are timing charts showing the operation of this embodiment, as in the case of the first embodiment.

As shown in FIG. 2, in this embodiment, the clock signal C
A shift register 21 that indicates the time length of the write control signal WR in synchronization with L, an instruction register 22 that temporarily holds the input instruction, and the value of the shift register 21 and the input instruction are simultaneously decoded. Decoder 2 that can
4.

This embodiment is an embodiment in which the selector 13 in the first embodiment is omitted by simultaneously decoding the value of the shift register 21 and the input instruction, and the instruction decoder has a 1-byte ( Instructions are processed in units of 8 bits).

The command input from the command terminal, ~D7, is shown in FIG.
), (b) and (c), input to the command register 22 in the WR low signal active state corresponding to each time width, and at the same time as the WR low signal is released.
Instructions are held in an instruction register 22. The time length of the input signal is held in the shift register 21 for a period of time synchronized with the clock signal CLK. A command to follow.~D7
is decoded by the decoder 24, and each part of the microcomputer is controlled by the decoded instructions. Although the instruction processing has been described, it goes without saying that the present invention can be effectively applied to the instruction processing of a write signal of quadruple width or more.

〔Effect of the invention〕

As described above in detail, the present invention provides the following advantages: by changing the instruction decoding method depending on the length of the write control signal,
This has the effect that a large number of instruction codes can be allocated with a small number of instruction codes, and furthermore, it has the advantage that complicated control at the time of writing can be made unnecessary.

[Brief explanation of the drawing]

1 and 2 are block diagrams of the first and second embodiments of the present invention, respectively, and FIG. 3(a). (b) and (C), Figure 4 (a), (b) and (C)
), and FIGS. 5(a), (b), and (C) are timing diagrams showing the instruction operation of the above embodiment, FIG. 6 is a block diagram of the conventional example, and FIGS. 7(a) and (b). , Figure 8 (a
) and (b), and FIGS. 9(a) and (b) are timing diagrams showing the instruction operation of the conventional example. In the figure, 11.21...shift register,
12゜22, 32...Instruction register, 13...
...-Selector, 14°15, 36.24.34...
····decoder.

Claims (1)

[Claims] In an instruction decoder for a microcomputer that processes multiple instruction word lengths, the instruction decoder includes a register that holds an input instruction and a decoding means that decodes the input instruction, the temporal length of a write control signal time counting means for counting time; command storage means for temporarily holding an input command under the control of the write control signal; An instruction decoder comprising: decoding means for decoding and outputting an input instruction;