JPH0216814A - Selection circuit - Google Patents
Selection circuitInfo
- Publication number
- JPH0216814A JPH0216814A JP16752688A JP16752688A JPH0216814A JP H0216814 A JPH0216814 A JP H0216814A JP 16752688 A JP16752688 A JP 16752688A JP 16752688 A JP16752688 A JP 16752688A JP H0216814 A JPH0216814 A JP H0216814A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- signals
- signal
- state
- signal line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 12
- 230000001360 synchronised effect Effects 0.000 description 2
- 230000009977 dual effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はセレクト回路、特に、半導体集積回路内部での
信号線のセレクト回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a selection circuit, and particularly to a selection circuit for signal lines inside a semiconductor integrated circuit.
次に従来のセレク）・回路について図面を参照して詳細
に説明する。Next, a conventional selector circuit will be explained in detail with reference to the drawings.
第６図は従来のセレクト回路の第１の例を示す回路図で
ある。FIG. 6 is a circuit diagram showing a first example of a conventional select circuit.
第６図に示すセレクト回路は、ある信号線をセレクトす
るための入力信号と、セレク）〜状態の出力は同時に行
なわれ、入力信号Ａ、１３に対し信号線が一本づつセレ
ク１〜される。In the select circuit shown in Fig. 6, the input signal for selecting a certain signal line and the output of the status (SELECT) to are performed simultaneously, and the signal lines are selected one by one for input signals A and 13. .
第７図は従来のセレクト回路の第２の例を示す回路図で
ある。FIG. 7 is a circuit diagram showing a second example of a conventional select circuit.
第７図に示ずモレ２１〜回路は、入力信号Ａ、Ｈに対し
ある決まった複数の信号線がセレクトされる。In the leakage circuit 21 to the circuit not shown in FIG. 7, a plurality of predetermined signal lines are selected for input signals A and H.
」二連した従来のセレクト回路は、各々の出力信号線が
単独でしかセレクトされず、複数本の出方信号線をセレ
クトするためには、あらがしめセレクトを行なうための
入力信号とセレクトされる信号線を対応させて回路を作
る必要があるという欠点があった。In the conventional dual select circuit, each output signal line is only selected individually, and in order to select multiple output signal lines, it is necessary to select the input signal and the input signal for the error selection. The drawback was that it was necessary to create a circuit by matching the signal lines.
〔課題を解決するための手段］
本発明のセレクト回路は、
（人）第１〜ｎの入力信号を順次デコードし、第１〜ｎ
のデコード信号を出力するデコ・−ド回路、（Ｂ）前記
第１〜ｎのデコード信号を保持する保持回路、
（Ｃ）前記保持回路の出力を制御する制御回路、とを含
んで構成される。[Means for Solving the Problems] The selection circuit of the present invention sequentially decodes (person) first to n input signals, and
(B) a holding circuit that holds the first to nth decoded signals; (C) a control circuit that controls the output of the holding circuit. .
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第１図は本発明の第１の実施例を示すブロック図である
。FIG. 1 is a block diagram showing a first embodiment of the present invention.
第１図に示ずセレクＩ・回路は、２つの入力信号Ａ、Ｂ
で４本の信号線Ｆ１〜Ｆ４を選択する場合を示し、
（人）入力信号Ａ、Ｂを順次デコードし、デコード信号
を出力するデコード回路１、
（Ｂ）デコード信号を保持する保持回路２、（Ｃ）保持
回路２の出力を制御する制御回路３、とを含んで構成さ
れる。The select I circuit, not shown in Figure 1, receives two input signals A and B.
(B) A holding circuit 2 that holds the decoded signal; (B) a holding circuit 2 that holds the decoded signal; (C) A control circuit 3 that controls the output of the holding circuit 2.
第２図は、第１図に示ずセレクト回路の詳細回路図であ
る。FIG. 2 is a detailed circuit diagram of a select circuit not shown in FIG. 1.
デコード信号は制御信号Ｃにより、保持回路２に収り込
まれる。The decoded signal is stored in the holding circuit 2 by the control signal C.
保持回路２に保持されている情報は、制御信号りにより
信号線Ｆ］〜Ｆ４に出力される。The information held in the holding circuit 2 is output to signal lines F] to F4 in response to a control signal.
第３図は第１図に示ずセレクト回路の動作を示すタイム
チャートである。ここでは、はじめに入力信号Ａ、Ｂが
′１°’、”］”であり、次に入力信号Ａ、Ｂが“０′
″、“°１′′というように順次入力される場合を示し
である。FIG. 3 is a time chart showing the operation of the select circuit not shown in FIG. 1. Here, first the input signals A and B are '1°', "]", then the input signals A and B are "0'
'', "°1'', etc. are input sequentially.
入力信号Ａ、Ｂによりセレクトされた信号線はＬＯＷレ
ベルとなり、このセレクト状７Ｂは制御（ｉ２号ＣがＬ
ＯＷであるときに保持回路２へ取り込まれる。ここては
最初に入力信号Ａ、Ｂが゛コ″′。The signal line selected by input signals A and B becomes LOW level, and this selection state 7B is controlled (i2 C is LOW)
When the signal is OW, it is taken into the holding circuit 2. Here, input signals A and B are first input.
“１″′であるから、デコード回路１の上から４番目の
信号線Ｔ−（がセレクＩ〜される。このセレクト状態は
制御信号ＣがＬＯＷレベルであるがら保持回路２に取り
込まれ、セレクト状態が保持される。1''', the fourth signal line T-( from the top of the decoding circuit 1 is selected I~. This select state is taken into the holding circuit 2 even though the control signal C is at a LOW level, and the select state is State is preserved.
次に入力信号Ａ、Ｂが’ｏ”、 “１“″が供給され
ると、デコード回路１の上から２番目の信号線Ｇがセレ
クトされ、このときも制御信号ＣがＬＯＷレヘレベある
から保持回路２に取り込まれる。Next, when the input signals A and B are supplied with 'o' and '1', the second signal line G from the top of the decoding circuit 1 is selected, and at this time as well, the control signal C is held at the LOW level. It is taken into circuit 2.
これで必要とする２本の信号線がセレクトできたので、
保持されたセレクト状態の出力を制御するための制御信
号りが入力され、２本の信号線Ｆ２、Ｆ４からＨｉ ｇ
ｈレベルが出力される。Now that you have selected the two signal lines you need,
A control signal for controlling the output of the held selected state is input, and a high signal is output from the two signal lines F2 and F4.
h level is output.
その後、保持回路２はＲＥＳＥＴ信号によりクリアされ
ることになる。Thereafter, the holding circuit 2 will be cleared by the RESET signal.
またデコード回路１は論理ゲートでも構成できる。Further, the decoding circuit 1 can also be configured with a logic gate.
第４図は本発明の第２の実施例を示す回路図、第５図は
第４図のタイムチャートである。FIG. 4 is a circuit diagram showing a second embodiment of the present invention, and FIG. 5 is a time chart of FIG. 4.
デコード状態の保持回路２への取り込みをクロック信号
ＣＬ ＯＣＫに同期させ、また制御回路３への制御信号
りもＮＯＲ回路５によってクロック信号ＣＬ ＯＣＫに
同期させている。The acquisition of the decoded state into the holding circuit 2 is synchronized with the clock signal CLOCK, and the control signal sent to the control circuit 3 is also synchronized with the clock signal CLOCK by the NOR circuit 5.
本発明のセレクト回路は、信号線のデコード状態の保持
を行ない、セレクト状態の出力を制御することにより、
少ない入力信号数で任意の信号線をセレクトできるとい
う効果がある。The select circuit of the present invention maintains the decoded state of the signal line and controls the output of the selected state.
This has the advantage that any signal line can be selected with a small number of input signals.
第１−図は本発明の第１の実施例を示すブロック図、第
２図は第１図の詳細回路図、第３図は第３図の動作を示
ずタイムチャー１〜、第４図は本発明の第２の実施例を
示す回路図、第５図は第４図のタイムチャー１・、第６
図は従来の第１の例を示す回路図、第７図は従来の第２
の例を示す回路図である。
１・・・・・・デコード回路、２・・・・・・保護回路
、３・・・・制御回路、
Ｔ１〜Ｔ８・・・・・・ＭＯＳトランジスタ。
代理人 弁理士 内 原 晋
スカ布号
第
第
肥
第
す
履
αＱＣ，に
臼７
Ｒ巨ＳＥＴ
鋼
図
第
霞Fig. 1 is a block diagram showing the first embodiment of the present invention, Fig. 2 is a detailed circuit diagram of Fig. 1, and Fig. 3 does not show the operation of Fig. 3. is a circuit diagram showing the second embodiment of the present invention, and FIG. 5 is a circuit diagram showing the second embodiment of the present invention, and FIG.
The figure is a circuit diagram showing the first conventional example, and Figure 7 is a circuit diagram showing the conventional second example.
FIG. 2 is a circuit diagram showing an example. 1... Decode circuit, 2... Protection circuit, 3... Control circuit, T1 to T8... MOS transistor. Agent Patent Attorney Susumu Uchihara Sukanu No. 1 Hidai Suori αQC, Niusu 7 R Giant SET Hagane No. 1 Kasumi
Claims (1)
のデコード信号を出力するデコード回路、 （Ｂ）前記第１〜ｎのデコード信号を保持する保持回路
、 （Ｃ）前記保持回路の出力を制御する制御回路、とを含
むことを特徴とするセレクト回路。[Scope of Claims] (A) Sequentially decoding the first to n input signals,
(B) a holding circuit that holds the first to nth decoded signals; and (C) a control circuit that controls the output of the holding circuit. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16752688A JPH0216814A (en) | 1988-07-04 | 1988-07-04 | Selection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16752688A JPH0216814A (en) | 1988-07-04 | 1988-07-04 | Selection circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0216814A true JPH0216814A (en) | 1990-01-19 |
Family
ID=15851330
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16752688A Pending JPH0216814A (en) | 1988-07-04 | 1988-07-04 | Selection circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0216814A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007253241A (en) * | 2006-03-20 | 2007-10-04 | Nantsune:Kk | Safety cover mounting structure for cutting device such as food slicer |
-
1988
- 1988-07-04 JP JP16752688A patent/JPH0216814A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007253241A (en) * | 2006-03-20 | 2007-10-04 | Nantsune:Kk | Safety cover mounting structure for cutting device such as food slicer |
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