JPS61125647A - Microprogram controller - Google Patents

Abstract

PURPOSE:To improve greatly the efficiency of program capacity by controlling optional by and sequentially the arithmetic control code processing and other control code processing on the same step with the sequence control signal and at a program level. CONSTITUTION:A storage STG2 storing a microprogram is program-accessed by a muPC1 and outputs an arithmetic control code 201, other control code 202, a branch code 203 and step processing sequence control signals alpha204 and beta205. A control register CR4 storing the code 202 latches an output part for code 202 of the STG2 synchronously with a CK701 according to signals CLR603 and LD604. A sequence control circuit SC6 gives the sequence to the step processing to control based on the feed of signals alpha204 and beta205 of the STG2.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a microprogram control device, and is particularly applicable to microprograms that frequently require ordering of arithmetic control and other control codes in steps. The present invention relates to a microprogram control device suitable for coding.

[Background of the invention]

Unlike the general 7Senpra program, which has instruction codes for only the main processor, the microprogram also describes the control mode for the peripheral circuits, as disclosed in Japanese Patent Laid-Open No. 186846/1983. It had the advantage of being able to perform detailed processing that was directly connected to the hardware. However, conventionally, these two processing order instructions and controls have been uniquely fixed, and this constraint has forced wasteful coding that requires two steps for one process of arithmetic control and other control codes corresponding to a series of instructions and controls. Ta. In addition, in reducing microprogram steps, Japanese Patent Laid-Open No. 59-53 discloses that a stack pointer control circuit is provided.
There are some known examples of 942, but nothing has been suggested regarding the problem of requiring two steps to process one arithmetic control/other control code.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to solve such conventional problems and provide a microprogram control device that reduces the capacity of microprograms.

[Summary of the invention]

The present invention provides a microprogram in storage with a field that defines the processing order of the arithmetic control code and other control codes, thereby ordering these two, and making it possible to perform one processing, which was previously forced by the constraint of a fixed processing order. This is an attempt to reduce the number of steps that use two steps to one.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a detailed circuit diagram of the sequence control circuit 6 shown in FIG.

In FIGS. 1 and 2, a microprogram program counter (μPC) 1 performs address setting using a control code 501 and an address 502 in synchronization with a clock CK701. A storage (8TG) 2 for storing microprograms is program accessed by μPCI, and receives arithmetic control code 201, other control code 202, blatch code 203, and step processing order control signals α (204) and β (205). Output.

The instruction register (IR) 3 that stores the arithmetic control code outputs the arithmetic control code output part of the 5TG2 by CK.
701”, clear (CLR) 601, load (
LD) Latch according to the 602 signal. Control register (CR) 4 that stores other control codes is 5T
Synchronize the other control code output section of G2 with CK701,
Latch according to the CL R, 603 and LD 604 signals. The bratch code register (BR) 5 latches the blatch code output part of 5TG2 in synchronization with CK701, and sends the control code 501 and address 502t- to μPCI.
Output. The sequence control circuit (SC) 6 controls the fields α (204) and β of the 5TG2 in the above sequence of operations.
Step processing is ordered and controlled based on (205). Among these, 7 lip-flop (FF) 63 is '0''
1'' indicates the beginning of the step, and 1'' indicates the middle of the step.

In Figure 3, (1) is α (204), β (205)
This is a case in which the processing of IR3 and CR4 in FIG. 1 are independent of each other and may be processed simultaneously within a step, and both are set in one clock and one step (CLR
601, Ln2O3, CLR603, Ln2O3).

In (2), α (204) is 11” and β (205) is “0”.
” in Figure 1, if you want to process IR3 first and then process CR4 (for example, if you want to write the result of calculation in IR3 to memory in CR4),
Clear CR and 4 with LR603 and IR with Ln2O3
After the processing of 3 is completed, the KCLR 601 and LD 604 perform the processing of CR4.

(8) is used when you want to do the opposite of (2) (for example, CR
4, if you want to test the value calculated in the previous step and perform calculation processing with IR3), α (204) is 0'', β (2
05) is 1", and in Figure 1, after C 4 processing, 1 3
For processing, from CLR601, Ln2O3, Ln
This is similarly realized in 2O3 and CLR603.

Next, the operation in FIG. 1 will be explained with reference to the timing chart in FIG. 5 based on the state transition diagram in FIG. 4 for each operation in FIG. 3.

At timing 1 in FIG. 5, (1) in FIG.
04 and β (205) are both 1'', the output 621 of the NAND gate 62 becomes 0, clearing the flip-flop 63, and the output Q631 becomes 6''. As a result, the AND gate 64 outputs 641"0", so L-C1
1204"l", β205"1', the EOR gate outputs LD602"1", Ln2O3"l" (However, L
D601=CLR602, LD603=CLR6Q4)
The process (1) is performed as follows. By timing 1:1, CK 701 to μPC1 is transmitted to AND gate 611, and the address is changed. This allows 5TG2
The next steps (201 to 205) are output.

At timing 2 in FIG. 5, (2) in FIG.
04)'1'', β(205)'O', so NAN
The output 621 of the D gate 62 is 11''. The output 641 of the FF 63 at timing 1.2 is 0'' and α(204)1''.

β(205)"1", CLR603"1" (
The first clock processing of 2) is performed. After this, at timing 2.1, since FF63 is 71'' (in the middle of the step), the output 631 of FF63 is 0'' and CK70 is sent to μPct.
1 is not given, and the outputs (201 to 205) of S'rG2 remain unchanged. At timing 2゜2, FF63"l", C
It is inverted and turned on by K702.

At timing 3 in Figure 5, the second clock of (2) is:
α (204) 1″, β (205) 0′, output 621″ 1
",l;'l;'63"0" causes output 631"1"
, the output 641"1n of the AND gate 64 becomes EO
Through R gate, output CLR601"l", LD604
"l" and L"t", processing 312>f is performed. Now, at timing 3.2, in synchronization with CK702, a new F
1'' is set to F63.

Since the operation shown in FIG. 3 (8) is just the reverse of (2), the explanation will be omitted.

The above has been explained using the state transition diagram shown in FIG.

According to this embodiment, in Figure 6, since the conventional processing order was fixed (for example, A4B), one step is required in case (a), but if you want to process in the order of B-+A, (b)
What used to take two steps (t) can now be done in one step as shown in (C), which is effective in reducing the program capacity.

〔Effect of the invention〕

As described above, according to the present invention, the arithmetic control code processing and its low control code processing on the same step can be controlled in any order at the program level using the order control signal, thereby greatly increasing the program capacity efficiency. .

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a detailed circuit diagram of the sequential control circuit shown in FIG. 1, and FIG. 3 is a diagram showing the types of sequential processing performed in FIG. 1. , Figure 4 is the third
FIG. 5 is a timing chart showing the operating state of FIG. 1, and FIG. 6 is a diagram showing the effects of the present invention. 1...Program counter, 2...Storage, 3
...Instruction register, 4...Control register, 5...Plastic cord register, 6.
...Order 20th person 3 times 0 0, Dorcf-cctre erasure 4 former 60th kōshaku nai w cg momme kan

Claims (1)

[Claims] 1. A program counter for setting the address of the microprogram, and a storage for storing the microprogram consisting of arithmetic control codes and other control codes;
A microprogram control device having a plurality of registers for latching outputs from the storage, a sequence control circuit for controlling the ordering of arithmetic control processing or other control processing, and a field for specifying the ordering in the storage. A microprogram control device characterized in that arithmetic control processing or other control processing is ordered in accordance with the contents of the field and output to the register.