JPH04326816A - Time division counting circuit - Google Patents

Abstract

PURPOSE:To prevent a counting circuit at every individual communication signal in a multiplex signal from being increased with the increase of the number of multiplexing. CONSTITUTION:A RAM circuit 4 is provided to be operated by an address for one cycle of the multiplex signal, and an adder circuit 2 is provided to add '1' between the output result of the RAM circuit 4 and the logic ('1' or '0') of the multiplex signal. Then, the output result of the adder circuit 2 is inputted to the RAM circuit 4. Thus, since a read-write operation is executed at every address of the RAM circuit 4, the counting circuit at every communication signal (at every address) can be realized.

Description

[Detailed description of the invention]

0001

[Industrial Field of Application] The present invention relates to a counting circuit, and in particular to a logic "1" or "0" for each time-division multiplexed communication signal.
”Relating to a time division counting circuit that performs calculations.

0002

2. Description of the Related Art As shown in FIG. 2, a conventional counting circuit decodes an address signal 5 corresponding to a multiplexing period in a decoding circuit 10 to create pulses φ1 to φn for each communication signal on the multiplexed signal. The counter circuit 9 is operated by ANDing the multiplexed signal for each communication signal and the φ pulse, and the output of the counter circuit is obtained as the result signal 11, and the counting circuit is configured and operated independently for each communication signal. was.

0003

[Problems to be Solved by the Invention] Therefore, in this conventional counting circuit, as the number of communication signals to be accommodated increases and the multiplicity increases, the number of AND and counter circuits provided for each communication signal, including the decoding circuit, increases proportionally. As a result, the hardware size increases and the device cannot be made smaller or more economical.

An object of the present invention is to provide a time division counting circuit which eliminates such drawbacks.

[0005]

[Means for Solving the Problems] A time division counting circuit according to the present invention operates based on an address for one period of a multiplexed signal.
an AM circuit, a holding circuit that temporarily holds the output of the RAM circuit for each address, an adder circuit that performs +1 addition based on the output of the holding circuit and the logic (“1” or “0”) of the multiplexed signal; The present invention is characterized by comprising an R/W control circuit that controls input/output of the output of the adder circuit to the RAM circuit between the RAM circuits.

[0006]

Embodiments Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of one embodiment of the present invention. This time-division counting circuit includes a RAM circuit 4 that operates according to addresses for one period of a multiplexed signal, and a
A holding circuit 7 temporarily holds the output of each address for each address, and a logic (“1” or “1”) of the output of this holding circuit 7 and the multiplexed signal.
0"), and an R/W control circuit 3 that controls input/output signals to the RAM circuit 4 between the output of the addition circuit 2 and the RAM circuit 4.

The RAM circuit 4 operates for each communication signal in accordance with the address signal 5 for one period of the multiplexed signal 1, and performs read/write operations in accordance with the R/W control signal 8. In the case of counting logic "1" on the multiplexed signal in the corresponding communication signal, if the content of address #1 of RAM circuit 4 is 0, when reading address #1, the RAM
The content 0 of the circuit 4 is held in the holding circuit 7, outputted as the count result signal 6, and inputted to the addition circuit 2. At this time, if the logic of the corresponding communication signal of the multiplexed signal 1 is "1", the adder circuit 2 calculates 0+1 and outputs "1" to the R/W control circuit 3. Since the R/W control circuit 3 is controlled by the R/W control signal 8, it does not output when the RAM circuit 4 is reading, but outputs the calculation result "1" from the adder circuit 2 to the RAM circuit 4 when writing. . When writing RAM circuit 4,
The input from the R/W control circuit 3 is stored in its own memory.

Since the above operation is executed in units of one address, when the RAM circuit 4 is read in the state of the next address address #1, the stored calculation result "1" is transferred from the RAM circuit 4 to the holding circuit 7. It is held and output as a counting result signal 6, and is also input to the adder circuit 2. At this time, if the corresponding communication signal of multiplexed signal 1 is "1", adder circuit 2 is 1+
1 and outputs “2” to the R/W control circuit 3.

As described above, counting of logic "1"s of communication signals corresponding to address #1 is executed. A change in address is a change in the communication signal, and a counting circuit can be configured for communication signals in all multiplexed signals.

[0011]

Effects of the Invention As explained above, the present invention provides a random access memory (
By configuring a time-division counting circuit that operates in the multiplexed format using RAM), the hardware scale, which increases in proportion to the number of lines accommodated and the number of multiplexes, can be realized with a minimum fixed scale. This has the effect of providing a simple counting circuit for highly multiplexed signals, which is less affected by fluctuations in the number of lines accommodated and the number of multiplexed lines.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a time division counting circuit of the present invention.

FIG. 2 is a diagram showing a conventional counting circuit.

[Explanation of symbols]

1 Multiplexed signal 2 Adder circuit 3 R/W control circuit 4 RAM circuit 5 Address signal 6 Counting result signal 7 Holding circuit 8 R/W control signal 9 Counter circuit 10 Decode circuit 11 Result signal

Claims (1)

[Claims] 1. A RAM circuit that operates according to addresses for one period of a multiplexed signal, a holding circuit that temporarily holds the output of the RAM circuit for each address, and a logic ("1" or "0"); and an R/W control circuit that controls input/output of the output of the adder circuit to the RAM circuit between the RAM circuits. time division counting circuit.