JPH04155957A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the breakage of an internal circuit by obtaining a diode having a large junction area between high and low potential power supplies. CONSTITUTION:Electrodes 12, 15, 22, 13, 14,16 to be connected with respective N-type regions 5a, 5d, 5e and P-type diffusion layers 21a, 21b, 20 are provided respectively. Then, a silicon nitride film 17 is accumulated on the whole surface so that contact holes are provided on the electrodes 15, 22, and a wiring 18 to be connected with the electrodes 15, 22 of the contact holes are provided selectively. Subsequently, a silicon nitride film 19 is accumulated on the surface containing the wiring 18 so that the contact hole is provided on the wiring 18. In this case, the electrodes 12 and 14 are connected with input-output terminals; the electrodes 13 and 16, with a low potential power supply VCC and the wiring 18, with a high potential power supply VDD to constitute an electrostatic protective element part.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device having an electrostatic protection element.

[Conventional technology]

As shown in FIG. 3, a conventional semiconductor device having an electrostatic protection element includes N+ type buried layers 3a, 3b and a P" type diffusion layer 4 selectively provided on one main surface of a P type silicon substrate 1. After forming, an N-type epitaxial layer is grown.Next, the N-type epitaxial layer is selectively oxidized to form a P-type silicon substrate 1.
．． A field oxide film 2 for element isolation is formed reaching each of the N+ type buried layers 3a and 3b and the P+ type buried layer 4, and the N type regions 5a and 5b on the N+ type buried layer 3 and the N+ type buried layer 4 are formed. Including layer 3
N-type regions 5c and 5d are formed on b.

Next, P-type impurities are selectively introduced into the P-type silicon substrate 1.
Next, P-type impurities are introduced into the surfaces of the N-type regions 5b and 5c to form the P-type diffusion layer 20.
1a, 21b are provided in the 0th order, N type regions 5a, 5d and P type diffusion layer 21a.

Electrodes 12, 15°13. connected to electrodes 21b and 20, respectively.
Silicon nitride film 1 is provided on the entire surface of the 0th order where 14 and 16 are provided respectively.
7 is deposited to form a contact hole on the electrode 15, and a wiring 18 connecting to the electrode 15 in the contact hole is selectively provided. Next, a silicon nitride film 19 is deposited on the surface including the wiring 18 to form a contact hole on the wiring 18.

Here, electrode 12 and electrode 14 are connected to input/output terminals, electrode 13 and electrode 16 are connected to low potential power supply VDD,
The wiring 18 is connected to a high potential power supply VCC and constitutes an electrostatic protection element section.

Note that an N1 type buried layer may be provided below the N type region.

FIG. 4 is an equivalent circuit diagram of FIG. 3.

As shown in Figure 4, a diode 23 is added between the high potential side power supply DD and the input/output terminal, a diode 24 is added between the low potential side power supply vcC and the input/output terminal, and a diode 25 is added between the power supply VDD and VCC. .

At the moment when a pulse voltage due to static electricity is applied between the power supplies VDD and VCC and the input/output terminals or between the power supplies VDD and VCC, the diode becomes equivalent to a capacitance, so the charge due to static electricity is accumulated in the diode.

After that, ti due to static electricity flows between the power supplies V DD , V cc and the input/output terminals or between the voltage MV0 and 700 through forward bias diodes, or the power supply DD, V
c and the input/output terminal or between the power supply vDtI and 700.

Further, areas other than the element region of the conventional semiconductor device are covered with a thick silicon oxide film 2.

[Problem to be solved by the invention]

In this conventional semiconductor device, when high-voltage static electricity is applied, the diode added between the power supplies is small, so the electric charge that should have been accumulated in the diode flows into the internal circuit at the moment static electricity is applied, causing the internal circuit to overflow. It had the disadvantage of being destroyed.

[Means to solve the problem]

The semiconductor device of the present invention includes a first N-type region provided on a P-type semiconductor substrate to form a protection diode between an input/output terminal and the semiconductor substrate, and a first N-type region forming a protection diode between a high potential power supply and the semiconductor substrate. and a P-type region provided on the surface of the second N-type region to form a protection diode between the high potential source and the input/output terminal, wherein A protection diode with a large junction area is connected in parallel to the protection diode between the high potential power source and the semiconductor substrate by a third N-type region provided in the semiconductor substrate.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a sectional view of a semiconductor chip showing one embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of FIG. 1.

As shown in FIGS. 1 and 2, N1 type buried layers 3a, 3b and P
After forming the +-type diffusion layer 4, an N-type epitaxial layer is grown, and the N-type epitaxial layer is selectively oxidized to form a P-type silicon substrate 1. N1 type buried layers 3a, 3b, P
A field oxidation M2 for element isolation reaching each of the + type buried layers 4 is formed, and an N type region 5a is formed on the N1 type buried layer 3a.

5b, N-type regions 5c and 5d on the N-type buried layer 3b, and N-type region 5e on the P-type silicon substrate. P-type impurities are selectively introduced into the P-type silicon substrate 1. A connecting P type diffusion layer 20 is provided in the 0th order, an N type region 5b,
P-type impurity is introduced into the surface of 5c to form a P-type diffusion layer 21a,
Next, electrodes 12, 15, 22, 13, 14, and 16 connected to the N-type regions 5a, 5d, and 5e and the P-type diffusion layers 21a, 21b, and 20 are provided, respectively. A silicon nitride film 17 is deposited on the electrode 15.2.
A contact hole is provided on the electrode 15.2 of the contact hole.
Next, a silicon nitride film 19 is deposited on the surface including the wiring 18 and the wiring 18 is selectively provided to connect to the wiring 18.
A contact hole is provided on 8.

Here, the electrode 12 and the electrode 14 are connected to the input/output terminal, the electrode 13 and the electrode 16 are connected to the low potential power supply VCC, and the wiring 18 is connected to the high potential power supply ■DD, forming an electrostatic protection element section. do.

〔Effect of the invention〕

As described above, the present invention has an epitaxial layer of an opposite conductivity type on a semiconductor substrate of one conductivity type in a region other than an element region, a pre-isolation region, and a wiring region, and has an epitaxial layer of an opposite conductivity type connected to a power source on the epitaxial layer of an opposite conductivity type. By having a wiring pattern, a diode having a large junction area between a high potential power source and a low potential power source can be obtained. The moment static electricity is applied, this diode becomes equivalent to a large capacitance and can store most of the charge, thereby reducing the current flowing through the internal circuit.

Therefore, damage to the internal circuit can be prevented.

[Brief explanation of drawings]

FIG. 1 is a sectional view of a semiconductor chip showing an embodiment of the present invention, FIG. 2 is an equivalent circuit diagram of FIG. 1, and FIG. 3 is a sectional view of a semiconductor chip showing an example of a conventional semiconductor device 1. FIG. 4 is an equivalent circuit diagram of FIG. 3. DESCRIPTION OF SYMBOLS 1... P type silicon substrate, 2... Field oxide film, 3a, 3b... N type buried layer, 4... P+ type diffusion layer, 5a, 5b, 5c, 5d, 5e-N type area, 12,
13. 14. 15. 16. 22... is the pole,
17.19...Silicon nitride film, 18...Wiring, 2
0...P+ type diffusion layer, 21...P type diffusion layer.

Claims (1)

[Claims] a first N-type region provided on a P-type semiconductor substrate to form a protection diode between an input/output terminal and the semiconductor substrate; and a second N-type region to form a protection diode between a high potential power supply and the semiconductor substrate. and a P-type region provided on the surface of the second N-type region to form a protection diode between the high-potential power source and the input/output terminal, the third N-type region provided on the semiconductor substrate. A semiconductor device comprising a protection diode with a large junction area connected in parallel to the protection diode between the high potential power source and the semiconductor substrate.