JPH04150073A - Junction type field effect transistor - Google Patents

Abstract

PURPOSE:To make it possible to set a drain current with accuracy by installing a first conducting type semiconductor substrate where a plurality of grooves are formed at a specified span on one main plane, and a second conducting type gate region formed along the grooves. CONSTITUTION:An n type semiconductor region 2 is formed on an n<+> semiconductor substrate 1. An n<+> type semiconductor region 3, which is a source's contact region is formed at a depth of around 1mum. Then, a groove ranging from about 5 to 8mum deep is formed at a place where a gate region is formed along the groove, a p<+> type semiconductor region 5 is formed at a depth of about 1mum. Then, the surface of the substrate 1 is covered with an oxide film 4, thereby forming an aluminum electrode 6 on the gate region 5 and the source' s contact region 3. Moreover, a gate electrode and the source electrode 6 are installed on the front surface while a drain electrode 100 is installed on the rear surface.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a junction field effect transistor (hereinafter referred to as J-FE).
In particular, the present invention relates to the structure of a single-gate junction field effect transistor.

[Prior Art] Taking an n-channel J-FET as an example, a conventional J-FET has a structure as shown in FIG. 3. That is,
It has an n-type semiconductor region 2 formed by epitaxial growth on a p+ type semiconductor substrate 7, and in this n-type semiconductor region 2, a source and train contact region is formed with an n-type semiconductor region 3, and a p-type semiconductor region 2 is formed. The semiconductor region 5 formed a gate region.

Electrodes 6 are provided in the source and drain contact regions 3 from the surface, and the gate region 5 is electrically connected to the p + -type semiconductor substrate 7 via the p + -type semiconductor region 8 . The p+ type semiconductor substrate 7 has a structure in which electrodes are taken from the back surface.

Therefore, the train current IDSS when the gate is at 0 bias, which is an important characteristic of J-FET, is divided between the p' type semiconductor region 5 which is the front gate region and the p' type semiconductor region 5 which is the back gate region.
It is determined by the distance between the °-type semiconductor substrates 7, that is, the channel thickness d'.

[Problems to be Solved by the Invention] In the two conventional J-FETs, as described above, the drain current IDSS is determined by the channel thickness d' due to its structure. There is a problem in that it is very difficult to uniformly control each element within the plane of the wafer so as to obtain a drain current I DSS of .

That is, an n-type semiconductor region 2 that will become a channel region is grown by epitaxial growth, but this n-type semiconductor region 2
(hereinafter referred to as the thickness) within the wafer surface, and the p′″ semiconductor region 5 which is the surface gate region.
Due to diffusion variations (variations in the depth direction) during the formation of the wafer, there is a problem in that the 1055 characteristics vary greatly among the elements within the wafer surface.

Therefore, the in-plane variation in shrimp thickness t can be reduced by ±3% or ±5
% and to reduce diffusion variations, the gate region 5 is formed by ion implantation. However, in order to check whether the channel thickness d' is within the allowable range, the check button shown in FIG. 4 is used. It was provided in the device to manage the bunch-through voltage (hereinafter referred to as VPT) between the front gate and the back gate.

That is, punch-through voltage VPT and train current I
There is a correlation with DSS, and the channel thickness d' was controlled based on this correlation.

However, in the conventional J-FET, since the thickness of the impurity region 5 cannot be precisely controlled, due to its structure, it is not possible to significantly reduce the variation in the drain current rDSS within the wafer surface, and it is difficult to check the characteristics of the pellet. Train current IDSS failures occur frequently.

This becomes more noticeable as the wafer diameter increases.

In addition, the epitaxial wafer, which is the material, has a strict standard for variation in thickness of ±3% to ±5%, so the unit cost is high, and since controlling the channel thickness d' requires man-hours, the manufacturing cost is very high. The problem of high prices also disappeared.

[Means for Solving the Problems] The gist of the present invention is to provide: - a semiconductor substrate of a first conductivity type in which a plurality of grooves opening in a main surface are formed at predetermined intervals; It includes a conductive type gate region, a first conductive type source contact region formed on one main surface between the gate regions, and a drain electrode provided on the back surface of the semiconductor substrate.

[Operation of the invention] In the junction field effect transistor having the above structure, a depletion layer develops at the junction between the gate region and the substrate due to the voltage applied to the gate region, and current flowing between the source contact region and the drain electrode is suppressed. Control. Here, the train current that flows when the bias of the gate region is set to "0" is controlled by the interval between the gate regions formed along the groove, but this interval is controlled by the processing accuracy when forming the groove. .

Generally, the accuracy of groove processing is higher than the accuracy of the impurity diffusion distance, so the drain current can be accurately set to the set value.

[Example code] Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1(c) is a sectional view showing a first embodiment of the J-FET of the present invention, and the manufacturing method thereof is shown in FIGS. 1(a) to (c). An n-type semiconductor region 2 of about 10×15 μm is formed on an n+ semiconductor substrate 1 by epitaxial growth,
An n + -type semiconductor region 3, which is a source contact region, is formed in the n-type semiconductor region to a depth of about 1 μm (see Fig. 1).
a)).

Next, a trench of about .delta. to 8 .mu.m is dug at the location where the gate region is to be formed, and a p'-type semiconductor region 5, which is the gate region, is formed to a depth of about 1 .mu.m along this trench.

After this, the surface of the substrate 1 is covered with an oxide film 4 (Fig. 1(b)).
reference).

Finally, an aluminum electrode 6 is formed on the gate region 5 and the source contact region 3, and the gate and source electrodes 6 are provided on the surface, and the drain electrode 100 is provided on the surface.
See C). Note that the channel thickness d is determined by the distance between gate regions. In this case, the channel thickness d is controlled by the accuracy of the lithography technique for forming the groove, and since the gate region 5 is only the surface of the groove, there is no variation in the channel thickness d' as in the conventional case.

FIG. 2(c) is a sectional view showing a second embodiment of the J-FET of the present invention, and a method for manufacturing the same will be described with reference to FIGS. 2(a) to (C).

The difference from the first embodiment is that when forming the n+ type semiconductor region 3 which is the contact region of the source, one pattern is formed without separating each region, and grooves for the gate region are formed. The point is to separate the source regions. With this method, the source contact region is formed over the entire surface of the source region, so the photoresist alignment accuracy when forming the contact window with the aluminum electrode after this has the advantage of being more flexible than in the first embodiment. This is especially advantageous when reducing the channel thickness d. The rest is the same as the first embodiment, so the explanation will be omitted.

[Effects of the Invention] As explained above, in the present invention, the channel thickness d is determined by the interval between each gate region formed from the surface, that is, the design dimension of the lithography pattern. Not affected. Therefore, there is an effect that almost no variation in drain current IDSS occurs within the wafer surface. Furthermore, since there is no need for special management of variations in thickness or control of the depth of the gate region, there is also the advantage that wafers can be manufactured at relatively low cost.

[Brief explanation of drawings]

1(a) to (C) are cross-sectional views showing the manufacturing process of the first embodiment of the J-FET of the present invention, and FIGS. 2(a) to (c) are cross-sectional views showing the manufacturing process of the first embodiment of the J-FET of the present invention. 3 is a cross-sectional view of a conventional J-FET, and FIG. 4 is a cross-sectional view showing the manufacturing process of an example. FIG. 3 is a sectional view showing a check pattern. 1......n+ type semiconductor substrate, 2...
・・・N-type semiconductor region, ・N゛-type semiconductor region (source contact region), 4. Oxide film, ・P゛-type semiconductor region (gate region), 7. ...Aluminum electrode, ・...p+ type semiconductor substrate, ...p" type semiconductor region.

Claims (1)

[Claims] A first groove in which a plurality of grooves opening on one principal surface are formed at predetermined intervals.
a conductive type semiconductor substrate, and a second semiconductor substrate formed along the groove.
A junction field effect transistor including a conductive type gate region, a first conductive type source contact region formed on one principal surface between the gate regions, and a drain electrode provided on a back surface of a semiconductor substrate.