JPH0414874A - Metal wiring structure of semiconductor integrated circuit device - Google Patents
Metal wiring structure of semiconductor integrated circuit deviceInfo
- Publication number
- JPH0414874A JPH0414874A JP11816590A JP11816590A JPH0414874A JP H0414874 A JPH0414874 A JP H0414874A JP 11816590 A JP11816590 A JP 11816590A JP 11816590 A JP11816590 A JP 11816590A JP H0414874 A JPH0414874 A JP H0414874A
- Authority
- JP
- Japan
- Prior art keywords
- titanium
- boride
- integrated circuit
- semiconductor integrated
- circuit device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 30
- 229910052751 metal Inorganic materials 0.000 title claims description 32
- 239000002184 metal Substances 0.000 title claims description 32
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims abstract description 63
- 239000010936 titanium Substances 0.000 claims abstract description 63
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 63
- 239000010410 layer Substances 0.000 claims abstract description 22
- 238000009792 diffusion process Methods 0.000 claims abstract description 19
- 238000000034 method Methods 0.000 claims description 26
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 229910021332 silicide Inorganic materials 0.000 claims description 6
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 5
- 239000002356 single layer Substances 0.000 claims description 4
- QDMRQDKMCNPQQH-UHFFFAOYSA-N boranylidynetitanium Chemical compound [B].[Ti] QDMRQDKMCNPQQH-UHFFFAOYSA-N 0.000 claims 1
- 239000000758 substrate Substances 0.000 abstract description 8
- QYEXBYZXHDUPRC-UHFFFAOYSA-N B#[Ti]#B Chemical compound B#[Ti]#B QYEXBYZXHDUPRC-UHFFFAOYSA-N 0.000 abstract description 7
- 230000015572 biosynthetic process Effects 0.000 abstract description 7
- 238000010438 heat treatment Methods 0.000 abstract description 6
- 229910052796 boron Inorganic materials 0.000 abstract description 5
- 238000006243 chemical reaction Methods 0.000 abstract description 5
- -1 boron ions Chemical class 0.000 abstract description 4
- 239000000203 mixture Substances 0.000 abstract description 4
- 239000002344 surface layer Substances 0.000 abstract description 4
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 3
- 229910033181 TiB2 Inorganic materials 0.000 abstract description 3
- 230000008018 melting Effects 0.000 abstract description 3
- 238000002844 melting Methods 0.000 abstract description 3
- 230000001590 oxidative effect Effects 0.000 abstract description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 3
- 230000006641 stabilisation Effects 0.000 abstract 1
- 238000011105 stabilization Methods 0.000 abstract 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 10
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 9
- 229910052802 copper Inorganic materials 0.000 description 9
- 239000010949 copper Substances 0.000 description 9
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 6
- 229910052737 gold Inorganic materials 0.000 description 6
- 239000010931 gold Substances 0.000 description 6
- 238000001312 dry etching Methods 0.000 description 5
- 229910000838 Al alloy Inorganic materials 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 4
- 238000002513 implantation Methods 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 238000001755 magnetron sputter deposition Methods 0.000 description 3
- 229910052763 palladium Inorganic materials 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000000654 additive Substances 0.000 description 2
- 230000000996 additive effect Effects 0.000 description 2
- 238000007772 electroless plating Methods 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 238000003801 milling Methods 0.000 description 2
- 239000002365 multiple layer Substances 0.000 description 2
- 238000000992 sputter etching Methods 0.000 description 2
- 238000000137 annealing Methods 0.000 description 1
- 238000005885 boration reaction Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 238000005121 nitriding Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 238000005546 reactive sputtering Methods 0.000 description 1
- 230000009257 reactivity Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体集積回路装置の配線構造および形成方法
に関し、特に半導体集積回路装置の拡散層上、多結晶シ
リコン上、金属ケイ化物上、金属配線上あるいは絶縁膜
上に設けられた、チタニウムホウ化物と下層配線および
絶縁膜との密着性の保持、耐熱性の向上、コンタクト抵
抗の低減。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a wiring structure and a method for forming a semiconductor integrated circuit device. Maintaining adhesion between titanium boride and lower wiring and insulating films provided on wiring or insulating films, improving heat resistance, and reducing contact resistance.
オーミック接合性の確保を目的としたチタニウムと、前
記チタニウム上に設けられたコンタクト部および配線層
全体のエレクトロマイグレーション(以下E、M、と記
す)耐性、ストレスマイグレーション(以下S 、M、
と記す)耐性、耐熱性の向上を目的としたチタニウムホ
ウ化物と、前記チタニウムホウ化物上に設けられた配線
抵抗の低減な目的とした単層あるいは複数層の導電膜よ
り構成される半導体集積回路装置の配線構造および形成
方法に関する。Electromigration (hereinafter referred to as E, M) resistance, stress migration (hereinafter referred to as S, M,
) A semiconductor integrated circuit composed of a titanium boride for the purpose of improving durability and heat resistance, and a single-layer or multiple-layer conductive film provided on the titanium boride for the purpose of reducing wiring resistance. The present invention relates to a device wiring structure and forming method.
C従来の技術〕
従来の半導体集積回路装置の金属配線構造および形成方
法は、第4図(a)に示す通り、半導体基板101上に
フォトリソグラフィー2 ドライエツチング、イオン注
入、熱拡散、CVD等の既知の手法を用いて、例えばシ
リコン酸化膜2シリコン窒化膜等より構成される厚さ0
.5〜1.0μmの層間絶m膜102に開口されたコン
タクトホール103の底部のみにp型あるいはn型の拡
散層104が存在する構造を形成する。C. Prior Art] As shown in FIG. 4(a), the conventional metal wiring structure and formation method of a semiconductor integrated circuit device is based on a process such as photolithography, dry etching, ion implantation, thermal diffusion, CVD, etc. on a semiconductor substrate 101. Using a known method, for example, a film with a thickness of 0 consisting of two silicon oxide films, two silicon nitride films, etc.
.. A structure is formed in which a p-type or n-type diffusion layer 104 exists only at the bottom of a contact hole 103 opened in an interlayer insulation film 102 with a thickness of 5 to 1.0 μm.
続いて(b)の通り、既知の手法であるり、C,マグネ
トロンスパッタ法によりチタニウム105を成膜パワー
2〜10KW、圧力5〜20mTorrの条件で0.0
5〜0.20μmの厚みで形成する。チタニウム105
は、コンタクト抵抗の低減、拡散層に対するオーミック
接合性の確保、上下層間の密着性改善、耐熱性の向上等
を目的として形成されるものである。Next, as shown in (b), titanium 105 was deposited using a known method or by C magnetron sputtering under conditions of a power of 2 to 10 KW and a pressure of 5 to 20 mTorr.
It is formed with a thickness of 5 to 0.20 μm. titanium 105
is formed for the purpose of reducing contact resistance, ensuring ohmic contact with the diffusion layer, improving adhesion between upper and lower layers, improving heat resistance, etc.
続いてチタニウムをターゲット、N2を反応ガスとした
反応性スパッタ法、あるいはT I C14力ス反応ソ
ースとしたCVD法により窒化チタニウム108を0.
05〜0.20μmの厚みでチタニウム105上に形成
するかあるいはN3、NH3ガスを用いたランプアニー
ル法によりチタニウム105表面部のみをスパッタ法、
CVD法で形成した厚みと同じたけ窒化させて同様の構
造を得るようにする。Subsequently, titanium nitride 108 was deposited at 0.05% by reactive sputtering using titanium as a target and N2 as a reactive gas, or by CVD using a TIC14 reaction source.
Form on titanium 105 to a thickness of 0.05 to 0.20 μm, or sputter only the surface portion of titanium 105 by lamp annealing using N3 or NH3 gas.
Nitriding is performed to the same thickness as that formed by the CVD method to obtain a similar structure.
この窒化チタニウム108は半導体基板と金属配線との
間の拡散・反応の防止、耐熱性、耐E 、M。This titanium nitride 108 prevents diffusion and reaction between the semiconductor substrate and metal wiring, has heat resistance, E resistance, and M resistance.
性および耐S、M、性の向上を目的として形成され、一
般にバリアメタルと呼ばれるものである。It is formed for the purpose of improving properties, S, M, and properties, and is generally called a barrier metal.
さらに(C)に示す通り、アルミニウムあるいはこれに
シリコン、銅、パラジウム等の添加元素を最大でも5%
含有したアルミニウム合金、銅、金等より構成される導
電膜109を窒化チタニウム108上にり、C,マグネ
ストロンスパッタ法により成膜パワー2〜10KW、圧
力5〜20[1lTOrrの条件で0.50〜1.00
μmの厚みで形成する。Furthermore, as shown in (C), at most 5% of aluminum or additional elements such as silicon, copper, palladium, etc.
A conductive film 109 composed of aluminum alloy, copper, gold, etc. containing aluminum alloy, copper, gold, etc. is deposited on the titanium nitride 108, and is deposited by C, magnetron sputtering at a power of 2 to 10 KW and a pressure of 5 to 20 [0.50 at 1 lTOrr. ~1.00
Formed with a thickness of μm.
導電膜109は配線構造全体の電気抵抗の低減を目的と
して形成される。The conductive film 109 is formed for the purpose of reducing the electrical resistance of the entire wiring structure.
続いて(d)のごとく既知の技術であるg線あるいはi
線を用いたフォトリソグラフィー法、CBβ3゜SF6
.CFt C(1<、CI(F3.A、r等をエツチ
ングカス、ミリングガ゛スとしたドライエツチング法、
イオンミリング法を用いてチタニウム105゜窒化チタ
ニウムios、導電膜109の不要部分を除去した配線
パターン化し、拡散層104上にチタニウム105.窒
化チタニウム108.it膜109より構成される構造
を有する半導体集積回路装置の金属配線を形成していた
。Next, as shown in (d), the known technology of g-line or i
Photolithography method using wire, CBβ3゜SF6
.. CFt C(1<, CI(F3.Dry etching method using A, r, etc. as etching gas and milling gas,
Using the ion milling method, titanium 105° titanium nitride ios is formed into a wiring pattern by removing unnecessary portions of the conductive film 109, and titanium 105° titanium nitride ios is formed on the diffusion layer 104. Titanium nitride 108. Metal wiring of a semiconductor integrated circuit device having a structure composed of the IT film 109 was formed.
上述した従来の半導体集積回路装置の金属配線構造およ
び形成方法は、以下に示す欠点がある。The conventional metal wiring structure and formation method of a semiconductor integrated circuit device described above has the following drawbacks.
現在入りアメタル材料として使用されている窒化チタニ
ウムは、比抵抗値が数十μΩ・印と、半導体集積回路装
置の配線に使用されているアルミニウム等の主導電材料
と比較して約1桁高く、さらに半導体集積回路装置へ適
用した場合、500℃以上の熱処理では接合リーク電流
が大幅に増大するなど、バリアメタルとして要求される
「低反応性」。Titanium nitride, which is currently used as a metal material, has a specific resistance value of several tens of μΩ, which is about an order of magnitude higher than the main conductive materials such as aluminum used for wiring of semiconductor integrated circuit devices. Furthermore, when applied to semiconductor integrated circuit devices, heat treatment at temperatures above 500°C significantly increases junction leakage current, which is a requirement for barrier metals with "low reactivity."
「低電気抵抗」の両特性を必ずしも同時に満足している
とは言えず、高性能、高信頼性を有する半導体集積回路
装置を得る事が困難である。It cannot be said that both characteristics of "low electrical resistance" are always satisfied at the same time, and it is difficult to obtain a semiconductor integrated circuit device having high performance and high reliability.
さらに耐熱性向上のためには窒化チタニウムの膜厚を厚
くする必要があるがエツチングが困難となるため、生産
工程での歩留り向上がむずかしい。Furthermore, in order to improve heat resistance, it is necessary to increase the thickness of the titanium nitride film, but this makes etching difficult, making it difficult to improve yield in the production process.
本発明の半導体集積回路装置の金属配線構造および形成
方法は、拡散層上、多結晶シリコン上。The metal wiring structure and formation method of a semiconductor integrated circuit device according to the present invention are provided on a diffusion layer and on polycrystalline silicon.
金属ケイ化物上、金属配線上あるいは絶縁膜上に形成さ
れたチタニウム、前記チタニウム上に形成されたチタニ
ウムホウ化物、前記チタニウムホウ化物上に形成された
導電膜より構成される配線を有し、拡散層上、多結晶シ
リコン上、金属ケイ化物上、金属配線上あるいは絶縁膜
上にチタニウムを形成する工程と、前記チタニウム上に
チタニウムホウ化物を形成するかあるいは前記チタニウ
ムの表面層をホウ化する工程と、前記チタニウムホウ化
物上に単層あるいは複数層の導電膜を形成する工程と、
続いて不要部分のみを除去して配線を形成する工程を有
する。It has a wiring made of titanium formed on a metal silicide, a metal wiring, or an insulating film, a titanium boride formed on the titanium, and a conductive film formed on the titanium boride, and the diffusion A step of forming titanium on a layer, polycrystalline silicon, metal silicide, metal wiring, or an insulating film, and a step of forming titanium boride on the titanium or boriding the surface layer of the titanium. and forming a single layer or multiple layers of conductive film on the titanium boride;
Next, there is a step of removing only unnecessary portions and forming wiring.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第1図は本発明の一実施例の縦断面図である。FIG. 1 is a longitudinal sectional view of an embodiment of the present invention.
第1図(a)に示す通り、半導体基板101上にリソグ
ラフィー ドライエツチング、イオン注入。As shown in FIG. 1(a), lithography, dry etching, and ion implantation are performed on a semiconductor substrate 101.
熱拡散、CVD等の既知の手法を用いて、例えばシリコ
ン酸化膜、シリコン窒化膜等より構成される厚さ0.5
〜1.0μmの層間絶縁膜102に開口されたコンタク
トホール103の底部にp型あるいはn型の拡散層10
4が存在する構造を形成する。Using known methods such as thermal diffusion and CVD, the film is made of silicon oxide film, silicon nitride film, etc. with a thickness of 0.5 cm.
A p-type or n-type diffusion layer 10 is formed at the bottom of a contact hole 103 opened in a ~1.0 μm interlayer insulating film 102.
4 forms a structure in which it exists.
続いて(b)に示す通り、既知の技術であるり、C,マ
グネトロンスパッタ法により成膜パワー1〜10KW、
成膜圧力5〜30[1lTOrrの条件で、チタニウム
105を0.05〜0.30μmの厚みで形成し、さら
にBあるいはB F 2をソースとしたイオン注入法に
より、チタニウム105中にホウ素イオン106を30
−90KeV、 I X 1015〜5 X1019個
/d、注入角度O〜数度の条件で打ち込む。Subsequently, as shown in (b), a film was formed using a known technique or by magnetron sputtering with a power of 1 to 10 KW.
Titanium 105 is formed to a thickness of 0.05 to 0.30 μm under a film forming pressure of 5 to 30[1 l TOrr, and boron ions 106 are added to titanium 105 by ion implantation using B or B F 2 as a source. 30
Implantation is performed under the conditions of -90 KeV, I x 1015 to 5 x1019 pieces/d, and an implantation angle of O to several degrees.
チタニウム中にホウ素イオンを注入すると、低温で非平
衡下でのチタニウムのホウ化反応が起こり、チタニウム
105の表面層にTiB2と言う組成を有する高融点で
化学的に極めて安定かつ比抵抗が数μΩ・印と低電気抵
抗を有するチタニウムホウ化物107が形成される。When boron ions are implanted into titanium, a boriding reaction of titanium occurs at low temperatures and in non-equilibrium conditions, and the surface layer of titanium 105 has a composition of TiB2, which has a high melting point, is extremely stable chemically, and has a specific resistance of several μΩ. - A titanium boride 107 having a low electrical resistance is formed.
続いて非酸化性雰囲気中で300℃〜500℃程度の熱
処理を施し、チタニウムホウ化物107を安定化させる
。チタニウムホウ化物107の厚みは注入エネルギー、
注入イオン量、注入角度。Subsequently, a heat treatment is performed at about 300° C. to 500° C. in a non-oxidizing atmosphere to stabilize the titanium boride 107. The thickness of titanium boride 107 depends on the implantation energy,
Injected ion amount and implantation angle.
熱処理条件により異なるため、個々の半導体集積回路装
置にあった最適条件を見い出す必要がある。Since it varies depending on the heat treatment conditions, it is necessary to find the optimal conditions for each individual semiconductor integrated circuit device.
さらに(C)に示す通り、アルミニウムにシリコン、銅
、パラジウム等のE、M、、S、M、の防止・抑制効果
のある添加元素を最大でも5%含有したアルミニウム合
金、銅、金等より構成される低い電気抵抗を有する導電
膜109を既知の技術であるり、C,マクネストロンス
バッタ法により、成膜パワー2〜l0KW、成膜圧力5
〜30mTorrの条件のもと、050〜1.00μm
の厚みでチタニウムホウ化物107上に形成する。Furthermore, as shown in (C), aluminum alloys containing at most 5% of additive elements such as silicon, copper, palladium, etc. that have the effect of preventing and suppressing E, M, S, M, copper, gold, etc. The conductive film 109 having a low electrical resistance is formed using a known technique or by the C. McNetron-Batter method at a film forming power of 2 to 10 KW and a film forming pressure of 5.
050-1.00μm under the condition of ~30mTorr
is formed on titanium boride 107 to a thickness of .
導電膜は配線構造全体の電気抵抗値の低減を主な目的と
して形成される。導電膜が銅、金などの場合、フォトレ
ジスト等の配線形成用マスクを用いた電解メツキ法ある
いは無電解メツキ法と言った手法による形成も可能であ
る。The conductive film is formed primarily to reduce the electrical resistance value of the entire wiring structure. When the conductive film is made of copper, gold, or the like, it can be formed by an electrolytic plating method or an electroless plating method using a mask for wiring formation such as a photoresist.
続いて(d)に示す通り、g線あるいはi線を用いたフ
ォトリソグラフィー、ECβ3.CF、、SF6゜CH
F3.Ar等をエツチングガス、ミリングガスとしたド
ライエツチング法、イオンミリング法と言った既知の技
術を用いて導電膜109.チタニウムホウ化物107.
チタニウム105の不要部分を除去して配線パターン化
する。Subsequently, as shown in (d), photolithography using g-line or i-line, ECβ3. CF,,SF6゜CH
F3. The conductive film 109 is etched using known techniques such as dry etching and ion milling using Ar or the like as an etching gas and a milling gas. Titanium boride 107.
Unnecessary portions of titanium 105 are removed to form a wiring pattern.
前記作業により、拡散層上にチタニウム、チタニウムホ
ウ化物、導電膜の3層より構成される半導体集積回路装
置の金属配線が形成される。Through the above operations, metal wiring of a semiconductor integrated circuit device consisting of three layers of titanium, titanium boride, and a conductive film is formed on the diffusion layer.
本発明の半導体装置の金属配線形成方法はチタニウムの
下層が拡散層に限らず多結晶シリコン。In the method for forming metal wiring in a semiconductor device according to the present invention, the lower layer of titanium is not limited to a diffusion layer but also polycrystalline silicon.
金属ケイ化物、金属配線、絶縁膜の場合でも適用でき、
また導電膜を複数層とし配線を4層構造とする事も可能
である。さらにMOS、 Bipolar。It can also be applied to metal silicides, metal wiring, and insulating films.
It is also possible to use a plurality of layers of conductive films to form a four-layer wiring structure. Furthermore, MOS, Bipolar.
Bi−0MO3、等の半導体集積回路装置の種類にかか
わらず適応可能である事は言うまでもない。Needless to say, it is applicable to any type of semiconductor integrated circuit device such as Bi-0MO3.
次に本発明の他の実施例について図面を参照して説明す
る。第2図は本発明の一実施例の縦断面図である。第2
図(a)に示す通り、半導体基板101上にリソグラフ
ィー、ドライエツチング。Next, other embodiments of the present invention will be described with reference to the drawings. FIG. 2 is a longitudinal sectional view of an embodiment of the present invention. Second
As shown in Figure (a), lithography and dry etching are performed on the semiconductor substrate 101.
イオン注入、熱拡散、CVD等の既知の手法を用いて、
例えばシリコン酸化膜、シリコン窒化膜等より構成され
る厚さ0.5〜1.00μmの層間絶縁膜102に開口
されたコンタクトホール103の底部にp型あるいはn
型の拡散層104が存在する構造を形成する。Using known techniques such as ion implantation, thermal diffusion, and CVD,
For example, p-type or n-type
A structure in which a type diffusion layer 104 exists is formed.
続いて(b)に示す通り、既知の技術であるり、C。Subsequently, as shown in (b), a known technique or C.
マクネストロンスバッタ法により成膜パワー1〜10K
W、成膜圧力5〜30 mTorrの条件でチタニウム
105を0.05〜0.30μmの厚みで形成し、さら
にT i C(! <を反応ソース、Ba5sあるいは
BCffl、をホウ化ガスとした低圧プラズマCVD法
を用いたホウ化処理により、例えば基板温度200〜6
00℃、圧力20〜500rnTorr。Deposition power 1 to 10K by McNetron Batter method
Titanium 105 was formed to a thickness of 0.05 to 0.30 μm under the conditions of W, film formation pressure of 5 to 30 mTorr, and low pressure using TiC (!< as the reaction source and Ba5s or BCffl as the boride gas). By boriding using plasma CVD method, for example, the substrate temperature is 200-600℃.
00°C, pressure 20-500rnTorr.
パワー0.2〜IKWと言った条件でチタニウム105
の表面層のみをホウ化してチタニウムホウ化物106を
0.05〜0.20μmの厚みで形成する。形成される
チタニウムホウ化物の組成2厚み、応力等の物理的性質
はガス比率、RFパワー、基板温度等のプラズマホウ化
条件により異なるため、適用する半導体集積回路装置に
あった条件を設定する。チタニウムホウ化物の中でも特
にTiB2と言う組成を有するものは化学的に極めて安
定かつ高融点で、比抵抗が数μΩ・国と低電気抵抗を有
するため、バリアメタルとして最適の材料と言える。Titanium 105 under conditions such as power 0.2 ~ IKW
Only the surface layer of is borated to form titanium boride 106 with a thickness of 0.05 to 0.20 μm. Since the physical properties such as composition 2 thickness and stress of the titanium boride formed vary depending on plasma boration conditions such as gas ratio, RF power, and substrate temperature, conditions are set that match the semiconductor integrated circuit device to be applied. Among titanium borides, one having the composition TiB2 in particular is chemically extremely stable, has a high melting point, and has a low electrical resistance of several μΩ, so it can be said to be an optimal material for barrier metals.
続いて非酸化性雰囲気中で300℃〜500℃程度の熱
処理を施し、チタニウムホウ化物106を安定化させる
。Subsequently, a heat treatment is performed at about 300° C. to 500° C. in a non-oxidizing atmosphere to stabilize the titanium boride 106.
さらに(C)に示す通り、アルミニウム、アルミニウム
にシリコン、銅、パラジウム等のE、M、。Furthermore, as shown in (C), E, M, etc. of aluminum, silicon, copper, palladium, etc. are added to aluminum.
S 、M、の防止・抑制効果のある添加元素を最大でも
5%含有したアルミ合金、銅あるいは金と言った金属よ
り構成される低い電気抵抗を有する導電膜109を既知
の技術であるり、C,マダネストロンスバッタ法により
、成膜パワー2〜l0KW。A conductive film 109 having low electrical resistance made of a metal such as aluminum alloy, copper, or gold containing at most 5% of an additive element that has the effect of preventing or suppressing S, M, etc. is manufactured using known technology. C. Film-forming power was 2 to 10 KW by Madanestron Batter method.
成膜圧力5〜30mTorrの条件の下、0.50〜1
.00μmの厚みでチタニウムホウ化物106上に形成
する。導電膜は配線構造全体の電気抵抗値の低減を主な
目的として形成する。導電膜は配線構造全体の電気抵抗
値の低減を主な目的として形成される。導電膜が銅、金
などの場合、電解メツキ法あるいは無電解メツキ法と言
った手法による形成も可能である。0.50 to 1 under conditions of film formation pressure of 5 to 30 mTorr
.. 00 μm thick on titanium boride 106. The conductive film is formed with the main purpose of reducing the electrical resistance value of the entire wiring structure. The conductive film is formed primarily to reduce the electrical resistance value of the entire wiring structure. When the conductive film is made of copper, gold, or the like, it can be formed by electrolytic plating or electroless plating.
続いて(d)に示す通り、g線あるいはi線を用いたフ
ォトリソグラフィー技術、BCffl、、CF、。Next, as shown in (d), photolithography techniques using g-line or i-line, BCffl, CF, are applied.
SF6.0HF3.Ar等をエツチングガス、ミリング
ガスとしたドライエツチング技術、イオンミリング技術
を用いて導電膜1o9.チタニウムポウ化物106.チ
タニウム105の不要部分を除去して配線パターン化す
る。前記作業により、拡散層上にチタニウム、チタニウ
ムホウ化物、導電膜の3層より構成される半導体装置の
金属配線が形成される。SF6.0HF3. The conductive film 1o9. Titanium poride 106. Unnecessary portions of titanium 105 are removed to form a wiring pattern. Through the above operations, metal wiring of the semiconductor device is formed on the diffusion layer, which is composed of three layers of titanium, titanium boride, and a conductive film.
以上説明したように本発明の半導体装置の金属配線形成
方法は、拡散層上、多結晶シリコン上。As explained above, the method for forming metal wiring in a semiconductor device according to the present invention is performed on a diffusion layer or polycrystalline silicon.
金属ケイ化物、金属配線あるいは絶縁膜上に、チタニウ
ムホウ化物と下層配線あるいは絶縁膜との間の密着性保
持、コンタクト抵抗の低減、オーミック接合性の確保等
を目的としたチタニウムと、前記チタニウム上に設けら
れたコンタクト部のE、M、耐性、耐熱性の向上を目的
とした、従来バリアメタルとして使用されている窒化チ
タニウムよりも低電気抵抗、高耐熱性を有するチタニウ
ムホウ化物と、前記チタニウムホウ化物上に設けられた
配線抵抗の低減、配線全体のE、M、耐性、S 、M、
耐性の向上を目的とした導電膜より構成される金属配線
を容易に形成できるため、従来の配線と比較して良好な
電気的特性と高い長期信頼性を有する安定した特性の半
導体集積回路装置を得られる効果がある。Titanium is placed on the metal silicide, metal wiring, or insulating film for the purpose of maintaining adhesion between the titanium boride and the underlying wiring or insulating film, reducing contact resistance, ensuring ohmic bonding, etc., and titanium on the titanium. titanium boride, which has lower electrical resistance and higher heat resistance than titanium nitride, which is conventionally used as a barrier metal, and the titanium Reduction of wiring resistance provided on boride, overall wiring E, M, resistance, S, M,
Metal interconnects made of conductive films with the aim of improving durability can be easily formed, making it possible to create semiconductor integrated circuit devices with stable characteristics that have better electrical properties and higher long-term reliability than conventional interconnects. There are benefits to be gained.
本発明の配線と従来の配線の電気的特性を第3図に示す
。FIG. 3 shows the electrical characteristics of the wiring according to the present invention and the conventional wiring.
第1図(a)〜(d)は本発明のl実施例の縦断面図、
第2図(a)〜(d)は本発明の他の実施例の縦断面図
、第3図は本発明と従来の配線の電気特性図、第4図(
a)〜(d)は従来の半導体装置の金属配線形成方法の
縦断面図である。
101・・・・・・半導体基板、102・・・・・・層
間絶縁膜、103・・・・・・コンタクトホール、10
4・・・・・・拡散層、105・・・・・・チタニウム
、106・・・・・・ホウ素イオン、107・・・・・
・チタニウムポウ化物、1o8・旧・・チタニウム窒化
物、109・・川・導電膜。
代理人 弁理士 内 原 晋
第1閉<d)
36θ
#0
5θθ
熱処理温償
(て)
第3図
電気性11与図
π3
鱈4図α)FIGS. 1(a) to 1(d) are longitudinal sectional views of an embodiment of the present invention;
2(a) to 2(d) are longitudinal cross-sectional views of other embodiments of the present invention, FIG. 3 is electrical characteristic diagrams of wiring of the present invention and conventional wiring, and FIG. 4 (
a) to (d) are vertical cross-sectional views of a conventional method for forming metal wiring in a semiconductor device. 101...Semiconductor substrate, 102...Interlayer insulating film, 103...Contact hole, 10
4...Diffusion layer, 105...Titanium, 106...Boron ion, 107...
・Titanium poride, 1o8・Old・・Titanium nitride, 109・・River・Conductive film. Agent Patent Attorney Susumu Uchihara 1st closing<d) 36θ #0 5θθ Heat treatment temperature compensation (te) Figure 3 Electricity 11 Y Figure π3 Cod Figure 4 α)
Claims (1)
リコン上、金属ケイ化物上、金属配線上あるいは絶縁膜
上に形成されたチタニウム、前記チタニウム上に形成さ
れたチタニウムホウ化物、前記チタニウムホウ化物上に
形成された単層あるいは複数層の導電膜より構成される
配線を有する事を特徴とする半導体集積回路装置の金属
配線構造。 2、前記半導体集積回路装置において、拡散層上、多結
晶シリコン上、金属ケイ化物上、金属配線上あるいは絶
縁膜上にチタニウムを形成する工程と、前記チタニウム
上にチタニウムホウ化物を形成する工程と、前記チタニ
ウムホウ化物上に単層あるいは複数層の導電膜を形成す
る工程と、不要部分のみを除去して配線を形成する工程
を有する事を特徴とする半導体集積回路装置の金属配線
形成方法。[Claims] 1. In a semiconductor integrated circuit device, titanium formed on a diffusion layer, polycrystalline silicon, metal silicide, metal wiring, or an insulating film, titanium boron formed on the titanium. 1. A metal wiring structure for a semiconductor integrated circuit device, characterized in that the metal wiring structure has a wiring made of a single layer or multiple layers of conductive film formed on the titanium boride. 2. In the semiconductor integrated circuit device, a step of forming titanium on the diffusion layer, polycrystalline silicon, metal silicide, metal wiring, or insulating film, and a step of forming titanium boride on the titanium. A method for forming metal wiring for a semiconductor integrated circuit device, comprising the steps of: forming a single layer or multiple layers of conductive film on the titanium boride; and forming wiring by removing only unnecessary portions.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11816590A JP3186053B2 (en) | 1990-05-08 | 1990-05-08 | Method for forming metal wiring structure of semiconductor integrated circuit device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11816590A JP3186053B2 (en) | 1990-05-08 | 1990-05-08 | Method for forming metal wiring structure of semiconductor integrated circuit device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH0414874A true JPH0414874A (en) | 1992-01-20 |
JP3186053B2 JP3186053B2 (en) | 2001-07-11 |
Family
ID=14729722
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11816590A Expired - Fee Related JP3186053B2 (en) | 1990-05-08 | 1990-05-08 | Method for forming metal wiring structure of semiconductor integrated circuit device |
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Country | Link |
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JP (1) | JP3186053B2 (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5528081A (en) * | 1993-06-25 | 1996-06-18 | Hall; John H. | High temperature refractory metal contact in silicon integrated circuits |
US5745990A (en) * | 1995-06-06 | 1998-05-05 | Vlsi Technology, Inc. | Titanium boride and titanium silicide contact barrier formation for integrated circuits |
US6380064B1 (en) | 1996-09-27 | 2002-04-30 | Sanyo Electric Co., Ltd. | Semiconductor devices and process for producing the same |
US6482737B2 (en) | 2000-05-11 | 2002-11-19 | Nec Corporation | Fabrication method of implanting silicon-ions into the silicon substrate |
-
1990
- 1990-05-08 JP JP11816590A patent/JP3186053B2/en not_active Expired - Fee Related
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5528081A (en) * | 1993-06-25 | 1996-06-18 | Hall; John H. | High temperature refractory metal contact in silicon integrated circuits |
US5745990A (en) * | 1995-06-06 | 1998-05-05 | Vlsi Technology, Inc. | Titanium boride and titanium silicide contact barrier formation for integrated circuits |
US6380064B1 (en) | 1996-09-27 | 2002-04-30 | Sanyo Electric Co., Ltd. | Semiconductor devices and process for producing the same |
US6482737B2 (en) | 2000-05-11 | 2002-11-19 | Nec Corporation | Fabrication method of implanting silicon-ions into the silicon substrate |
Also Published As
Publication number | Publication date |
---|---|
JP3186053B2 (en) | 2001-07-11 |
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