JPH04148555A - Lead frame and semiconductor device using it - Google Patents
Lead frame and semiconductor device using itInfo
- Publication number
- JPH04148555A JPH04148555A JP27402790A JP27402790A JPH04148555A JP H04148555 A JPH04148555 A JP H04148555A JP 27402790 A JP27402790 A JP 27402790A JP 27402790 A JP27402790 A JP 27402790A JP H04148555 A JPH04148555 A JP H04148555A
- Authority
- JP
- Japan
- Prior art keywords
- plating film
- bismuth
- lead frame
- lead
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 42
- 238000007747 plating Methods 0.000 claims abstract description 30
- 229910052797 bismuth Inorganic materials 0.000 claims abstract description 26
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 claims abstract description 26
- 239000011347 resin Substances 0.000 claims abstract description 9
- 229920005989 resin Polymers 0.000 claims abstract description 9
- 238000007789 sealing Methods 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims description 18
- 238000000034 method Methods 0.000 abstract description 23
- 230000008018 melting Effects 0.000 abstract description 13
- 238000002844 melting Methods 0.000 abstract description 13
- 229910000679 solder Inorganic materials 0.000 description 33
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 7
- 229910045601 alloy Inorganic materials 0.000 description 5
- 239000000956 alloy Substances 0.000 description 5
- 238000005275 alloying Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 238000005476 soldering Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000007598 dipping method Methods 0.000 description 2
- 239000000155 melt Substances 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 229910001174 tin-lead alloy Inorganic materials 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 1
- 229910052793 cadmium Inorganic materials 0.000 description 1
- BDOSMKKIYDKNTQ-UHFFFAOYSA-N cadmium atom Chemical compound [Cd] BDOSMKKIYDKNTQ-UHFFFAOYSA-N 0.000 description 1
- 230000008094 contradictory effect Effects 0.000 description 1
- 239000006023 eutectic alloy Substances 0.000 description 1
- 230000005496 eutectics Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 231100000989 no adverse effect Toxicity 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
- 239000011701 zinc Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明はリードフレームおよびこれを用いた半導体装置
に関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a lead frame and a semiconductor device using the lead frame.
（従来の技術）
半導体装置は基板へのはんだ付けに際し、半導体装置の
アウターリードにあらかじめ形成したはんだ層と、基板
の接合部位にあらかじめ形成したはんだ層とを溶融して
接合するようにしでいる。(Prior Art) When a semiconductor device is soldered to a substrate, a solder layer formed in advance on the outer lead of the semiconductor device and a solder layer formed in advance at the bonding site of the substrate are melted and bonded.
上記のアウターリードへのはんだ層の形成は、半導体チ
ップの接合工程、樹脂封止工程等の半導体装置へのアッ
センブリ工程を経た最終段階で行われるのが通常である
が、近年ではリードフレームの段階で形成することも試
みられている。The formation of the solder layer on the outer leads described above is normally performed at the final stage after the semiconductor device assembly process, such as the semiconductor chip bonding process and the resin sealing process, but in recent years, it has been performed at the lead frame stage. Attempts have also been made to form
このようにリードフレームの段階でアウターリードには
んだめっきやはんだ浸漬によりはんだ層を形成しておけ
ば、半導体装置の組立以後におけるはんだめっきのウェ
ットプロセスが省け、また、はんだ浸漬時の熱的ショッ
クが避けられるから、半導体チップ等への悪影響がなく
、信転性の高い半導体装置を提供できる。If a solder layer is formed on the outer leads by solder plating or solder dipping at the lead frame stage in this way, the wet solder plating process after the semiconductor device is assembled can be omitted, and thermal shock during solder dipping can be avoided. Since this can be avoided, there is no adverse effect on semiconductor chips, etc., and a semiconductor device with high reliability can be provided.
（発明が解決しようとするする課Ｂ）
しかしながら、上記のようにリードフレームの段階では
んだ層を形成するのは次のような問題点がある。(Problem B to be Solved by the Invention) However, forming the solder layer at the lead frame stage as described above has the following problems.
すなわち、前記アッセンブリ工程での半導体チップの接
合工程、樹脂封止工程ではかなりの高温がリードフレー
ムに加わる。そのためアウターリードに形成するはんだ
層は上記の高温に耐えうる高い融点を有するものが望ま
れる。現行では、融点の高い、錫対鉛が９：１の９−１
はんだが通常用いられている。That is, considerable high temperatures are applied to the lead frame during the semiconductor chip bonding process and resin sealing process in the assembly process. Therefore, it is desirable that the solder layer formed on the outer lead has a high melting point that can withstand the above-mentioned high temperatures. Currently, 9-1, which has a high melting point and a ratio of tin to lead of 9:1, is used.
Solder is commonly used.
しかし一方、基板への実装工程では、半導体チップの信
転性、作業性等の点から、低温でのはんだ付けが行える
よう要望される。このため基板にあらかじめ形成される
はんだ層は最も融点の低い６−４はんだが通常用いられ
ている。On the other hand, however, in the mounting process on the substrate, it is desired to be able to perform soldering at a low temperature from the viewpoint of reliability of semiconductor chips, workability, etc. For this reason, 6-4 solder, which has the lowest melting point, is usually used as the solder layer previously formed on the substrate.
上記のようにアウターリードのはんだ層が９−１はんだ
で、基板のはんだ層が６−４はんだであると、はんだ付
けの際の温度は基板のはんだ層が流れ出さない温度であ
る１５０℃前後となるが、この温度ではアウターリード
の９−１はんだのはんだ層の粘度が高く、良好なはんだ
付けが行えない問題点がある。As mentioned above, if the solder layer of the outer lead is 9-1 solder and the solder layer of the board is 6-4 solder, the temperature during soldering is around 150°C, which is the temperature at which the solder layer of the board does not flow out. However, at this temperature, the viscosity of the 9-1 solder layer of the outer lead is high, and there is a problem that good soldering cannot be performed.
またアウターリードのはんだ層が９−１はんだであって
も、なお上記のアッセンブリ工程での耐熱性は充分でな
く、アッセンブリ工程で温度が多少とも変動するとはん
だ層が溶けてしまうという本質的な問題点もある。Furthermore, even if the solder layer of the outer lead is 9-1 solder, it still does not have sufficient heat resistance during the above assembly process, and there is an inherent problem that the solder layer will melt if the temperature fluctuates even slightly during the assembly process. There are also points.
このようにアウターリードのはんだ層はアッセンブリ工
程での高温に耐えられなければならず、−大基板への実
装時には低温で融解してほしいという相反する要求があ
り、現状では両者を満足するリードフレームはない。In this way, there are contradictory demands for the solder layer of the outer lead to withstand the high temperatures during the assembly process, and for it to be melted at a low temperature when mounted on a large board.Currently, there are lead frames that satisfy both requirements. There isn't.
本発明は上記事情に鑑みてなされたものでその目的とす
るところは、アッセンブリ工程での高温に耐えることが
でき、−大基板へ低温で接合しうるリードフレームおよ
びこれを用いた半導体装置を提供するにある。The present invention has been made in view of the above circumstances, and its purpose is to provide a lead frame that can withstand high temperatures during assembly processes and that can be bonded to a large substrate at low temperatures, and a semiconductor device using the same. There is something to do.
（課題を解決するための手段）
上記目的による本発明に係るリードフレームでは、樹脂
封止型半導体装置に用いるリードフレームにおいて、少
なくともアウターリードの基板への接合面にビスマスめ
っき皮膜を形成したことを特徴としている。(Means for Solving the Problems) In the lead frame according to the present invention for the above-mentioned purpose, a bismuth plating film is formed at least on the bonding surface of the outer lead to the substrate in the lead frame used for a resin-sealed semiconductor device. It is a feature.
また、本発明に係る半導体装置では、リードフレームの
ダイパッド上に半導体チップが接合され半導体チップと
インナーリードとが電気的に接続され、半導体チップが
封止樹脂により封止された半導体ｓｘにおいて、前記リ
ードフレームの少なくともアウターリードの基板への接
合面にリードフレームの段階でビスマスめっき皮膜を形
成したことを特徴としている。Further, in the semiconductor device according to the present invention, in the semiconductor sx, the semiconductor chip is bonded onto the die pad of the lead frame, the semiconductor chip and the inner lead are electrically connected, and the semiconductor chip is sealed with a sealing resin. The lead frame is characterized in that a bismuth plating film is formed on at least the bonding surface of the outer lead to the substrate at the lead frame stage.
（作用）
以上のように本発明によれば、リードフレームの段階で
は少なくともそのアウターリードにビスマスめっき皮膜
を形成しているので、アウターリードの保護膜として作
用すると共に、リードフレームへの半導体チップの接合
工程、樹脂封止工程等での半導体装置アッセンブリ工程
で熱が加わっても、ビスマスは融点が２７１℃と高いの
で溶けてしまうことがなく、−男手導体装置を基板に接
合する際、基板の接合部にはんだ層等を形成しておくこ
とにより、ビスマスめっき皮膜ははんだ層等と当接して
、当接部から低融点の合金化が進行し、もって低温度で
半導体装置の基板への接合が行えるという著効を奏する
。(Function) As described above, according to the present invention, since the bismuth plating film is formed on at least the outer leads at the lead frame stage, it acts as a protective film for the outer leads and also protects the semiconductor chip from being attached to the lead frame. Bismuth has a high melting point of 271°C, so even if heat is applied during the semiconductor device assembly process such as the bonding process and resin sealing process, it will not melt. By forming a solder layer, etc. on the bonding area, the bismuth plating film comes into contact with the solder layer, etc., and low melting point alloying progresses from the abutting area, which allows it to be bonded to the substrate of the semiconductor device at low temperatures. It has the remarkable effect of being able to perform bonding.
（実施例）
以下では本発明の好適な実施例を添付図面を用いて詳細
に説明する。(Embodiments) Hereinafter, preferred embodiments of the present invention will be described in detail using the accompanying drawings.
第１図はリードフレーム１０の概略図を示す。FIG. 1 shows a schematic diagram of a lead frame 10.
図において、１２はアウターリード、１４はインナーリ
ード、１６はダイパッド、１８はサポートバー、２０は
ダムバー、２２．２２はレール部を示す。In the figure, 12 is an outer lead, 14 is an inner lead, 16 is a die pad, 18 is a support bar, 20 is a dam bar, and 22.22 is a rail portion.
本発明では、リードフレーム１０の少なくともアウター
リード１２上にビスマスめっき皮膜２４（第２図）を形
成する点に特徴がある。The present invention is characterized in that a bismuth plating film 24 (FIG. 2) is formed on at least the outer leads 12 of the lead frame 10.
なおビスマスめっき皮膜２４はリードフレーム１０の全
面に形成してもよいし、アウターリード１２の全面ある
いは基板への接合面となる片面にのみ形成するようにし
てもよい。The bismuth plating film 24 may be formed on the entire surface of the lead frame 10, or may be formed on the entire surface of the outer lead 12 or only on one surface that is to be bonded to the substrate.
ビスマスめっき皮膜２４の厚さは特に限定されるもので
はないが、基板との必要な接合強度が得られるだけの厚
さがあればよい。The thickness of the bismuth plating film 24 is not particularly limited, as long as it is thick enough to obtain the necessary bonding strength with the substrate.
ダイパッド１６、インナーリード１４上には半導体チッ
プ接合用、ワイヤボンディング用の金めつき皮膜あるい
は銀めっき皮膜を形成する。A gold plating film or a silver plating film for semiconductor chip bonding and wire bonding is formed on the die pad 16 and inner leads 14.
第２図は上記リードフレーム１０を用いてアッセンブリ
した半導体装置２６を示し、ダイパッド１６上に半導体
チップ２８が接合され、半導体チップ２８とインナーリ
ード１４がワイヤで接続されてのち、半導体チップ２８
が封止樹脂３０で封止されて成る。上記ではアウターリ
ード１２の基板３２への接合面にのみビスマスめっき皮
膜２４を形成した例を示す。FIG. 2 shows a semiconductor device 26 assembled using the lead frame 10. A semiconductor chip 28 is bonded onto the die pad 16, and the semiconductor chip 28 and the inner leads 14 are connected with wires.
is sealed with a sealing resin 30. In the above example, the bismuth plating film 24 is formed only on the bonding surface of the outer lead 12 to the substrate 32.
ビスマスの融点は２７１℃であるから、テラセンプリ工
程での上記半導体チップの接合工程、樹脂封止工程で加
わる高温に充分耐えることができる。Since the melting point of bismuth is 271° C., it can sufficiently withstand the high temperatures applied during the semiconductor chip bonding process and resin sealing process in the terra assembly process.
一方、基板３２上の半導体装置の接合すべき個所には、
あらかじめはんだ層、錫層、鉛層などの接合層３４を形
成しておく。On the other hand, at the location where the semiconductor device on the substrate 32 is to be bonded,
A bonding layer 34 such as a solder layer, a tin layer, a lead layer, etc. is formed in advance.
半導体装置の実装の際、半導体装置２６のアウターリー
ド１２を接合層３４に当接させて加温すると、アウター
リード１２のビスマスめっき皮膜２４と接合層３４との
当接面で両金属が互いに拡散して合金化が起こる。この
合金化は接合層３４の金属の種類とその組成にもよるが
、１５０℃以下の低温のままで合金化が進行し、ビスマ
スめっき皮膜２４と接合層３４の境界部分が順次融解し
、アウターリードの接合が行える。When mounting a semiconductor device, when the outer lead 12 of the semiconductor device 26 is brought into contact with the bonding layer 34 and heated, both metals diffuse into each other at the contact surface between the bismuth plating film 24 of the outer lead 12 and the bonding layer 34. alloying occurs. Although this alloying depends on the type and composition of the metal in the bonding layer 34, the alloying progresses at a low temperature of 150° C. or lower, and the boundary between the bismuth plating film 24 and the bonding layer 34 melts sequentially, and the outer Leads can be joined.
ビスマスは錫、鉛、はんだと低融点の共晶あるいは非共
晶組成の合金を形成する。この低融点の合金を形成する
場合のビスマスの比率は５０−ｔ％前後である。Bismuth forms a low melting point eutectic or non-eutectic alloy with tin, lead, and solder. The proportion of bismuth in forming this low melting point alloy is around 50-t%.
上記のようにアウターリード１２上に形成したビスマス
めっき皮膜２４を接合層３４に当接させるとき、当接面
ではビスマスの比率が５０％となり、上記低融点の合金
を形成しやすくなっている。When the bismuth plating film 24 formed on the outer lead 12 is brought into contact with the bonding layer 34 as described above, the ratio of bismuth is 50% on the contact surface, making it easier to form the above-mentioned low melting point alloy.
こうして当接部を加熱すると低融点の合金化が次々と進
み、低温度での接合が可能となった。When the abutting portion is heated in this way, low melting point alloying progresses one after another, making it possible to join at low temperatures.
上記接合層３４の金属は、錫、鉛の単体の他、種々の組
成の錫−鉛合金（はんだ）が有効である。As the metal of the bonding layer 34, in addition to tin and lead alone, tin-lead alloys (solder) of various compositions are effective.
またこの錫−鉛合金にカドミウム、インジウム、亜鉛等
を含ませた多元合金であってもよい。Alternatively, it may be a multi-component alloy in which cadmium, indium, zinc, etc. are included in this tin-lead alloy.
なお、上記実施例ではアうターリード１２にビスマスめ
っき皮膜２４を形成したが、ビスマスめっき皮膜２４の
みでは基板３２への接合に量が充分でないときは、半導
体装置２６に組み立てたのちに、アウターリードをはん
だ浴あるいは錫浴に浸漬してビスマスめっき皮膜２４上
にはんだ皮膜あるいは錫皮膜をさらに肉盛りするように
してもよい。この場合のビスマスめっき皮膜とはんだ皮
膜あるいは錫皮膜とは金属学的な合金ではないが、やは
り１５０℃以下で溶融し、基板３２の前記接合層３４と
の間でやはり低温度での接合が可能となる。In the above embodiment, the bismuth plating film 24 was formed on the outer lead 12, but if the amount of bismuth plating film 24 alone is not sufficient for bonding to the substrate 32, the outer lead may be coated after the semiconductor device 26 is assembled. A solder film or a tin film may be further built up on the bismuth plating film 24 by immersing it in a solder bath or a tin bath. Although the bismuth plating film, solder film, or tin film in this case is not a metallurgical alloy, it still melts at 150° C. or lower, and can be bonded to the bonding layer 34 of the substrate 32 at a low temperature. becomes.
以上、本発明の好適な実施例について種々述べてきたが
、本発明は上述の実施例に限定されるのではな〈発明の
精神を逸脱しない範囲で多くの改変を施し得るのはもち
ろんである。Although various preferred embodiments of the present invention have been described above, the present invention is not limited to the above-mentioned embodiments (it goes without saying that many modifications can be made without departing from the spirit of the invention). .
（発明の効果）
以上のように本発明によれば、リードフレームの段階で
は少なくともそのアウターリードにビスマスめっき皮膜
を形成しているので、アウターリードの保護膜として作
用すると共に、リードフレームへの半導体チップの接合
工程、樹脂封止工程等での半導体装置アッセンブリ工程
で熱が加わっても、ビスマスは融点が２７１℃と高いの
で溶けてしまうことがなく、−男手導体装置を基板に接
合する際、基板の接合部にはんだ層等を形成しておくこ
とにより、ビスマスめっき皮膜ははんだ層等と当接して
、当接部から低融点の合金化が進行し、もって低温度で
半導体装置の基板への接合が行えるという著効を奏する
。(Effects of the Invention) As described above, according to the present invention, since the bismuth plating film is formed on at least the outer leads at the lead frame stage, it acts as a protective film for the outer leads and also serves as a semiconductor layer for the lead frame. Bismuth has a high melting point of 271°C, so it will not melt even when heat is applied during semiconductor device assembly processes such as chip bonding processes and resin sealing processes. By forming a solder layer or the like on the bonding area of the substrate, the bismuth plating film comes into contact with the solder layer, etc., and a low melting point alloy progresses from the abutting area, resulting in the formation of a semiconductor device substrate at a low temperature. It has the remarkable effect of being able to join to.
第１図はリードフレームの概略を示す説明図、第２図は
半導体装置の断面図を示す。
１０・・・リードフレーム、 １２・・・アウターリ
ード、 １４・・・インナーリード、・ダイパッド、
・ビスマスめ
つき皮膜、
・接合層。FIG. 1 is an explanatory diagram showing an outline of a lead frame, and FIG. 2 is a sectional view of a semiconductor device. 10... Lead frame, 12... Outer lead, 14... Inner lead, - Die pad, - Bismuth plating film, - Bonding layer.
Claims (1)
いて、 少なくともアウターリードの基板への接合面にビスマス
めっき皮膜を形成したことを特徴とするリードフレーム
。 ２、リードフレームのダイパッド上に半導体チップが接
合され、半導体チップとインナーリードとが電気的に接
続され、半導体チップが封止樹脂により封止された半導
体装置において、 前記リードフレームの少なくともアウターリードの基板
への接合面にリードフレームの段階でビスマスめっき皮
膜を形成したことを特徴とする半導体装置。[Claims] 1. A lead frame for use in a resin-sealed semiconductor device, characterized in that a bismuth plating film is formed on at least the bonding surface of the outer lead to the substrate. 2. In a semiconductor device in which a semiconductor chip is bonded onto a die pad of a lead frame, the semiconductor chip and inner leads are electrically connected, and the semiconductor chip is sealed with a sealing resin, at least one of the outer leads of the lead frame A semiconductor device characterized in that a bismuth plating film is formed on a surface to be bonded to a substrate at the lead frame stage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2274027A JP2966079B2 (en) | 1990-10-11 | 1990-10-11 | Lead frame, semiconductor device using the same, and method of mounting semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2274027A JP2966079B2 (en) | 1990-10-11 | 1990-10-11 | Lead frame, semiconductor device using the same, and method of mounting semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04148555A true JPH04148555A (en) | 1992-05-21 |
| JP2966079B2 JP2966079B2 (en) | 1999-10-25 |
Family
ID=17535942
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2274027A Expired - Fee Related JP2966079B2 (en) | 1990-10-11 | 1990-10-11 | Lead frame, semiconductor device using the same, and method of mounting semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2966079B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04297059A (en) * | 1991-03-26 | 1992-10-21 | Aiwa Co Ltd | Electronic parts for surface mounting |
| WO1997000753A1 (en) * | 1995-06-20 | 1997-01-09 | Matsushita Electric Industrial Co., Ltd. | Solder, and soldered electronic component and electronic circuit board |
| JP2006219736A (en) * | 2005-02-14 | 2006-08-24 | Toyo Kohan Co Ltd | Surface-treated al sheet |
-
1990
- 1990-10-11 JP JP2274027A patent/JP2966079B2/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04297059A (en) * | 1991-03-26 | 1992-10-21 | Aiwa Co Ltd | Electronic parts for surface mounting |
| WO1997000753A1 (en) * | 1995-06-20 | 1997-01-09 | Matsushita Electric Industrial Co., Ltd. | Solder, and soldered electronic component and electronic circuit board |
| US5962133A (en) * | 1995-06-20 | 1999-10-05 | Matsushita Electric Industrial Co., Ltd. | Solder, electronic component mounted by soldering, and electronic circuit board |
| CN1080616C (en) * | 1995-06-20 | 2002-03-13 | 松下电器产业株式会社 | Solder and soldered electronic component and electronic circuit board |
| JP2006219736A (en) * | 2005-02-14 | 2006-08-24 | Toyo Kohan Co Ltd | Surface-treated al sheet |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2966079B2 (en) | 1999-10-25 |
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