JPH0412028B2 - - Google Patents

Info

Publication number
JPH0412028B2
JPH0412028B2 JP57500908A JP50090882A JPH0412028B2 JP H0412028 B2 JPH0412028 B2 JP H0412028B2 JP 57500908 A JP57500908 A JP 57500908A JP 50090882 A JP50090882 A JP 50090882A JP H0412028 B2 JPH0412028 B2 JP H0412028B2
Authority
JP
Japan
Prior art keywords
die
package
copper
semiconductor
metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP57500908A
Other languages
Japanese (ja)
Other versions
JPS58500463A (en
Inventor
Denisu Aaru Orusen
Keisu Jii Supanjaa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of JPS58500463A publication Critical patent/JPS58500463A/en
Publication of JPH0412028B2 publication Critical patent/JPH0412028B2/ja
Granted legal-status Critical Current

Links

Classifications

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    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

A semiconductor device (10) including a metallurgically compatible unplated package. The package includes a plateless copper alloy die mount area (14) to which a semiconductor die (12) is attached. The semiconductor die (12) is metallized on its mounting surface (40) to provide electrical contact. A metallic solder (38) which is compatible with both the copper alloy and the die metallization joins the die (12) to the die mount area (14). The package further includes a plateless copper alloy lead portion (16) which is physically joined (42) to the die mount area (14). The top surface of the semiconductor die (12) is provided with a patterned metallization (24, 26) making electrical contact to select the portions of the die. Electrical contact is made between the top surface die metallization (24, 26) and the lead portion (16) of the package by ultrasonically bonded copper ribbon (28). The die (12) and interconnecting ribbon (28) is then enclosed by an epoxy encapsulant (18) or by a welded metal cover (58).

Description

請求の範囲 １ メツキのしていない銅合金ダイ取付部分； 第１および第２表面を有する半導体ダイ； チタン層、ニツケル層および銀層の順次的層か
ら構成され、前記第１表面上にあつて、前記チタ
ン層が前記第１表面への電気的接触を行なう第１
金属層； 前記第１金属層および前記銅合金ダイ取付部分
との冶金学的相和性を有し、前記半導体ダイを前
記ダイ取付部分に接合する錫、銀、アンチモンは
んだ； 前記第２表面上でパターンを形成し、前記第２
表面の選択した部分への電気的接触を行なう第２
金属層； 前記ダイ取付部分に固定された銅合金導線コネ
クタリード部分； 前記第２金属層と前記導線コネクタリード部分
との間に結合されそれらを電気的に相互接続させ
る銅接続手段； 前記半導体ダイ、前記銅接続手段、前記ダイ取
付部分の一部、および前記導線コネクタリード部
分の一部を包囲するための手段； から成ることを特徴とする半導体デバイス。Claim 1: An unplated copper alloy die attach portion; a semiconductor die having first and second surfaces; comprising sequential layers of a titanium layer, a nickel layer and a silver layer, on said first surface; , wherein the titanium layer makes electrical contact to the first surface.
a metal layer; a tin, silver, antimony solder having metallurgical compatibility with the first metal layer and the copper alloy die attach portion and joining the semiconductor die to the die attach portion; on the second surface; form a pattern with the second
a second making electrical contact to a selected portion of the surface;
a metal layer; a copper alloy conductor connector lead portion secured to the die attach portion; a copper connection means coupled between the second metal layer and the conductor connector lead portion to electrically interconnect them; , means for enclosing the copper connection means, a portion of the die attach portion, and a portion of the conductor connector lead portion.

２ 前記銅合金ダイ取付部分が、金属ベースに固
着されたボンデイング台から成る、ところの特許
請求の範囲第１項記載の半導体デバイス。2. The semiconductor device according to claim 1, wherein the copper alloy die attachment portion comprises a bonding stand fixed to a metal base.

３ 前記第２金属層は、チタン層、ニツケル層お
よび銅層の順次的層から構成され、前記チタン層
が前記第２表面への電気的接触を行なう、ところ
の特許請求の範囲第１項記載の半導体デバイス。3. The second metal layer is comprised of successive layers of titanium, nickel and copper, the titanium layer making electrical contact to the second surface. semiconductor devices.

発明の背景 本発明は、一般的には半導体デバイス構造に関
するものであり、更に具体的に言うとめつきのし
てない銅合金パツケージに実装され結合された半
導体ダイを含む、めつきのしてないパツケージを
含む半導体デバイスに関する。BACKGROUND OF THE INVENTION The present invention relates generally to semiconductor device structures, and more particularly to unplated packages containing semiconductor die mounted and bonded to unplated copper alloy packages. It relates to a semiconductor device including.

半導体デバイスは、代表的な場合には半導体ダ
イとそのダイのためのパツケージ又はハウジング
を含む。パツケージはダイ実装部分と導線（リー
ド）部分とを含む。拡散領域、接合面
（junction）などを含むダイの頂部表面及び底部
表面はいづれも金属被覆されている。底部金属被
覆をパツケージのダイ実装部分に結合するのには
はんだが用いられる。ワイヤ導線は頂部金属被覆
及びパツケージ導線部分と結合し、それらを相互
接続している。ダイ及び相互接続導線はついでパ
ツケージ内に封じこめられる。囲いは、ダイとダ
イ実装及び導線部分の１部の周囲にモールドされ
たプラスチツク製カプセル封入（encapsulation）
又は実装部分に溶接されダイ上方に広がつている
金属製覆いを具える。 A semiconductor device typically includes a semiconductor die and a package or housing for the die. The package includes a die mounting portion and a conductor (lead) portion. Both the top and bottom surfaces of the die, including the diffusion regions, junctions, etc., are metallized. Solder is used to bond the bottom metallization to the die mounting portion of the package. Wire conductors join the top metallization and the package conductor portions and interconnect them. The die and interconnect leads are then encapsulated within the package. The enclosure is a plastic encapsulation molded around the die and a portion of the die mounting and conductor sections.
or a metal shroud welded to the mounting portion and extending over the die.

パツケージのダイ実装部分は機械的支持と電気
的接触を与え、熱だめ（ヒートシンク）（heat
sink）として機能する。ダイは、通常は軟ろう、
硬ろう又は導電性エポキシを用いてダイ実装部分
に接着されている。これらの実装材料の各々は特
有の利点と欠点をもつている。例えば、鉛主成分
合金又は錫主成分合金である軟ろうは安価ではあ
るが、硬ろうに比べると熱疲労が起きやすく、電
気抵抗、熱抵抗が高い。硬ろうは金主成分合金で
あり、すぐれた熱、電気および機械的特性をもつ
た信頼性の高い結合を与えるが、金主成分硬ろう
は非常に高価である。導電性エポキシは軟ろうと
同様に比較的安価であるが、硬ろうに比べるとそ
の結合状態はあまり望ましいものではなく、貴金
属充填剤（precious metal fillers）をしばしば
含んでいる。 The die mounting portion of the package provides mechanical support and electrical contact, and serves as a heat sink.
functions as a sink). The die is usually soft wax,
It is bonded to the die mounting part using hard solder or conductive epoxy. Each of these packaging materials has unique advantages and disadvantages. For example, soft solder which is a lead-based alloy or a tin-based alloy is inexpensive, but it is more susceptible to thermal fatigue and has higher electrical resistance and thermal resistance than hard solder. Hard solders are gold-based alloys that provide reliable bonds with excellent thermal, electrical, and mechanical properties, but gold-based solders are very expensive. Conductive epoxies, like soft solders, are relatively inexpensive, but their bonding properties are less desirable than hard solders, and they often contain precious metal fillers.

半導体ダイの背面は、結合可能な表面とするた
めに金属被覆が行われている。結合にはんだを用
いる場合には、背面金属被覆は選択したはんだと
相和性（compatible）がなければならない。同
様にそのはんだはダイ実装部分の金属と相和性が
なければならない。即ち、背面金属、はんだおよ
びダイ実装金属はすべて冶金学的に相和性がなけ
ればならない。冶金学的に相和性があるというこ
とは、そのはんだが湿潤しはんだが接触する金属
表面に強力な結合部を形成することはできるが、
その結合部に望ましくない金属間化合物は形成し
ないことを意味する。これとは対照的に、金およ
び錫は破壊さえやすい金属間化合物を形成する可
能性があり、従つて信頼性の低い結合部をつくる
ものと思われる。 The back side of the semiconductor die is metallized to provide a bondable surface. If solder is used for bonding, the back metallization must be compatible with the selected solder. Similarly, the solder must be compatible with the metal of the die mounting portion. That is, the backside metal, solder, and die-mount metal must all be metallurgically compatible. Metallurgically compatible means that the solder can wet and form a strong bond with the metal surfaces it contacts;
This means that no undesirable intermetallic compounds are formed at the bond. In contrast, gold and tin can form intermetallic compounds that are susceptible to fracture and therefore appear to create less reliable bonds.

相和性（compatibility）が求められる結果、
代表的な場合には金属被覆（clad）又はめつきを
したダイ実装領域が用いられるようになる。ダイ
実装領域の下にある材料は、その熱特性、電気的
特性及び機械的特性によつて選択される。金属被
覆（cladding）又はめつきは必要とされる冶金学
的相和性を与える。選択されたはんだ系に応じ
て、ダイ実装領域はその上が材料、通常はニツケ
ルか金の薄い層によつて被覆される。この結果、
材料自体の費用とともにめつき又は金属被覆作業
の費用がデバイスの総費用に加えられることにな
る。 As a result of the need for compatibility,
Typically, metal clad or plated die mounting areas will be used. The material underlying the die mounting area is selected for its thermal, electrical, and mechanical properties. Metal cladding or plating provides the required metallurgical compatibility. Depending on the solder system chosen, the die mounting area is covered therewith by a thin layer of material, usually nickel or gold. As a result,
The cost of the plating or metallization operation along with the cost of the material itself will add to the total cost of the device.

半導体ダイの前表面は、パターン配線が形成さ
れた（patterned）金属層によつてメタライズさ
れ、この金属層により例えばバイポーラトランジ
スタの場合にはトランジスタのベース及びエミツ
タ電極に対する電気的接触が可能になる。このパ
ターン形成金属配線は、細いワイヤ（代表的の場
合には直径25−500ミクロン）によつて半導体パ
ツケージの導線（リード）部分に接続されてお
り、これらの細いワイヤは表面金属配線とパツケ
ージ導線との間に結合されている。これらのワイ
ヤは、通常はアルミニウム又は金であり、上部表
面金属配線はアルミニウム又は多数の別の多層金
属系であり、パツケージ導線は、ニツケル又は金
でめつきされている。導線めつき又は金属被覆
は、アルミニウム又は金のワイヤとパツケージ導
線の剛性材料との間の冶金学的相和性のために必
要である。ここでははんだ湿潤性が必要ないが、
望ましくない金属間化合物が結合部に形成しない
ようにするために冶金学的相和性は必要である。
この場合にも、パツケージ導線のめつき又は金属
被覆は高価であり、金ワイヤを用いた場合にはそ
のために更に費用がかさむことになる。 The front surface of the semiconductor die is metallized by a patterned metal layer that allows electrical contact to the base and emitter electrodes of the transistor, for example in the case of a bipolar transistor. The patterned metal traces are connected to the semiconductor package leads by thin wires (typically 25-500 microns in diameter) that connect the surface metal traces and the package leads. is connected between These wires are typically aluminum or gold, the top surface metallization is aluminum or many other multilayer metal systems, and the package conductors are plated with nickel or gold. Conductor plating or metallization is necessary for metallurgical compatibility between the aluminum or gold wire and the rigid material of the package conductor. Although solder wettability is not required here,
Metallurgical compatibility is necessary to prevent unwanted intermetallic compounds from forming at the joint.
Again, plating or metallizing the package conductors is expensive, which would add to the cost if gold wire were used.

上述したように組み立てられた半導体デバイス
全体は多くの短所をもつている。半導体デバイス
を組み立てるには、種々の冶金学的選択対象物の
なかから選択する必要があり、費用、熱および電
気的特性及び信頼性などの変数に関して変換
（tradeoff）を必要とする。例えば、信頼性は、
アルミニウム＝金の金属間化合物の生成によつて
損なわれるであろう。これらの短所および必要と
される変換のために、改良された半導体デバイス
組立体をつくる必要があつた。 The overall semiconductor device assembled as described above has many disadvantages. Assembling semiconductor devices requires choosing among a variety of metallurgical options and requires tradeoffs with respect to variables such as cost, thermal and electrical properties, and reliability. For example, reliability is
This will be impaired by the formation of an aluminum=gold intermetallic compound. Because of these shortcomings and the required transformations, there has been a need to create improved semiconductor device assemblies.

従つて、本発明の目的は、めつきのしていない
合金パツケージ部材上に組み立てられた改良され
ためつきのしてないパツケージを含む半導体デバ
イスを提供することである。 SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a semiconductor device that includes an improved non-plated package assembled on a non-plated alloy package member.

本発明のもう１つの目的は、改良された冶金学
的に相和性のある裏表面金属配線、金属はんだお
よびめつきのしていないダイ実装パツケージ部材
を含む、めつきのしてないパツケージを含む半導
体デバイスを提供することである。 Another object of the present invention is to provide improved metallurgically compatible backside metallization, metal solder, and semiconductor packaging including unplated die-mount package components. is to provide the device.

本発明の更にもう１つの目的は、めつきのして
ない銅合金パツケージ導線部分と相和性のある前
表面金属配線および導線結合手段を含む、めつき
のしてないパツケージを含む半導体デバイスを提
供することである。 Yet another object of the present invention is to provide a semiconductor device that includes an unplated package that includes front surface metallization and conductor bonding means that are compatible with the unplated copper alloy package conductor portion. That's true.

本発明のさらにもう１つの目的は、金属間化合
物を形成しない改良されたデバイス金属配線を含
む、めつきのしてないパツケージを含む半導体デ
バイスを提供することである。 Yet another object of the present invention is to provide a semiconductor device that includes an unplated package that includes improved device metal interconnects that do not form intermetallic compounds.

本発明のもう１つの目的は、めつきのしてない
銅合金ダイ実装パツケージ部材と冶金学的に結合
した半導体ダイ、およびめつきのしてない銅合金
導線部分パツケージ部材と結合した導線を含む、
めつきのしてないパツケージを含む半導体デバイ
スを提供することである。 Another object of the invention includes a semiconductor die metallurgically bonded to an unplated copper alloy die mounting package member and a conductor bonded to an unplated copper alloy conductor segment package member.
An object of the present invention is to provide a semiconductor device including an unplated package.

本発明の更にもう１つの目的は、めつきのして
ない実装部材パツケージ部分に実装され改良され
た信頼特性を有するハウジングに収容されためつ
きのしてないパツケージを含む半導体デバイスを
提供することである。 Yet another object of the present invention is to provide a semiconductor device that includes a non-plated package mounted on a non-plated mounting member package portion and housed in a housing having improved reliability characteristics.

発明の要約 上述した目的や利点およびその他の目的及び利
点は、めつきのしてないパツケージ部材と組み合
わさつた相和性のある金属系により接触されてい
る半導体ダイを使用することによつて達成され
る。本発明の１実施例では、半導体デバイスは、
その第１表面上にメタライズされ、ダイ金属配線
（メタライゼーシヨン）と銅合金パツケージ部分
との両方と冶金学的の相和性を有するはんだ組成
を用いてパツケージのめつきのしてない銅金属ダ
イ実装部分に取りつけられた半導体ダイを含む。
パツケージの銅合金導線部分と半導体ダイの第２
表面上にパターン配線が形成された金属配線層と
の間に銅リボン（copper ribbon）が結合され、
それらの間を電気的に相互接続している。この銅
リボンは、導線部分及びパターン形成の金属層と
冶金学的相和性を有する。ダイ及び相互接続用リ
ボンはカプセルに封入され、機械的保護及び周囲
の保護を与える。SUMMARY OF THE INVENTION The foregoing and other objects and advantages are achieved by the use of a semiconductor die contacted by a compatible metal system in combination with an unplated package member. . In one embodiment of the invention, the semiconductor device includes:
The unplated copper metal of the package is metallized on its first surface and is metallurgically compatible with both the die metallization and the copper alloy package portion. Includes a semiconductor die attached to a die mounting section.
The copper alloy conductor part of the package and the second part of the semiconductor die
A copper ribbon is bonded between a metal wiring layer with pattern wiring formed on the surface,
There is electrical interconnection between them. The copper ribbon is metallurgically compatible with the conductor portion and the patterned metal layer. The die and interconnect ribbons are encapsulated to provide mechanical and environmental protection.

本発明の構成をまとめると下記に示す通りであ
る。即ち、本発明は、 めつきのしてない銅合金ダイ実装パツケージ部
分と、第１および第２表面を有する半導体ダイ
と、前記第１表面上にあつてそこへの電気的接触
を行う第１金属配線と、前記第１金属配線および
前記銅合金ダイ実装パツケージ部分と冶金学的相
和性を有し、前記ダイを前記ダイ実装パツケージ
部分と適合する錫、銀もしくはアンチモンはんだ
と、前記第２表面上にパターンを形成し、その選
択された部分への電気的接触を行う第２金属配線
と、前記ダイ実装パツケージ部分に関連して機械
的に固定された銅合金導線コネクタパツケージ部
分と、前記第２パターン形成金属配線と前記導線
コネクタパツケージ部分とのあいだに超音波的に
結合されそれらを電気的に相互接続させる銅接続
手段と、前記半導体ダイ、前記銅接続手段、及び
前記ダイ実装部分と導線コネクタパツケージ部分
の各々の一部を囲う手段との組合わせからなるこ
とを特徴とするめつきのしてないパツケージを含
む半導体デバイスとしての構成を有するものであ
り、或いはまた、 前記銅合金ダイ実装部分は、金属ベースに保持
されるボンデイング台を具えることを特徴とする
めつきのしてないパツケージを含む半導体デバイ
スとしての構成を有して、更にまた、 前記第１金属配線は、チタン、ニツケルおよび
銀の連続層からなることを特徴とするめつきのし
てないパツケージを含む半導体デバイスとしての
構成を有するものであり、或いはまた 前記第２金属配線は、チタン、ニツケル及び銅
の連続層からなることを特徴とするめつきのして
ないパツケージを含む半導体デバイスとしての構
成を有し、或いはまた、 チタン、ニツケル、及び銅のパターン形成され
た１つの上部金属を具備する半導体ダイと、前記
半導体ダイに隣接して配置された複数の銅合金導
線と、 前記銅合金導線を前記半導体ダイの上部金属へ
接続するための複数の銅ワイヤ線との組み合わせ
で構成されたことを特徴とするめつきのしてない
パツケージを含む半導体デバイスとしての構成を
有するものである。 The configuration of the present invention is summarized as follows. That is, the present invention provides: a semiconductor die having an unplated copper alloy die mounting package portion, first and second surfaces, and a first metal on said first surface making electrical contact thereto. a tin, silver or antimony solder that is metallurgically compatible with the first metal interconnect and the copper alloy die mounting package portion and compatibility with the die mounting package portion; and a tin, silver or antimony solder on the second surface. a second metal trace patterned thereon and making electrical contact to selected portions thereof; a copper alloy conductor connector package portion mechanically secured in association with said die mount package portion; a copper connecting means ultrasonically coupled between two patterned metal traces and the conductive wire connector package portion to electrically interconnect them; and a conductive wire with the semiconductor die, the copper connecting means, and the die mounting portion. The device is configured as a semiconductor device including a non-plated package characterized in that the connector package portion is configured in combination with means for enclosing a portion of each of the connector package portions, or the copper alloy die mounting portion is , the first metal wiring is made of titanium, nickel, and silver. It has a configuration as a semiconductor device including an unplated package characterized in that it consists of a continuous layer, or the second metal wiring is characterized in that it consists of a continuous layer of titanium, nickel, and copper. a semiconductor die configured as a semiconductor device including an unmetallized package; and a plurality of copper wires for connecting the copper alloy conductors to the upper metal of the semiconductor die. It has a configuration as a device.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は、本発明によるプラスチツク製のカプ
セル封入した半導体デバイスを部分的に切断した
斜視図で示したものである。 FIG. 1 shows a partially cut away perspective view of a plastic encapsulated semiconductor device according to the present invention.

第２図は、半導体デバイス組立体を断面図で概
略的に示したものである。 FIG. 2 schematically shows a semiconductor device assembly in cross-section.

第３図は、本発明の別の実施例を部分的に切断
した斜視図で示したものである。 FIG. 3 shows a partially cut away perspective view of another embodiment of the invention.

好ましい実施例の詳細説明 第１図は、本発明による半導体デバイス１０の
１実施例を部分的に切断した斜視図を示したもの
である。ここではシリコンバイポーラトランジス
タとして示してあるデバイス１０は、結合され保
護パツケージ内にカプセル封入されている半導体
ダイ１２を含む。パツケージはダイ実装部分１
４、導線（リード）部分１６及び成型されたプラ
スチツク製カプセル（encapsulant）１８を含む。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a partially cutaway perspective view of one embodiment of a semiconductor device 10 according to the present invention. Device 10, shown here as a silicon bipolar transistor, includes a semiconductor die 12 that is bonded and encapsulated within a protective package. The package is the die mounting part 1
4, including a lead portion 16 and a molded plastic encapsulant 18.

ダイ１２はダイ実装部分１４に冶金学的に結合
されている。ダイ実装部分に機械的支持を与え、
トランジスタダイの背面又はコレクタに対し電気
的接触を与え、デバイスの動作で発生する熱を散
逸するための熱だめ（heat sink）として機能す
る。ダイ実装部分はまたフランジを通つて延びて
いる実装穴２２を有するフランジ部分２０を含む
ことがある。フランジ及び穴は例えば電気的シヤ
シ又は熱だめに対しデバイスの実装を容易にす
る。 Die 12 is metallurgically coupled to die mounting portion 14 . Provides mechanical support to the die mounting area,
It provides electrical contact to the backside or collector of the transistor die and acts as a heat sink to dissipate heat generated by operation of the device. The die mounting portion may also include a flange portion 20 having a mounting hole 22 extending therethrough. The flanges and holes facilitate mounting the device to, for example, an electrical chassis or heat sink.

ダイ１２の上部表面上には、トランジスタのベ
ース及びエミツタ端子にそれぞれ電気的接触を行
うベース金属２４及びエミツタ金属２６を含むパ
ターン形成金属配線がある。金属ワイヤである、
又はできればリボン状であることが好ましい導線
２８は、ベース及びエミツタ金属と導線部分１６
とを相互接続している。導線は上部表面金属配線
と導線部分１６の末端部に位置している結合部位
との間をできれば超音波を用いた結合技術によつ
て結合している。導線部分１６のうちの１本の導
線３２は、ダイ実装部分１４の柱（post）部分３
４に機械的に結合されている。これはパツケージ
のダイ実装部分と導線実装部分とを機械的相互接
続するのに役立つており、またトラジスタダイの
コレクタ部分とパツケージ導線部分との間を電気
的に相互接続させている。２つのパツケージ部分
を結合し、ダイと導線部分１６との間を導線２８
で結合すると、非常に小型でかつ感度のよいトラ
ンジスタダイと電気的接触を行うための手段が与
えられる。従つて半導体デバイスの使用者はパツ
ケージ外部と効果的な電気的接触をすることがで
きる。 On the top surface of die 12 is patterned metal wiring including base metal 24 and emitter metal 26 that make electrical contact to the base and emitter terminals of the transistor, respectively. metal wire,
Alternatively, the conductor 28, which is preferably ribbon-shaped, is formed between the base and emitter metal and the conductor portion 16.
are interconnected. The conductor is bonded between the upper surface metal trace and the bonding site located at the distal end of the conductor portion 16, preferably by ultrasonic bonding techniques. One conductor 32 of the conductor portion 16 is attached to a post portion 3 of the die mounting portion 14.
4. Mechanically coupled to 4. This serves to provide a mechanical interconnection between the die mounting portion and the conductor mounting portion of the package, and an electrical interconnection between the collector portion of the transistor die and the package conductor portion. The two package sections are joined together and the conductor 28 is inserted between the die and the conductor section 16.
This provides a means for making electrical contact with a very small and sensitive transistor die. The user of the semiconductor device can therefore make effective electrical contact with the exterior of the package.

デバイスを完成させるために、結合した半導体
ダイ、相互接続用の導線、及びダイ実装部分と導
線部分の部品を、成形した保護用のプラスチツク
製容器（ハウジング）１８内にカプセル封入す
る。このプラスチツクはダイ及び導線を機械的損
傷及び汚染から保護する。プラスチツクカプセル
封入は、また導線部分１６を機械的に支持し、パ
ツケージ部品の正しい位置ぎめを維持する。 To complete the device, the combined semiconductor die, interconnect conductors, and die mounting and conductor components are encapsulated within a molded protective plastic housing 18. This plastic protects the die and conductors from mechanical damage and contamination. The plastic encapsulation also mechanically supports the conductor portion 16 and maintains proper positioning of the package components.

第２図は、本発明による半導体デバイス組立体
を分解図で示したものである。半導体ダイは、パ
ターン形成前面金属配線２４，２６を有する。ダ
イの下面は、ダイの下面と良好な電気的及び機械
的接触をする金属層４０によりメタライズされて
いる。半導体ダイをパツケージダイ実装部分１４
に結合させるためにはんだが用いられている。こ
のはんだは、ダイ実装部分を予め錫めつきするこ
とによつて、又はダイの下面を予め被覆すること
によつて予備成形（preform）として供給され
る。 FIG. 2 shows an exploded view of a semiconductor device assembly according to the present invention. The semiconductor die has patterned front side metal traces 24,26. The bottom surface of the die is metallized with a metal layer 40 that makes good electrical and mechanical contact with the bottom surface of the die. Package die mounting part 14 for semiconductor die
Solder is used to bond the The solder is supplied as a preform by pre-tinning the die mounting portion or by pre-coating the underside of the die.

本発明によると、ダイ実装部分１４は銅又は銅
合金で作られ、めつきされないままになつてい
る。銅又は選択された銅合金は、それらの望まし
い熱特性、電気的及び機械的特性の故に、パツケ
ージ部分の為に選択される。デバイスの費用を増
やすダイ実装部分１４のめつき又は金属被覆は不
必要である。“めつきのしてない銅合金”という
語は、薄い表面合金を形成するために加熱するこ
とによつて形成される表面合金と金属間化合物を
含むことを意味し、特に加熱が通常のその後の結
合段階だけからなる場合を意味する。即ち、“め
つきをしてない”ということは、“被覆していな
い”ことを意味するものではなく、めつきをして
ないことは、メタクリル酸メチル又はその他のア
クリル酸（acrylic）などの保護被覆を除外する
ものではない。 According to the invention, the die mounting portion 14 is made of copper or a copper alloy and is left unplated. Copper or selected copper alloys are selected for the package portion because of their desirable thermal, electrical and mechanical properties. Plating or metallization of the die mounting portion 14, which increases the cost of the device, is unnecessary. The term "unplated copper alloys" is meant to include surface alloys and intermetallic compounds formed by heating to form thin surface alloys, especially after heating is normal. This means a case consisting only of a combination stage. In other words, "unplated" does not mean "uncoated," and unplated does not mean coated with methyl methacrylate or other acrylic acids. Protective coatings are not excluded.

ダイ実装部分用材料として銅又は銅合金を選ん
でから、その材料に直接結合するはんだ３８を選
択する。従来の硬ろうおよび軟ろうは上述した
種々の短所を有する以外にも、反復可能な信頼性
の高い方法では直接に銅と結合しない。従つて、
米国特許第4170472号に開示された錫−銀−アン
チモニーはんだはこの応用例においては好好まし
いはんだである。特に重量百分率（％）で錫約61
−69％アンチモニー８−11％、銀23−28％を含む
はんだが好ましい。このはんだは硬ろうの特性と
軟ろう特性とのほぼ中間の特性を有しており、
種々の先行技術のはんだの望ましい特徴の多くを
組み合わせてもつている。この錫−銀−アンチモ
ニーはんだは、めつきしてないダイ実装部位に直
接に結合する。 After selecting copper or a copper alloy as the material for the die mounting portion, a solder 38 is selected to bond directly to that material. In addition to having the various shortcomings mentioned above, conventional hard and soft solders do not bond directly to copper in a repeatable and reliable manner. Therefore,
The tin-silver-antimony solder disclosed in U.S. Pat. No. 4,170,472 is the preferred solder for this application. Especially in weight percentage (%) about tin 61
Preferred is a solder containing -69% antimony, 8-11% antimony, and 23-28% silver. This solder has properties that are approximately intermediate between those of hard solder and those of soft solder.
It combines many of the desirable features of various prior art solders. This tin-silver-antimony solder bonds directly to the unplated die mounting areas.

金属被覆層４０は、半導体ダイの裏面に適用さ
れ、ダイに良好な電気的接触を与え、ろう付け可
能な表面を与える。この金属被覆層は、ダイに付
着してオーム電気接続を与えなければならず、ま
たダイ結合のために選択したはんだと冶金学的に
相和的がなければならない。好ましい金属被覆層
は、チタン、ニツケルおよび銀の連続して層から
なつている。チタンはシリコンウエーハの露出し
た裏面と接触している。加熱するとケイ化チタン
が形成され、このケイ化チタンはウエーハとの強
力な冶金学的結合とともに良好な電気的接触を与
える。銀は、はんだと強力な結合部を形成する。
中間のニツケル層は、シリコンウエーハへの銀の
移動を防止するための障壁として作用する。代わ
りの金属被覆層も用いることができるが、Ti−
Ni−Ag系が好ましい。例えば代わりの金属被覆
層はクロムと銀との連続層からなるが、ケイ化ク
ロムは、シリコンに対してより弱い機械的結合を
示し、チタンにより形成される結合より冶金学的
に劣つている。 A metallization layer 40 is applied to the back side of the semiconductor die to provide good electrical contact to the die and provide a brazable surface. This metallization layer must adhere to the die to provide an ohmic electrical connection and must be metallurgically compatible with the solder selected for die bonding. A preferred metallization layer consists of successive layers of titanium, nickel and silver. The titanium is in contact with the exposed backside of the silicon wafer. Upon heating, titanium silicide is formed, which provides a strong metallurgical bond as well as good electrical contact with the wafer. Silver forms a strong bond with solder.
The intermediate nickel layer acts as a barrier to prevent silver migration to the silicon wafer. Although alternative metallization layers can be used, Ti-
Ni-Ag type is preferred. For example, an alternative metallization layer consists of a continuous layer of chromium and silver, but chromium silicide exhibits a weaker mechanical bond to silicon and is metallurgically inferior to the bond formed by titanium.

パツケージ導線部分１６もまためつきのしてな
い銅又は銅合金で形成されている。銅合金が好ま
しいが、それは銅合金が望ましい量の剛性を与え
るからである。この剛性は、例えば導線をソケツ
トまたはプリント回路基板の穴に挿入しやすく
し、デバイスがひとたび回路内に配線されたなら
ばデバイスの位置を維持するのに必要である。 The package conductor portion 16 is also formed of non-glare copper or copper alloy. Copper alloys are preferred because they provide a desirable amount of stiffness. This stiffness is necessary, for example, to facilitate the insertion of conductive wires into sockets or holes in printed circuit boards, and to maintain the position of the device once it is wired into the circuit.

導線部分１６およびダイ実装部分１４は、部位
４２において物理的に結合されている。この結合
はダイ実装作業前に達成される。この実施例では
ダイ実装部分と導線実装部分とは最初は分離して
いるのであるから、これらの２つの部分は特定の
必要性を満たすため相異なる冶金学的性質を有す
る相異なる銅合金からの同種合金から形成するこ
とができる。例えば、導線部分は、ダイ結合を容
易にするためより柔らかい合金でつくることがで
きるダイ実装部分に比較してより高い降伏点又は
かたさを有する合金で作ることができる。別の実
施例（図示されていない）においては、ダイ実装
部分と導線部分とは単一の単位構造として形成さ
れている。そのような実施例においては、これら
２つの部分は勿論同一材料で形成されなければな
らない。 Wire portion 16 and die mount portion 14 are physically coupled at site 42 . This bonding is accomplished prior to die mounting operations. Since the die mounting section and the conductor mounting section are initially separate in this embodiment, these two sections are made of different copper alloys with different metallurgical properties to meet specific needs. It can be formed from homogeneous alloys. For example, the lead portion may be made of an alloy that has a higher yield point or stiffness compared to the die mounting portion, which may be made of a softer alloy to facilitate die bonding. In another embodiment (not shown), the die mounting portion and the lead portion are formed as a single unitary structure. In such embodiments, these two parts must of course be made of the same material.

ダイの上部表面上には、参照数字24および26に
よつて示されているパターン形成の金属層があ
る。この金属層はトランジスタのベースおよびエ
ミツタのようなデバイス領域に電気的接触を行
う。導線２８はパターン形成の金属配線とパツケ
ージ導線部分とを相互接続させる。従来のパツケ
ージに用いられているアルミニウムワイヤ（配
線）は、めつきのしてない銅合金パツケージに対
する結合では比較的信頼性が低い。金ワイヤも使
用できるが、きびしい制限的なプロセス上の制約
がある。更に金導線はきわめて高価である。本発
明によると、導線２８は銅又は銅合金からなり、
銅合金パツケージに直接に結合するのに用いられ
る。パターン形成金属層２４，２６は導線２８と
相和性がなければならない。従つて、層２４，２
６はチタン、ニツケル、銅の連続層からなつてい
ることが好ましい。チタンは半導体ダイと直接に
接触し、良好な電気的および機械的接触を行う。
銅層は銅導線との強力な結合を可能にする。ニツ
ケル層は銅の移動（マイグレーシヨン）に対する
障壁となり、銅がデバイス性能に悪影響を与える
可能性のある半導体ダイへの銅の移動を防止す
る。Ti−Ni−Cu金属系は、これらの３種の金属
が、例えば硝酸、酢酸、弗化水素酸および水から
なる食刻剤（etchant）では１回のエツチング作
業でエツチングできるという理由からも好まし
い。Al−TiW−Cuなどの代わりの金属系も冶金
学的には容認できるが、層にパターンを形成する
ために３種の別々の食刻剤を必要とし、したがつ
て３回の別々の食刻段階を必要とするという短所
を有する。 On the top surface of the die is a patterned metal layer designated by reference numerals 24 and 26. This metal layer makes electrical contact to device regions such as the base and emitter of the transistor. Conductive lines 28 interconnect the patterned metal traces and the package conductive lines. The aluminum wire used in conventional packages is relatively unreliable in bonding to unplated copper alloy packages. Gold wire can also be used, but there are severe and restrictive process constraints. Furthermore, gold conductors are extremely expensive. According to the invention, the conducting wire 28 is made of copper or a copper alloy;
Used to bond directly to copper alloy packages. Patterned metal layers 24, 26 must be compatible with conductive wire 28. Therefore, layer 24,2
Preferably, 6 comprises a continuous layer of titanium, nickel and copper. The titanium is in direct contact with the semiconductor die, making good electrical and mechanical contact.
The copper layer allows for strong bonding with copper conductors. The nickel layer provides a barrier to copper migration, preventing copper from migrating into the semiconductor die where it can adversely affect device performance. The Ti-Ni-Cu metal system is also preferred because these three metals can be etched in a single etching operation with an etchant consisting of, for example, nitric acid, acetic acid, hydrofluoric acid, and water. . Alternative metal systems such as Al-TiW-Cu are metallurgically acceptable, but require three separate etchants to pattern the layer, thus requiring three separate etchants. This method has the disadvantage of requiring a cutting step.

半導体デバイスの組み立て中には、めつきのし
てない銅表面の酸化を防止するよう注意しなけれ
ばならない。表面が酸化すると適当な冶金学的結
合が阻止され、組立体歩留りおよび信頼性に関す
る諸問題が起きる可能性がある。従つてはんだの
溶解中に、加熱されたパツケージ部材は、ダイボ
ンデイングおよびその後のワイヤボンデイングを
妨げる酸化を防ぐために窒素または化成
（forming）ガスなどの流動する不活性又は還元
雰囲気内に維持される。導線は超音波を用いたボ
ンデイング技術を用いて上部金属配線およびパツ
ケージ導線に接着される。このような技術は特に
熱圧縮又はボールボンデイング技術と比べると加
熱がきわめて少なくてすむ。超音波ワイヤボンデ
イングは室温作業であるので、ボンデイング中に
酸化を防ぐための特別の保護雰囲気は不必要であ
る。 During assembly of semiconductor devices, care must be taken to prevent oxidation of unplated copper surfaces. Surface oxidation can prevent proper metallurgical bonding and can cause assembly yield and reliability problems. Thus, during melting of the solder, the heated package member is maintained in a flowing inert or reducing atmosphere, such as nitrogen or forming gas, to prevent oxidation that would interfere with die bonding and subsequent wire bonding. The conductors are bonded to the upper metal wiring and package conductors using ultrasonic bonding techniques. Such techniques require significantly less heating, especially when compared to hot compression or ball bonding techniques. Since ultrasonic wire bonding is a room temperature operation, no special protective atmosphere is required to prevent oxidation during bonding.

導線２８は横断面が円形のワイヤではなく銅の
リボン状であることが好ましい。銅導線は従来の
アルミニウム又は金導線よりもかたくて変形しに
くい。平らなリボンの形は超音波エネルギーを結
合部位全体にわたつて分布し、横断面が円形のワ
イヤよりも必要とする変形が少なくすむ。銅リボ
ンの超音波ボンデイングは他の金属に比べて結合
を制御しやすくなる。比較的にかたい銅はほとん
ど変形せず、均質で再現性のある結合部位を形成
し、従つて過度の変形から起きる可能性のある短
絡の回数を減少させる。 Preferably, the conductor 28 is a copper ribbon rather than a wire with a circular cross section. Copper conductors are harder and less susceptible to deformation than traditional aluminum or gold conductors. The flat ribbon shape distributes the ultrasonic energy throughout the bonding site and requires less deformation than a wire with a circular cross section. Ultrasonic bonding of copper ribbons provides better control of the bond than with other metals. Relatively hard copper deforms very little, forming homogeneous and reproducible bonding sites, thus reducing the number of short circuits that can occur from excessive deformation.

ダイボンデイングおよび導線ボンデイングの後
に、半導体ダイおよび結合部位はダイ被覆で被わ
れる。このダイ被覆は、銅−銅結合部における銅
の移動およびデンドライトの形成を防止するのに
ぜひ必要のように思われる。ポリイミド類は好ま
しいダイ被覆材料である。ダイ被覆はダイおよび
結合部を周囲の雰囲気から守る第１の障壁層であ
る。半導体デバイスのカプセル封入を完了するた
めに、第１図に示すプラスチツク製容器１８が、
ダイおよび導線とダイ実装パツケージ部品の一部
の周囲に射出成型又は圧送成型されている。この
プラスチツクはエポキシ、ポリイミド、工業用プ
ラスチツク又はそれに類するものでさしつかえな
い。 After die bonding and lead bonding, the semiconductor die and bond sites are covered with a die coating. This die coating appears to be necessary to prevent copper migration and dendrite formation at the copper-copper joint. Polyimides are preferred die coating materials. The die coating is the first barrier layer that protects the die and bond from the surrounding atmosphere. To complete the encapsulation of the semiconductor device, the plastic container 18 shown in FIG.
It is injection molded or pressure molded around the die and some of the conductors and die-mounted package components. The plastic may be epoxy, polyimide, industrial plastic or the like.

第３図は本発明の別の実施例を示し、そこでは
めつきのしてない銅又は銅合金部品が非可塑性デ
バイス５０に組み立てられている。デバイス５０
はめつきのしてない台座５４の上に実装されてい
る半導体ダイを含み、この台座はヘツダベース５
５上に実装されている。その代りにめつのしてな
い台座をベースそのものの一部とすることもでき
る。このベースは半導体デバイスの実装を容易に
するのに役立つ。ベースの各端にある穴によつて
デバイスをヒートシンク、シヤシ又はそれに類似
した物に取り付けることができる。 FIG. 3 shows another embodiment of the invention in which unplated copper or copper alloy parts are assembled into a non-plastic device 50. device 50
It includes a semiconductor die mounted on an unfitted pedestal 54, which pedestal is connected to the header base 5.
It is implemented on 5. Alternatively, the plain pedestal can be part of the base itself. This base serves to facilitate the mounting of semiconductor devices. Holes at each end of the base allow the device to be attached to a heat sink, chassis, or the like.

銅合金結合柱５６は、ベースの穴を介して突出
しており、導線を適所に融合させるために溶解し
た絶縁ガラスアイレツト５９によつてベースに物
理的に固定されている。部分的に切断した図に示
されている金属被覆５８ベースに溶接されて気密
封止された囲いを形成し、その内部では雰囲気を
制御することができる。 A copper alloy bonding post 56 projects through the hole in the base and is physically secured to the base by a fused insulating glass eyelet 59 to fuse the conductors in place. A metallization 58, shown in a partially cutaway view, is welded to the base to form a hermetically sealed enclosure within which a controlled atmosphere can be provided.

半導体デバイス５０は第２図に関して上述した
方法と同様の方法で組み立てられる。銅導線６８
は、銅合金結合柱５６とダイの上部表面上のパタ
ーン形成金属配線６４，６６との間に結合されて
いる。導線は、銅リボンであることが好ましく、
パツケージ柱と金属配線との両方に超音波で結合
されることが好ましい。これらの銅導線と相和性
を有するために、上部表面はチタン、ニツケル、
銅の連続層からなつていることが好ましい。ダイ
はその底部表面上にメタライズされ、ダイと電気
的接触を与え、ろう付け可能な表面を与える。は
んだはこのメタライズした層と銅合金ダイ実装台
座とを結合させる。上述したはんだは銅合金およ
び底部表面金属配線と冶金学的に相和性を有しな
ければならず、錫−銀−アンチモニ−合金が有利
である。底部表面金属配線はチタン、ニツケル、
銀の連続層からなつていることが好ましい。 Semiconductor device 50 is assembled in a manner similar to that described above with respect to FIG. copper conductor wire 68
are bonded between the copper alloy bonding posts 56 and patterned metal traces 64, 66 on the top surface of the die. Preferably, the conductive wire is a copper ribbon;
Preferably, both the package post and the metal wiring are ultrasonically coupled. To be compatible with these copper conductors, the upper surface is made of titanium, nickel,
Preferably, it consists of a continuous layer of copper. The die is metallized on its bottom surface to provide electrical contact with the die and provide a brazable surface. Solder joins this metallized layer to the copper alloy die mounting pedestal. The solder described above must be metallurgically compatible with the copper alloy and the bottom surface metallization, with tin-silver-antimony alloys being preferred. Bottom surface metal wiring is titanium, nickel,
Preferably, it consists of a continuous layer of silver.

更に実例をあげて一層具体的に云うと、多数の
シリコンバイポーラパワートランジスタがほぼ第
１図に示すようなパツケージ内に組み立てられて
いる。トランジスタの前面はチタン、ニツケル、
銅の連続層で金属配線されている。シリコンダイ
表面の露出部分に直接に接触しているチタン層の
厚さは50−100ナノメートルである。チタンの上
には厚さ約300−500ナノメートルのニツケル層が
ある。最後に、厚さ約４−６ミクロンの銅層がニ
ツケルの上に形成される。これらの金属層はHF
−HNO3−CH3COOH−水の食刻液を用いて１回
のエツチング段階でパターン配線が形成され、ベ
ースおよびエミツタ接点を形成する。 More specifically by way of example, a number of silicon bipolar power transistors are assembled in a package generally as shown in FIG. The front of the transistor is made of titanium, nickel,
Metallic wiring with continuous layers of copper. The thickness of the titanium layer in direct contact with the exposed portion of the silicon die surface is 50-100 nanometers. On top of the titanium is a layer of nickel about 300-500 nanometers thick. Finally, a copper layer approximately 4-6 microns thick is formed over the nickel. These metal layers are HF
The pattern wiring is formed in one etching step using a -HNO3 - CH3COOH -water etchant to form the base and emitter contacts.

トランジスタの裏側の表面は厚さがそれぞれ約
100、500、4000ナノメートルのチタン、ニツケ
ル、銀の連続層によつて金属被覆されている。 The back surface of the transistor is each approximately
It is metallized with successive layers of titanium, nickel, and silver of 100, 500, and 4000 nanometers.

ダイ実装パツケージ部分は合金C19400、即ち
鉄および亜鉛の銅合金でできている。トランジス
タは錫−銀−アンチモニ−はんだを用いてダイ実
装パツケージ部分に接着される。このはんだは還
元雰囲気内でバツケージ上にプレホーム
（preform）される。トランジスタとパツケージ
の結合は約350−450℃の還元雰囲気内で行われ
る。 The die mounting package portion is made of alloy C19400, an iron and zinc copper alloy. The transistor is bonded to the die mount package using tin-silver-antimony solder. The solder is preformed onto the bag cage in a reducing atmosphere. Bonding of the transistor and package is performed in a reducing atmosphere at approximately 350-450°C.

導線部分パツケージ部材は合金C15500、即ち
銀およびマグネシウムの銅合金でできている。横
断面が約75ミクロン×125ミクロンの銅リボンが、
パターン形成のベースおよびエミツタ金属とパツ
ケージ導線部分との間を超音波で結合している。 The conductor part package member is made of alloy C15500, a copper alloy of silver and magnesium. A copper ribbon with a cross section of approximately 75 microns x 125 microns,
Ultrasonic bonding is used between the patterned base and emitter metal and the package conductor.

トランジスタ、リボン、露出したダイ接着領域
およびワイヤ接着部分の結合端はポリイミドダイ
被覆によつて被われている。ポリイミドは約300
℃で焼結することによつて硬化される。ダイ被覆
プロセス後に、ダイおよび金属パツケージ部材の
各部分は、保護エポキシ容器を射出成型すること
によつてカプセル封入される。 The bonding ends of the transistor, ribbon, exposed die attach area and wire attach portion are covered by a polyimide die cover. Polyimide is about 300
Hardened by sintering at °C. After the die coating process, the die and parts of the metal package member are encapsulated by injection molding a protective epoxy container.

デバイスはこのようなデバイスに見出される最
も一般的に発生する故障、即ちパツケージに対す
るダイ接着の機械的故障、ベース又はエミツタに
対する導線接着の機械的故障、及び成形化合物の
水分浸透を保護するように設計された試験（テス
ト）を受ける。これらの試験として例えばパワー
サイクリング（power cycling）又は間欠的に作
動する寿命試験及び高湿、高温逆バイアス試験が
ある。 The device is designed to protect against the most commonly occurring failures found in such devices: mechanical failure of the die bond to the package, mechanical failure of the conductor bond to the base or emitter, and moisture infiltration of the molding compound. Take the given exam (test). These tests include, for example, power cycling or intermittent life tests and high humidity, high temperature reverse bias tests.

VBEF、BVCEO、HFEなどの特定の変化として定
義されるデバイス故障率（％）は、従来の方法で
組み立てられたデバイスに比べると本発明によつ
て作られたデバイスでは低下する。 Device failure rate (%), defined as a specific change in V BEF , BV CEO , H FE , etc., is reduced for devices made according to the present invention compared to devices assembled using conventional methods.

従つて、上述した目的と利点に完全に合致して
いる新規な半導体デバイスが本発明によつて提供
されたことは明白である。このデバイスはめつき
のしてない銅又は銅合金パツケージ部品及び冶金
学的に相和性のある金属系およびデバイスを組み
立てるためのはんだを含む。本発明は特定のデバ
イスおよびパツケージ型について説明したが、本
発明およびその用途は上述したデバイスおよびパ
ツケージ型に限定するつもりはない。本発明は例
えば種々のパツケージ型内に組み立てたその他の
デバイスおよび集積回路にも利用できる。その他
の変形および変更も勿論上述の説明にかんがみ当
業技術者にとつては明白であろう。従つて、それ
らの変形、変更はすべて本発明の範囲内に入るも
のとして含むことが意図されている。 It is therefore apparent that a novel semiconductor device has been provided by the present invention, which fully meets the objects and advantages set forth above. The device includes unplated copper or copper alloy package parts and a metallurgically compatible metal system and solder for assembling the device. Although the invention has been described with respect to particular device and package types, the invention and its applications are not intended to be limited to the devices and package types described above. The invention can also be used with other devices and integrated circuits assembled in various package types, for example. Other variations and modifications will, of course, be apparent to those skilled in the art in view of the above description. Accordingly, all such modifications and changes are intended to be included within the scope of the present invention.

JP57500908A 1981-03-23 1982-02-05 Semiconductor devices including unplated packages Granted JPS58500463A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US24678481A 1981-03-23 1981-03-23
US246784BRCH 1981-03-23

Publications (2)

Publication Number Publication Date
JPS58500463A JPS58500463A (en) 1983-03-24
JPH0412028B2 true JPH0412028B2 (en) 1992-03-03

Family

ID=22932185

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57500908A Granted JPS58500463A (en) 1981-03-23 1982-02-05 Semiconductor devices including unplated packages

Country Status (5)

Country Link
EP (1) EP0074378A4 (en)
JP (1) JPS58500463A (en)
KR (1) KR900001223B1 (en)
IT (1) IT1147903B (en)
WO (1) WO1982003294A1 (en)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3401404A1 (en) * 1984-01-17 1985-07-25 Robert Bosch Gmbh, 7000 Stuttgart SEMICONDUCTOR COMPONENT
GB2174063B (en) * 1985-04-22 1988-08-17 Philips Electronic Associated Semiconductor device having a laser printable envelope
JPS63253653A (en) * 1987-04-10 1988-10-20 Citizen Watch Co Ltd Resin sealed type pin grid array and manufacture thereof
IT1252624B (en) * 1991-12-05 1995-06-19 Cons Ric Microelettronica SEMICONDUCTOR RESIN ENCLOSED AND ELECTRICALLY INSULATED DEVICE WITH IMPROVED INSULATION CHARACTERISTICS, AND RELATED MANUFACTURING PROCESS
JPH088446A (en) * 1995-05-25 1996-01-12 Rohm Co Ltd Discrete diode
US6821821B2 (en) * 1996-04-18 2004-11-23 Tessera, Inc. Methods for manufacturing resistors using a sacrificial layer
US6020636A (en) * 1997-10-24 2000-02-01 Eni Technologies, Inc. Kilowatt power transistor
US7696611B2 (en) * 2004-01-13 2010-04-13 Halliburton Energy Services, Inc. Conductive material compositions, apparatus, systems, and methods

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2984774A (en) * 1956-10-01 1961-05-16 Motorola Inc Transistor heat sink assembly
US3434018A (en) * 1966-07-05 1969-03-18 Motorola Inc Heat conductive mounting base for a semiconductor device
US3597666A (en) * 1969-11-26 1971-08-03 Fairchild Camera Instr Co Lead frame design
US3763403A (en) * 1972-03-01 1973-10-02 Gen Electric Isolated heat-sink semiconductor device
JPS5120323B2 (en) * 1972-08-08 1976-06-24
US3821615A (en) * 1973-05-16 1974-06-28 Solitron Devices Long life lead frame means for semiconductor devices
US3922712A (en) * 1974-05-01 1975-11-25 Gen Motors Corp Plastic power semiconductor flip chip package
JPS5315763A (en) * 1976-07-28 1978-02-14 Hitachi Ltd Resin sealed type semiconductor device
IN148328B (en) * 1977-04-18 1981-01-17 Rca Corp
IT7821073V0 (en) * 1978-03-09 1978-03-09 Ates Componenti Elettron CLAMP FOR FIXING A SEMICONDUCTOR DEVICE TO A HEAT SINK.
JPS5516425A (en) * 1978-07-21 1980-02-05 Toshiba Corp Semiconductor device
JPS55127027A (en) * 1979-03-26 1980-10-01 Toshiba Corp Semiconductor device

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JPS58500463A (en) 1983-03-24
KR830009650A (en) 1983-12-22
EP0074378A4 (en) 1985-04-25
EP0074378A1 (en) 1983-03-23
IT1147903B (en) 1986-11-26
WO1982003294A1 (en) 1982-09-30
KR900001223B1 (en) 1990-03-05
IT8248005A0 (en) 1982-03-16

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