JPH04144277A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To make it possible to manufacture a semiconductor memory in a simple process by a method wherein the storage anode of a capacitor element is formed of first and second conductor films and the conductor films are laminated in such way that they are connected to each other at one part of the films and are made to separate from each other at the remnant parts of the films. CONSTITUTION:A storage node of a capacitor element 2 is formed of first and second conductor films (polycrystalline silicon films) 13 and 14 and sidewalls (an SiO2 film) 24 are respectively formed on each inner side of opening parts 23 formed in the film 13. The film 14 is connected to a source and drain region (an n<-> diffused layer) 21 on one side of a transistor 11 via a contact hole 22 surrounded with the sidewalls 24 and the films 13 and 14 are laminated in such a way that they are connected to each other at one part of the films 13 and 14 and are made to separate from each other at the remnant parts of the films 13 and 14. A dielectric film (an ONO film) 16 is formed on the surfaces of the films 13 and 14. Accordingly, the area of the hole 22 can be automatically reduced under the limit of a lithography and a storage of electricity is possible in the surfaces of the films 13 and 14 at the parts separating from each other.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a DRAM, and particularly to a semiconductor memory called a stacked capacitor DRAM.

[Summary of the invention]

The present invention provides a semiconductor memory as described above, in which a storage node of a capacitive element is formed using first and second conductive films, and the first and second conductive films are connected to each other at a portion and separated from each other at the remaining portion. By laminating them in a similar manner, a so-called self-shrink type two-to-contact structure and a fin structure are combined, making it possible to achieve a high degree of integration and yet to be manufactured using a simple process. .

[Conventional technology]

As a structure that reduces the memory cell area of stacked capacitive DRAM and achieves high integration, the area of the contact hole between the storage node of the capacitive element and the source/drain region of one of the transistors is automatically reduced to below the limit of lithography. A so-called self-shrinking node contact structure is known.

On the other hand, a so-called fin structure having stacked storage nodes is known as a structure that prevents the capacitance value of a capacitor element from decreasing due to reduction in memory cell area.

Figure 2 shows a multilayer capacitive type D that combines these so-called self-shrinking node contact structures and a fin structure.
A conventional example of RAM is shown.

In this conventional example, a memory cell is composed of a transistor 11 and a capacitive element 12. The capacitive element 12 includes a storage node made of three layers of polycrystalline Si films 13 to 15, and a storage node made of three layers of polycrystalline Si films 13 to 15;
ONO is a three-layer film consisting of an O□ film, a SiN film, and a SiO□ film.
It is composed of a dielectric film made of a film 16 and a plate 'TI pole made of a single layer of polycrystalline Si film 17.

The N- diffusion layer 21, which is one source/drain region of the transistor 11, and the polycrystalline Si film 14 are connected through a contact hole 22.

The contact hole 22 is opened while forming a side wall made of a SiO□ film 24 or the like inside the opening 23 of the polycrystalline Si film 13. Therefore, even if the area of the opening 23 is about the limit of lithography, the area of the contact hole 22 is automatically reduced to below the limit of lithography. Therefore, this conventional example has a so-called self-shrinking node contact structure.

Moreover, the ONO film 1 is also formed between the polycrystalline Si films 14 and 15.
6 and a polycrystalline St film 17 are interposed therebetween, and the storage node is of a stacked type. Therefore, this conventional example also has a so-called fin structure.

[Problem to be solved by the invention]

However, in the conventional example shown in FIG. 2, three layers of polycrystalline Si films 13 to 15 are required to form a storage node, so the manufacturing process is complicated.

In addition, if three layers of polycrystalline Si films 13 to 15 are required in this way, it is necessary to open contact holes 25 for connecting the polycrystalline Si films 14 and 15 separately from the contact holes 22. There is. Therefore, this also complicates the manufacturing process in the conventional example shown in FIG.

[Means for Solving the Problems] In the semiconductor memory according to the present invention, the storage node of the capacitive element 12 is formed by the first and second conductor films 13 and 14, and the storage node formed in the first conductor film 13 is A side wall 24 is formed inside the opening 23, and the side wall 2
The second conductor film 14 is connected to one source/drain region 21 of the transistor 11 through a contact hole 22 surrounded by The first and second conductor films 13 are stacked so that they are connected in some parts and separated in the rest.
．． A dielectric film 16 is formed on the surface of 14.

[Effect]

In the semiconductor memory according to the present invention, a side wall 24 is formed inside the opening 23 of the first conductor film 13 constituting the storage node, and the contact hole 22 for the transistor 11 is surrounded by the side wall 24. .

Therefore, the area of the contact hole 22 can be automatically reduced to below the limit of lithography, resulting in a so-called self-shrinking node contact structure.

Further, the first and second conductive films 13.14 are laminated so as to be separated from each other except at the connecting portions, and a dielectric film 16 is provided on the surfaces of the first and second conductive films 13.14. It is formed.

Therefore, the first and second conductor films 1 in the spaced apart part from each other
It is possible to store electricity on the surface of 3.14, and has a so-called fin structure.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG.

FIG. 1 shows the manufacturing process of this embodiment.

In this manufacturing process, as shown in FIG. 1A, the Si substrate 26
A SiO□ film 27 is formed on the surface of the gate oxide film 7 to form a gate oxide film.

Then, a gate electrode is formed using the polycrystalline Si film 31 on the 5iOzW layer 127, and N diffusion layers 21 and 32, which are source and drain regions, are formed to complete the transistor 11.

Thereafter, a Si film 33 is deposited on the entire surface by CVD to form a glabellar insulating film, and a SiN film 33 is deposited on this 5iOz film 33.
4 is deposited by low pressure CVD.

Then, a crystalline Si film 13 is deposited on the SiN film 3 and 4 by CVD, and the polycrystalline Si film 13 is buttered so as to correspond to the N- diffusion layer 21. During this patterning, the polycrystalline St film 13 has an opening 2 located on the N- diffusion layer 21.
3 is also formed.

Next, as shown in FIG. 1B, a Sing film 24 is deposited on the entire surface by CVD, and a resist film 35 is applied on this 5iOz# 24. Then, an opening 36 surrounding the opening 23 is formed in the resist film 35. do.

After that, using the resist film 35 as a mask, the SiO□ film 2
4N film 34 and SiO2 film 33 are sequentially etched. Then, four tact holes 37 are opened on the SiO□ film 24, and the SiO□ film 24 is opened inside the opening 23.
SiO□ film 24 is left on the film 4 and serves as the side wall
A contact hole 22 is opened on the membrane.

In other words, the area of the contact hole 22 is automatically smaller than the area of the opening 23 on the SiO□ film 24 serving as the sidewall. Therefore, if the area of the opening 23 is about the limit of lithography, the area of the contact hole 22 is less than the limit of lithography.

Next, as shown in FIG. 1C, after removing the resist film 35, a polycrystalline Si film 14 is deposited by CVD.
Polycrystalline Si film 14 is patterned to correspond to film 13.

Then, this polycrystalline Si film 14 is connected to the polycrystalline Si film 13 inside the contact hole 37, and the SiO□ film 2
4 and 24 are spaced apart from the upper crystalline Si film 13 and further connected to the N − diffusion layer 21 via a contact hole 22 . The storage node of the capacitive element 12 is completed by the polycrystalline Si films 13 and 14 formed as described above.

Next, as shown in FIG. 1D, the Si film 24 is removed by etching to form a cavity in a portion where the polycrystalline Si films 13 and 14 are separated from each other. However, the four-crystal Si film 13.1 on the SiO□ film 24 as the inner side wall of the opening 23
4, so it will not be etched.

After that, polycrystalline SiI! ! ONO on the surface of 13.14 mag.
The capacitor element 12 is completed by forming M16, depositing a polycrystalline Si film 17, and patterning the polycrystalline Si film 17 into a plate electrode pattern.

In this capacitive element 12, the ONO film 16 is also formed on the surface of the spaced part between the polycrystalline Si films 13 and 14, and the polycrystalline Si film 17 has also entered this spaced part. It is possible to store electricity even on the surface of

In this embodiment as described above, the storage node of the capacitive element 12 is composed of only the two-layer polycrystalline Si film 13.14, and the contact holes 37.22 are opened at one time, so that the manufacturing process is simple.

〔Effect of the invention〕

In the semiconductor memory according to the present invention, although the so-called self-shrinking node contact structure and the fin structure are combined to enable high integration, the storage node of the capacitive element is formed only by the first and second conductor films. Since it is formed, it can be manufactured through a simple process.

[Brief explanation of drawings]

FIG. 1 is a side sectional view sequentially showing the manufacturing process of an embodiment of the present invention, and FIG. 2 is a side sectional view of a conventional example of the present invention. In addition, in the symbols used in the drawings, 11.
3, 14----------------------------------------------------------------''23-----] 24---'' ONO film N-diffusion layer contact hole opening SiO □ film agent soil Figure 1B Inside 1C

Claims (1)

[Scope of Claims] In a semiconductor memory in which a memory cell is constituted by a transistor and a capacitive element, a storage node of the capacitive element is formed by a first and a second conductive film, and the first conductive film A side wall is formed inside the opening formed in the opening, and the second
a conductor film is connected to one source/drain region of the transistor, the first and second conductor films are stacked so that they are connected to each other in some parts and separated in the rest, and and second
A semiconductor memory in which a dielectric film is formed on the surface of a conductor film.