JPH03205866A - Memory device - Google Patents

Abstract

PURPOSE:To enhance reliability without complicating a manufacturing process by laminating a conductive film of the same layer as a conductive film for forming one and the other electrodes of a capacity element on a contact part of a transistor with a bit line. CONSTITUTION:In a memory device having a memory cell formed of one transistor 12 and one capacity element 25, a first conductive film 17 of the same layer as a conductive film for forming one electrode of the element 25 is laminated on an impurity region 14a in a state in contact with the region 14a of the transistor 12, a second conductive film 23 of the same layer as a conductive film for forming the other electrode of the element 25 is laminated on the film 17 in a state in contact with the film 17, and a bit line 32 is connected to the film 17.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a DRAM, particularly a star-socket capacitor type DRAM.
It relates to a memory device called RAM.

[Summary of the invention]

In the memory device as described above, the present invention provides a manufacturing process in which a conductive film of the same layer as the conductive films constituting one and the other electrodes of the capacitive element is laminated at the contact portion between the transistor and the bit line. This improves reliability without complicating the process.

[Conventional technology]

In star-socket capacitor type DRAM, the gate electrode of the transfer transistor, that is, the word line, is formed using the first layer of polycrystalline S.
Alternatively, one electrode of the capacitive element, that is, the storage node, is formed with the second layer of polycrystalline Si film, and the other electrode of the capacitive element, that is, the counter electrode, is formed with the third layer of polycrystalline St. Formed with a film and created by AI! It is generally formed from a film.

[Problem to be solved by the invention]

However, although the surface direction has been significantly reduced due to the miniaturization of DRAMs, the reduction rate in the height direction is smaller than that. For this reason, the aspect ratio of the contact hole of the bit line with respect to the transfer transistor becomes large, and the step coverage of the bit line deteriorates, causing a problem in the reliability of the DRAM.

On the other hand, in order to solve this problem, it has been considered to form the bit line with a fourth layer of polycrystalline Si film or the like and use the AI film for wiring of peripheral circuits. However, providing a fourth layer of polycrystalline Si film or the like complicates the manufacturing process accordingly.

[Means to solve the problem]

In the memory device according to the present invention, the first conductive film 1 is in the same layer as the conductive film 17 constituting one electrode of the capacitive element 25.
A conductive film 23 is stacked on one impurity region 14a of the transistor l2 with 7 in contact with the impurity region 14a, and constitutes the other electrode of the capacitive element 25.
A second conductive film 23 of the same layer is laminated on the first conductive film 17 in contact with the first conductive film 17, and a bisotho wire 32 is connected to the second conductive film 23. has been done.

[Effect]

In the memory device according to the present invention, first and second conductive films 17 and 2 are formed on one impurity region 14a of transistor 12.
3 are sequentially stacked, and the bit line 32 is connected to the second conductive film 23.

Therefore, the step difference of the bit line 32 at the contact portion with the transistor 12 is small, and the step coverage of the bit line 32 is good.

Moreover, the first and second conductive films 17 and 23 are connected to the capacitive element 2.
Conductive films 17 constituting one and the other electrodes of No. 5, respectively.
, 23, the number of conductive film layers is not increased.

? Example] Hereinafter, a manufacturing process of an example of the present invention will be described with reference to FIG.

In this manufacturing process, as shown in FIG.
A gate electrode of the transfer transistor l2 is formed on the first layer of polycrystalline Si film 13, and an N'' region 14a is formed on the gate electrode of the transfer transistor l2.
, 14b and an SiO2 film 15, which is an interlayer insulating film, are formed.

Next, as shown in FIG. IB, N+ regions 14a, 14b
The contact holes 16a and 16b reaching the contact holes 16a and 16b are made of SiO. membrane 15
In this state, the second layer of polycrystalline Sill! 17
is deposited by CVD. And this polycrystalline Si
A resist 18 is patterned to cover portions of the film 17 on and near the N'' regions 14a and 14b.

Next, as shown in FIG. IC, the polycrystalline Si film 17 is patterned using the resist 18 as a mask, and after removing the resist 18, an insulating film 2l, which is a two-layer film of an SiN film and a SiO2 film, is formed. Form on the entire surface. And the part of this insulating film 21 above the N+ region 14a? The resist 22 is patterned so as to be exposed.

Next, as shown in FIG. ID, the insulating film 21 is etched using the resist 22 as a mask, and after removing the resist 22, a third layer of polycrystalline Si film 23 is deposited by CVD. Then, in this polycrystalline Si film 23, N”e
The resist 24 is patterned to expose a portion near the periphery of the polycrystalline Si film 17 on the ff region 14a.

Next, as shown in FIG. 1E, the polycrystalline Si film 23 is patterned using the resist 24 as a mask, and then the resist 24 is patterned.
Remove 4. As a result, the polycrystalline Si films 17, 23
A capacitive element 25 is formed, which serves as a storage node and a counter electrode, respectively.

Next, as shown in FIG.
After forming the film 26, a BPSG film 27 is deposited by CVD. Then, a contact hole 3l reaching the polycrystalline Si film 23 on the N+ region 14a is formed with the BPSG film 27 and the S
An opening is opened in the iO2 film 26, and A#ll 32 is patterned into a bit line pattern and connected to the polycrystalline Si film 23. With the above, this embodiment is complete.

In this embodiment, polycrystalline Si is formed on the N'' region 14a.
The films 17 and 23 are sequentially stacked, and the contact hole 3
Since the contact hole 3 only needs to reach the polycrystalline Si film 23, the contact hole 3 may be shallower than when the contact hole 31 reaches the N'' region 14a. The film 32 has good step coverage.

Furthermore, as is clear from the above manufacturing process, the polycrystalline Si films 17 and 23 on the N'' region 14a are the polycrystalline Si films 17 and 23 that constitute the storage node and counter electrode of the capacitive element 25.
, 23 are in the same layer. Therefore, although the polycrystalline Si films 17 and 23 are stacked on the N'' region 14a, the number of layers of the polycrystalline Si film is not increased.

〔Effect of the invention〕

In the memory device according to the present invention, the manufacturing process is not complicated because the number of layers of the conductive film is not increased, and the reliability is high because the step coverage of the bit line is good.

[Brief explanation of drawings]

FIG. 1 is a side sectional view sequentially showing the manufacturing process of an embodiment of the present invention. In addition, in the symbols used in the drawings, 12-...1--1--1-1 transfer transistor 1 4
a −−−−−−−−−−−−−N” area 17−・
----------・-----Polycrystalline Si film 2 3
=1−−−−−−−−−−−−−−1 polycrystalline Si film 2
5 ---------------------One capacitive element 3 2-----------------A/film.

Claims (1)

[Claims] In a memory device in which a memory cell is composed of one transistor and one capacitive element, a first conductive film of the same layer as a conductive film constituting one electrode of the capacitive element is provided. A conductive film is stacked on one impurity region of the transistor in contact with the impurity region, and a second conductive film of the same layer as the conductive film constituting the other electrode of the capacitive element is in contact with the impurity region of the transistor. A memory device, characterized in that the memory device is stacked on the first conductive film in contact with the first conductive film, and a bit line is connected to the second conductive film.