JPH04142640A - Address converter - Google Patents

Abstract

PURPOSE:To suppress the overhead for address conversion of an operation system by providing an address converter with the function that if a logical address to be input is the address of a page for an operation system a changeover means is controlled and a logical address is output as a physical address. CONSTITUTION:An arithmetic means M1 converts a logical address correspond ing to a logical address space having a plurality of pages including pages for operation system into a physical address corresponding to a physical address space. A changeover means M2 operates a logical address to be inputted and converts it to output it with or without the intervention of the arithmetic means M1. Further, a changeover control means M3 discriminates whether or not a logical address to be inputted is an address of the page for operation system, and if the logical address is the address of the page for operation system, the control changeover means M3 controls the changeover means M2 to output the logical address as a physical address without the intervention of the arithme tic means M1. With this, overhead for address conversion of address for opera tion system is suppressed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an address conversion device from a logical address space to a physical address space.

[Conventional technology]

Conventionally, address conversion for microcomputers has been widely used as a method to improve software productivity by separately preparing a logical address space in which programs are created and a physical address space in which the programs actually operate, and then linking them. It is being done.

[Problem to be solved by the invention]

However, in recent years, with the increase in the size of software, the number of cases in which operating systems are implemented in microprocessors has increased, and when a page for an operating system is provided in a logical address space, there is an increasing demand for high-speed operation of the operating system.

An object of the present invention is to provide an address translation device that can suppress overhead for address translation of an operating system.

[Means to solve the problem]

As shown in FIG. 1, the present invention comprises arithmetic means Ml for converting a logical address corresponding to a logical address space having a plurality of pages including operating system pages into a physical address corresponding to a physical address space; a switching means M2 capable of switching between outputting the logical address via the arithmetic means M1 or outputting it without intervening the arithmetic means Ml; switching control means M3 that determines whether the address is an address for an operation system page, and if it is an address for an operating system page, controls the switching means M2 to output the logical address as a physical address without intervening the calculation means M1; The gist of the present invention is an address translation device equipped with the following.

[Effect]

The switching control means M3 determines whether the input logical address is an address for an operating system page, and if it is an address for an operating system page, it controls the switching means M2 to convert the logical address to a calculating means. To output as a physical address without intervening M1.

C Embodiment] An embodiment embodying the present invention will be described below with reference to the drawings.

FIG. 2 shows the overall configuration of the microcomputer.

A memory management unit (hereinafter referred to as MMU) 2 is connected to a central processing unit (hereinafter referred to as CPU) 1, and a memory unit (hereinafter referred to as MEM) 3 is connected to MMU2. And the CPU
When I executes a program, CPU 1 sends a logical address to MMU2, which converts it into a physical address and sends it to MEM3. MEM3 is designed to return the contents (instruction code) of the physical address to CPU I.

FIG. 3 shows the functional configuration of the microcomputer.

The logical address space 4 includes first to fourth pages PI.

P2. P3. P4 is allocated, and the first page Pl is a page for the operating system. In addition, the physical address space 5 includes first to fourth address spaces 5a and 5b.
, 5c, and 5d are provided. Each address space 5a of the physical address space 5.

5b, 5c, 5d are each page PI of logical address space 4
, P2. P3. This corresponds to P4.

The second page P2 of the logical address space 4 and the second address space 5b of the physical address space 5 are connected via an adder 6. Also, the third page P3 of the logical address space 4
and the third address space 5C of the physical address space 5 are connected via an adder 7. Furthermore, the fourth page P4 of the logical address space 4 and the fourth address space 5d of the physical address space 5 are connected via an adder 8.

Further, the first page PI of the logical address space 4 and the first address space 5a of the physical address space 5 are directly connected.

The base value storage device 9 stores a base address value for converting an address in the logical address space 4 to an address in the physical address space 5, and outputs base address value data to each adder 6, 7.8. . Each adder6. 7
．． 8 adds the address value of the logical address space 4 to this base address value and converts it into the address value of the physical address space 5.

In this embodiment, the MMU 2 constitutes the calculation means, the switching means, and the switching control means, and the CPU constitutes a part of the switching control means.

Next, the address conversion operation by the microcomputer configured as described above will be explained.

When the CPUI executes a program, the CPU1
A logical address consisting of a page number and an address within the page is sent to the MMU2. When the MMU 2 determines that the page number of the logical address is the first page Pl (operation system page), it extends the intra-page address by "0" and adds an upper bit. Note that at this time, in addition to rQJ extension, "1" extension, etc. may be used.

When the MMU 2 determines that the page number of the logical address is the second page P2, the adder 6 adds the base address value of the base value storage 9 to the intra-page address value to generate a physical address. Further, when the MMU 2 determines that the page number of the logical address is the third page P3, the adder 7 adds the base address value of the base value storage 9 to the intra-page address value to generate a physical address. Furthermore, when the MMU 2 determines that the page/number of the logical address is the fourth page P4, the adder 8
At , the base address value of the base value storage unit 90 is added to the in-page address value to generate a physical address.

Then, after being converted to a physical address by MMU2,
In MEM3, the contents of the physical address (instruction code)
is sent back to CPU 1. As a result, the CPU 1 executes the program.

As described above, in this embodiment, if the page number of the logical address is the first page Pi (operation system page), the MMU 2 simply extends the address value within the page by "0" and adds the upper bit. The operation is now converted to a physical address without using a special processing cycle.

In other words, the CPU outputs a logical address indicating whether the page is for an operating system or not, and if it is a page for an operating system, it is converted into a physical address by simply adding and adding upper bits without using an adder. did.

As a result, the execution speed of the program written in the first page Pl of the logical address space 4 is the same as that of the second to fourth pages P2 to
The execution speed is faster than that of the program written in P4, and the overhead for address conversion of the operating system can be suppressed.

Note that this invention is not limited to the above embodiments (
For example, in the above embodiment, four pages are provided in the logical address space, but the number is not limited to four. Furthermore, the number of operating system pages is not limited to one.

〔Effect of the invention〕

As described in detail above, the present invention provides an excellent effect of suppressing the overhead for address translation of the operating system.

[Brief explanation of drawings]

FIG. 1 is a complaint correspondence diagram, FIG. 2 is an overall configuration diagram of a microcomputer according to an embodiment, and FIG. 3 is a functional configuration diagram of the microcomputer. Ml is an arithmetic means, M2 is a switching means, and M3 is a switching control means. Patent applicant: Nippondenso Co., Ltd. Agent: Patent attorney On 1) Hironobu (and 1 other person) Figure 2 4 t+]-d

Claims (1)

[Claims] 1. A logical address corresponding to a logical address space having multiple pages including pages for an operating system,
A calculation means for converting into a physical address corresponding to a physical address space, and a switch capable of switching between outputting the input logical address via the calculation means or outputting it without intervening the calculation means. means for determining whether or not the inputted logical address is an address for an operating system page, and if it is an address for an operating system page, controlling the switching means to change the logical address through a calculating means; 1. An address translation device comprising: switching control means for outputting a physical address without changing the physical address.