JPH03142546A - Address converting device - Google Patents

Abstract

PURPOSE:To obtain a real or absolute address and to give an access to a memory by performing an address converting process in response to the attribute of a virtual computer under the control of a microprogram when an access is given to the memory with a logical address. CONSTITUTION:When an access request is received to a memory 80, the deciding result of an address conversion mode is checked. If the checking contents are turned off, a memory control unit 60 uses a logical address directly as a real address of the memory 80 to give an access to the memory 80. If the contents of the deciding result of the address conversion mode are turned on a signal line 30, it is checked whether to logical address on a signal line 31 is registered in an address conversion buffer 70 or not. If so, the buffer 70 outputs a real address corresponding to the registered logical address. Then the unit 60 outputs the real address and has an access to the memory 80. If the logical address is not registered in the buffer 70, the unit 60 starts a microprogram 50 and carries out an address converting process in accordance with the attribute of a virtual computer.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an address translation device, and particularly relates to an address translation device in a virtual computer system.

[Background Art] Generally, in a virtual computer system, several virtual computers (hereinafter referred to as 9M) can be defined under one real computer (hereinafter referred to as host computer). The storage device of each defined VM can be realized by mapping the storage device of the actual computer.
Conventionally, two methods described below are known.

(1) Pageable VM The first method is to provide a continuous partial space of the virtual space of a real computer as the main memory of the VM.

The VM's logical address is determined by the VM's dynamic address translation (DA).
T) is converted into a real memory address by adding a constant value unique to each pageable VM called the main memory start address and performing the DAT of the real computer.

-'(2) Resident VM The second method is to provide a continuous partial space of the absolute address space of the real computer as the main memory of the VM.
The logical address of is converted to the address of the real storage device by adding the VM's DAT and the main storage start address.

Hereinafter, a conventional technique based on the second method will be explained with reference to the drawings.

FIG. 2 is a block diagram showing the configuration of a conventional resident ■M address translation device. In Figure 2, 100
is the segment table origin register (STO), 1
10 is the above-mentioned 1a start address register (MSORGR),
120 is a logical address register (LAR), 130.1
32.134 is a 3-person adder, ↓40 is a segment table (ST), 145 is a page table (PT), 1
50 is a real address register.

In FIG. 2, the LAR 120 stores the logical address of the VM, and this logical address consists of a segment index (SX), a page index (px), and a byte index (BX).

SX of LAR120, segment table origin (STO) stored in 5TOR100, and MSOR
Main memory start address (MSOR) stored in GRIIO
G) is added by the three-man power adder 130, and the signal,
Segment table entry (STE) in iIM 131
) is output as a real memory address.

5T140 is indexed by the real storage address of this STE, and the page table origin (PT○
) 141 is output to the signal line 142. This PT○14↓
, LAR120(7)PX, and MSORGRI 10
M S ORG stored in 3-man power adder 1
32 and output to signal II 132 as the actual address of the page table entry (PTE).

The PT 145 is indexed by the real address of this PTE, detects the PTE, and outputs the PFRA contained in this PTE. This PFRA, LAR120 BX, and MS
MSORG stored in ORGRIIO is added by a three-man adder 134, thereby determining the real memory address corresponding to the logical address of the VM stored in LAR. This real storage address is stored in real address register i 50.

In the address translation operation described above, if the address translation mode hit in the program state word (PSW) of the VM is off, the selector 160 selects LAR1 instead of PFRA.
20 SX and PX are selected, and the three-man power adder 134 is
Using this SX and PX, the real storage address can be determined in the same manner as described above.

Incidentally, as a conventional technique related to the above-mentioned address translation device, for example, a technique described in Japanese Patent Application Laid-Open No. 60-215265 is known.

[Problems to be Solved by the Invention] ゛The above-mentioned conventional technology does not consider the amount of hardware used for VM address translation, and in particular, it is difficult to perform virtual However, there is a problem in that the amount of hardware required increases significantly when realizing this.

SUMMARY OF THE INVENTION An object of the present invention is to provide an address translation device for a virtual machine that can solve the problems of the prior art and can be configured with a small amount of hardware.

[Means for Solving the Problems] According to the present invention, the above-mentioned object has a means for determining an address translation mode, and when the address translation mode is on, memory access using a logical address is performed in an address translation buffer. a real address corresponding to the logical address,
Alternatively, in a computer system that launches a microprogram to perform address conversion processing when an absolute address is not stored, a latch is provided to indicate that a virtual machine is running, and when the latch is on, the virtual machine is running. In this case, this can be achieved by providing means for forcibly turning on the address translation mode of the virtual machine, regardless of the address translation mode of the virtual machine.

[Operation Address translation mode is always on while the virtual machine is operating. As a result, in the present invention, when a memory is accessed using a logical address, if a real address or an absolute address corresponding to the logical address is not stored in the address translation buffer, a microprogram is activated and the microprogram is controlled. Below, address conversion processing is performed according to the attributes of the virtual machine, and a real address or an absolute address can be obtained, and the memory can be accessed using the obtained address.

In addition, even when the virtual machine is not in address conversion mode, the microprogram adds the main culprit/report start address and calculates the real memory address.
Moreover, this real memory address is registered in the address translation buffer. According to the present invention, there is no need to provide an adder dedicated to the main memory start address, and the increase in hardware can be suppressed.

[Embodiment 1] Hereinafter, an embodiment of the address translation device according to the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In FIG. 1, 10 is a VM running determination latch, 11
．． 12 is an address translation mode determination latch, 4o is an address translation activation circuit, 5o is a microprogram, 6o is a memory management unit, 70 is an address translation buffer, 80
is memory.

In the embodiment of the present invention shown in FIG. 1, the VM running determination latch 10 is a mode latch that indicates that the VM is running, and is set by an instruction to start running the VM, and is used to identify interrupts, etc. Due to this factor, it is reset when control is transferred to the host computer. Further, the address conversion mode determination latch 11 is an address conversion mode latch in the PSW, and the address conversion mode determination latch 1
2 is a latch that indicates whether or not the address translation mechanism within the PSW is supported. These latches 11
．． 12 is the host computer's P while the host computer is running.
The contents of the SW are stored, and the VM's PSW is stored while the VM is running.
The contents of are stored.

and both of these latches 11.12 together]''
If set to , address translation mode is turned on. Therefore, the outputs "O'' and "1"° of the outputs of these latches ↓1.12 through the AND circuit 20 and the output of the latch 10 through the OR circuit 21 are the addresses, respectively. It shows the determination result of whether the conversion mode is off or on, and is sent to the memory management unit 60 via the signal line 30.

While the VM is running, the latch 10 is set to "1", and regardless of the address translation mode of the VM indicated by the contents of the latches 11 and 12, the signal line always determines that the address translation mode is on. 30 to the memory management unit 60.

When there is an access request to the memory 80, the signal line 30
The determination result of the above address translation mode is checked, and if the content is OFF, the memory management unit 60 transfers the signal line 3
The memory 80 is accessed using the logical address given from 1 as the real address of the memory. Further, if the determination result of the address translation mode on the signal line 30 is ON, it is checked whether the logical address on the signal line 31 is registered in the address translation buffer 70 or not.

If a logical address is registered, the address translation buffer 70 outputs a real address corresponding to the logical address, and the memory management unit 60 accesses the memory 80 using this real address.

If no logical address is registered in the address translation buffer 7o, the memory management unit 60 starts the microprogram 50 via the address translation startup circuit 40, and the microprogram 50 performs address translation according to the attributes of the virtual machine. Execute processing.

The microprogram 50 operates as follows to execute address conversion processing.

In other words, if it is a pageable VM and the address translation mode is off, the main memory start address is added to the logical address of the VM, and the DAT of the host computer is added.
By performing the processing, the real address of the memory 80 is obtained.

When it is a pageable VM and the address translation mode is on, performs VM DAT processing on the VM's logical address, adds the main memory start address to the result,
Furthermore, the real address of the memory 80 is obtained by performing DAT processing on the host computer.

When it is a resident VM and the address translation mode is off,
The real address of the memory 80 is obtained by adding the main memory start address to the logical address of the VM and then performing DAT processing on the host computer.

When it is a resident VM and address translation mode is on,
The VM's DAT processing is performed on the VM's logical address, and the real address of the memory 80 is obtained by calculating the force a of the main memory start address on the result.

As described above, the real address determined by the microprogram 50, together with the corresponding logical address, space identifier, VM identifier, and address translation mode identifier,
It is registered in the address translation buffer 70 and used for accessing the memory 80.

According to the embodiment of the present invention described above, since VM address translation can be executed using a microprogram, it is possible to configure a VM address translation device with only a slight increase in hardware. In particular, while the amount of hardware is severely limited, it becomes possible to easily realize a virtual computer using a small 1'J-machine.

[Effects of the Invention] As described above, according to the present invention, an address translation device for a virtual machine can be realized with a small amount of hardware.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, and FIG. 2 is a block diagram showing the configuration of a conventional QVM address translation device. 10...VM running judgment latch, 11.12...
・Address conversion mode determination latch, 4o...Address conversion starting circuit, 50...Micro program, 60...Memory management unit, 7o...
Address translation buffer, 80...Memory, 100
...Segment table origin register (STO)
, Engineering 10... Main memory start address register (MSOR)
GR) 120...Logical address register (LAR
), 130.132, 134... 3 manual adder,
140...Segment table (ST), 14
5 page table (PT), 150...Group/real address register.

Claims (1)

[Claims] 1. It has means for determining whether the address translation mode is on or off, and when the address translation mode is on, a real address corresponding to the logical address is stored in the address translation buffer by memory access using the logical address, or In a computer system that activates a microprogram to perform address conversion processing when an absolute address is not stored, means for determining that a virtual machine is running; and a means for determining that the virtual machine is running. An address translation device comprising means for forcibly turning on the address translation mode of the virtual machine, regardless of whether the address translation mode of the virtual machine is on or off.