JPH04141752A - Information processor - Google Patents

Abstract

PURPOSE:To surely detect abnormality when a fault occurs by comparing the value of a write pointer attached on a reply returned from a system controller with that of the write pointer held with a request buffer. CONSTITUTION:The value of the write pointer of the request buffer which holds request information sent from an arithmetic processor 2 to the system controller 5 is added on the request information, and it is sent to the system controller 5. The value of the write pointer is also held with the request buffer, and the value of the write pointer attached on the reply returned from the system controller 5 is compared with that of the write pointer held with the request buffer. Thereby, the abnormality due to the fault can be detected, and the validity of the reply can be checked, and it is possible to prevent data change and system down from occurring.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing device, and particularly to an information processing device that performs reply control.

[Conventional technology]

A conventional information processing device includes a plurality of processing devices that perform calculation control, an input/output processing device that performs input/output control, a main storage device that performs storage operations, and a system control device that controls each of the above devices. In preparation for this, the arithmetic control processing unit only performed reply control that controlled the order of requests and replies.

[Problem to be solved by the invention]

In the conventional reply control for information processing equipment described above, the order of requests and replies is controlled, but the correspondence between requests and replies is not actually checked. When a failure occurs in a request buffer of an arithmetic processing unit and the failure is not detected, the system operates abnormally, resulting in problems such as data corruption and system failure.

[Means to solve the problem]

The information processing device of the present invention includes a plurality of arithmetic processing devices that perform arithmetic control, a plurality of input/output processing devices that perform input/output control,
a main storage device that performs storage operations; a system control device that controls each of the processing devices; A request buffer is provided for controlling the request reply from the system control device, and the value of the write pointer of this request buffer is added to the request and sent to the system control device, and the value of the write pointer is also held in the request buffer. and means for comparing the value of the write pointer added to the reply when the reply is returned from the system control device with the value of the write pointer held in the request buffer.

〔Example〕

Next, the present invention will be explained with reference to the drawings. Fig. 1 is a block diagram showing one embodiment of the present invention, and Fig. 2 is a calculation processing bag of this embodiment! FIG.

The present embodiment shown in FIG.
, arithmetic processing devices 2 and 3 that perform arithmetic control, an input/output processing device 4 that performs input/output control, and a system control device 5 that performs control between the above devices.

The arithmetic processing units 2 and 3 in FIG. 2 are the system control unit 5.
A request flag 11 indicating that the request is valid, a request code register 12 that holds the request code, a request buffer 21 that buffers the request information, and a location in the request buffer 21 where the request information is written. A write pointer 22 to specify, a read pointer 23 to specify from which position in the request buffer 21 the request information is to be read, a reply flag 31 indicating that the reply from the system control device 5 is valid, and a reply code. The request buffer 2 specified by the hold code register 32 and the read pointer 23
A reply waiting register 33 that holds the contents of 1 at the timing when a reply is returned, and a reply code register 3.
2 and the write pointer value in the reply waiting register 33.

3(a) and 3(b) are timing diagrams for explaining the operation of this embodiment.
) and (b), the operations when a memory read request is sent to the system control device 5 and when a reply to the memory read request is returned from the system control device 5 will be described.

In the arithmetic processing units 2 and 3, a request code indicating a read request to the memory is stored in a request code register 12.
is set, the request flag 11 is set, the request signal 111 and the request code signal 121 are sent to the system control device 5, and at the same time the write pointer 2 is set.
A write pointer 221, which is the output signal of No. 2, is also sent to the system control device 5. When the request flag 11 is set, the request signal 111 becomes a set signal, and the request buffer 21 holds the request code signal 121 and the write pointer signal 221 at the position specified by the write pointer 22, and the write pointer 22 also counts. It will be uploaded.

The system control device 5 receives the request code signal 121 using the request signal 111, and after making adjustments with other processing devices, sends a read request to the main storage device 1, and retrieves the ply code from the main storage device 1. When the data is returned, the requester reply code and reply data of the request are sent. At this time, the write pointer value added to the request code is passed around as is and returned to the requester with it added to the reply code.

The arithmetic processing unit reads the request information 211 from the position specified by the read pointer 23 of the request buffer 21 in order to control the reply to the request, and sets the reply signal 312 as a set signal to the reply waiting register 3.
3, and if there is a preceding request in the request buffer 21, the request buffer 21 waits until the reply of the preceding request is returned, but if there is no valid request waiting for a reply in the request buffer 21, the write pointer 22 and the read pointer 23 are equal, the request information written in the request buffer 21 is set in the reply waiting register 33 at the reply timing.

Reply notice signal 3 sent from system control device 5
11, the reply flag 31 is set, the reply signal 312 becomes a set signal, the reply code signal 321 from the system control device 5 is set in the reply code register 32, the request information 211 is set in the reply waiting register 33, and the read pointer is set. 23 is also counted up.

Next, the write pointer signal 322 from the system control device 5 set in the reply code register 32 and the write pointer signal 331 from the request buffer 21 set in the reply waiting register 33 are sent to the comparison circuit 41.
It is checked whether they match, and if they do not match, an error signal 411 is output.

In this way, if the main storage device 1 and the system control device 5 normally reply to the request, the write pointer values will be equal and no error will occur.

〔Effect of the invention〕

As described above, the present invention adds the value of the write pointer of the request buffer that holds request information sent from the arithmetic processing unit to the system control device to the request and sends it to the system control device, and also adds the value of the write pointer of the request buffer that holds request information sent from the processing unit to the system control device. By retaining the value of the write pointer and comparing the value of the write pointer added to the reply when the reply is returned from the system control unit with the value of the write pointer held in the request buffer, the request and reply are Even if the relationship does not operate normally, the abnormality is detected on the arithmetic processing unit side and the authenticity of the reply is checked, which has the effect of preventing data corruption and system failure.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2 is a block diagram of an arithmetic processing device of this embodiment, and Figs. 3(a) and (b).
) is a timing chart for explaining the operation of this embodiment. 1... Main storage device, 2.3... Arithmetic processing unit, 4.
...Input/output processing device, 5...System control device, 11
...Request flag, 12...Request code register, 21...Request buffer, 22...
Write pointer, 23...Read pointer, 31...
-Reply flag, 32...Reply code register, 33...Reply wait register, 41...Comparison circuit.

Claims (1)

[Claims] A plurality of arithmetic processing units that perform arithmetic control, a plurality of input/output processing devices that perform input/output control, a main storage device that performs storage operations, and a system control device that performs control between the respective devices; A buffer for holding request information to be sent from a processing device to the system control device, means for adding a value of a write pointer of this buffer to the request information and sending it to the system control device, and a value of the write pointer of the buffer. An information processing device comprising means for comparing a value of a write pointer to which the request information from the system control device is added.