JPH04137559A - Variable resistance device in master slice lsi - Google Patents
Variable resistance device in master slice lsiInfo
- Publication number
- JPH04137559A JPH04137559A JP26255690A JP26255690A JPH04137559A JP H04137559 A JPH04137559 A JP H04137559A JP 26255690 A JP26255690 A JP 26255690A JP 26255690 A JP26255690 A JP 26255690A JP H04137559 A JPH04137559 A JP H04137559A
- Authority
- JP
- Japan
- Prior art keywords
- master slice
- variable resistance
- resistance
- selection circuit
- terminals
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 2
- 229920005591 polysilicon Polymers 0.000 abstract description 2
- 230000000694 effects Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、マスタスライスLS Ilこおけるチップ
完成後をこ、内部の抵抗値を変更できるようにしγこ可
変抵抗装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a gamma variable resistance device that allows the internal resistance value of a master slice LS Il to be changed after the chip is completed.
異なるLSIチップ間のクロックスキューを調整する方
法として、LSIチップ完成後Gこ、クロックラインの
抵抗値を調整する方法がある。One method for adjusting the clock skew between different LSI chips is to adjust the resistance value of the clock line after the LSI chip is completed.
第2図は従来のクロックスキューの調整を行う可変抵抗
装置の回路図である0図において、 (la)。FIG. 2 is a circuit diagram of a conventional variable resistance device for adjusting clock skew.
(lb)はLSIチップの外部を二股けられγこクロッ
クスキュー調整用の可変抵抗、 (2a)、(2b)
はLSIチップである。(lb) is a variable resistor that is split into two parts on the outside of the LSI chip for adjusting the γ clock skew, (2a), (2b)
is an LSI chip.
次をこ動作Vこついて説明する。可変抵抗(Ia)、
(lb)の抵抗値を変えて、LSIチップ(2a)、
(2b)間のクロックスキューの管理を行なう。The following operation will be explained in detail. variable resistance (Ia),
By changing the resistance value of (lb), LSI chip (2a),
(2b) Manage the clock skew between the two.
従来の可変抵抗装置は以上のように構成されているので
、プリント基板上に、可変抵抗素子を設ける必要があり
、プリント基板上の素子数が増し。Since the conventional variable resistance device is configured as described above, it is necessary to provide a variable resistance element on the printed circuit board, which increases the number of elements on the printed circuit board.
実装密度が下がるという問題点かあつγこ。また、LS
Iチップ内の任意の部分の抵抗値を調整することができ
ないという問題点かあつrこ。The problem is that the packaging density decreases. Also, L.S.
The problem is that the resistance value of any part within the I-chip cannot be adjusted.
この発明は上記のような問題点を解消するためになされ
たもので、可変抵抗素子と、その抵抗値を選択できる回
路を有するマスタスライスLSIにおける可変抵抗装置
を提供することを目的とする0
〔課題を解決するための手段〕
この発明(こ係る可変抵抗装置は、マスタスライスLS
Iの内部領域にしきつめられfこトランジスタのゲート
を接続して形成しγこ抵抗素子と、その両端および途中
から2不以上の端子を取り出し。The present invention was made in order to solve the above-mentioned problems, and an object of the present invention is to provide a variable resistance device in a master slice LSI that has a variable resistance element and a circuit that can select the resistance value of the variable resistance element. Means for Solving the Problems] This invention (this variable resistance device is a master slice LS
A resistor element is formed by connecting the gate of the transistor f to the internal region of I, and two or more terminals are taken out from both ends and part of the resistor element.
少なくともl箇所以上の端子間の短絡、開放を制御する
回路とを有するものである。It has a circuit that controls short-circuiting and opening between at least l terminals.
この発明における可変抵抗装置は、マスタスライスLS
Iの内部領域(こしきつめられfこトランジスタのゲー
トを利用して抵抗素子を形成する。その抵抗素子の両端
および途中から取り出しTこ2本以上の端子間の少なく
とも1箇所以上の端子間を短絡又は開放することによっ
て、異なる抵抗値を得る。The variable resistance device in this invention is a master slice LS.
A resistive element is formed using the internal region of I (tightly packed) using the gate of the transistor. Take out the resistive element from both ends and the middle and short-circuit the terminals at at least one place between two or more terminals. Or open it to obtain a different resistance value.
〔実施例〕
以下、この発明の一実施例を図について説明する。第1
図において、 (3al、 (3b)、 (3cL
(3d)はマスタスライスLSIの内部領域をこあるト
ランジスタのポリシリコンゲートを利用し1こ抵抗素子
、 (4a)。[Example] Hereinafter, an example of the present invention will be described with reference to the drawings. 1st
In the figure, (3al, (3b), (3cL
(3d) is a resistive element using the polysilicon gate of a transistor which is located in the internal area of the master slice LSI, (4a).
(4b) 、 (4c’)はそれぞれ抵抗素子(3a)
、 (3bl、 (3c)、 (3d)より取り出しT
こ端子、(5)は端子(4a)、 (4b)、 (4c
)間の短絡、開放を選択する機能を有する選択回路であ
る1、
次をこ動作Gこついて説明する。選択回路(5)を開放
シTコ場合2ポリ/リコンゲートの抵抗素子(3&l
。(4b) and (4c') are each resistance element (3a)
, (3bl, (3c), (3d) take out T
This terminal, (5) is terminal (4a), (4b), (4c
) is a selection circuit that has the function of selecting short-circuit or open-circuit between G. When the selection circuit (5) is opened, the resistor element of 2 poly/recon gates (3&l
.
(3bl、 (3c1. f3d)を直列接続し1こ抵
抗値が得られる。(3bl, (3c1. f3d) are connected in series to obtain one resistance value.
選択回路(5)を短絡した場合、抵抗素子(、(a)、
(3b)を直列接続し1こ抵抗値が得られ1選択回路
(5)の状態をこより、2種類の抵抗IIを得ることが
できる。When the selection circuit (5) is short-circuited, the resistance elements (, (a),
(3b) are connected in series to obtain one resistance value, and by checking the state of the one selection circuit (5), two types of resistors II can be obtained.
なお、上記実施例では選択回路15)を1箇所に用いf
こものを示したが、選択回路(5)を2a所以上に用い
てもよく、抵抗素子(3a)〜(,3d)より取り出す
端子(4a)〜(4c)の位置との組み合わせにより1
種々の抵抗値を持つTこ可変抵抗素子を形成することが
できる。In the above embodiment, the selection circuit 15) is used at one location.
Although a small one is shown, the selection circuit (5) may be used at more than 2a locations, and depending on the combination with the positions of the terminals (4a) to (4c) taken out from the resistive elements (3a) to (, 3d),
Variable resistance elements having various resistance values can be formed.
以上のようにこの発明によれば、マスタスライスLSI
の内部領域にしきつめられTこトランジスタのゲートを
利用して、可変抵抗素子を構成しTこので、プリント基
板の実装密度を上げることができ、ま1こ、マスクスラ
イスLSI内の回路の任意の位置の抵抗値を、状況に応
じ1こ逐時変更できるという効果がある。さらに、この
発明における可変抵抗装置は、配線工程のみで実現でき
るので。As described above, according to the present invention, the master slice LSI
The gate of the transistor is used to configure a variable resistance element, which is tightly packed in the internal region of the transistor.This makes it possible to increase the packaging density of the printed circuit board. This has the effect that the resistance value at the position can be changed one by one depending on the situation. Furthermore, the variable resistance device according to the present invention can be realized by only a wiring process.
マスタスライスLSIにおいて容易に実現できる。This can be easily realized in a master slice LSI.
第1図はこの発明の一実施例によるマスタスライスLS
IIこおける可変抵抗装置の回路図、第2図は従来の可
変抵抗装置の回路図である。
図において、 (3a)〜(3d)は抵抗素子、(4
al 〜(4c)は端子、(5)は選択回路である。
なお2図中、同一符号は同一 または相当部分を示す。FIG. 1 shows a master slice LS according to an embodiment of the present invention.
FIG. 2 is a circuit diagram of a conventional variable resistance device. In the figure, (3a) to (3d) are resistance elements, (4
al to (4c) are terminals, and (5) is a selection circuit. In Figure 2, the same reference numerals indicate the same or equivalent parts.
Claims (1)
ランジスタのゲートを、接続して形成した抵抗素子と、
その両端および途中から2本以上の端子を取り出し、少
なくとも1箇所以上の端子間の短絡、開放を制御できる
回路を備えたマスタスライスLSIにおける可変抵抗装
置。A resistive element formed by connecting the gates of transistors tightly arranged in the internal region of the master slice LSI;
A variable resistance device in a master slice LSI, which includes a circuit that can take out two or more terminals from both ends and the middle of the terminal and control shorting and opening between the terminals at at least one location.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP26255690A JPH04137559A (en) | 1990-09-27 | 1990-09-27 | Variable resistance device in master slice lsi |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP26255690A JPH04137559A (en) | 1990-09-27 | 1990-09-27 | Variable resistance device in master slice lsi |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH04137559A true JPH04137559A (en) | 1992-05-12 |
Family
ID=17377450
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP26255690A Pending JPH04137559A (en) | 1990-09-27 | 1990-09-27 | Variable resistance device in master slice lsi |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH04137559A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9880203B2 (en) | 2014-03-17 | 2018-01-30 | Fuji Electric Co., Ltd. | Semiconductor device and method for manufacturing the semiconductor device |
-
1990
- 1990-09-27 JP JP26255690A patent/JPH04137559A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9880203B2 (en) | 2014-03-17 | 2018-01-30 | Fuji Electric Co., Ltd. | Semiconductor device and method for manufacturing the semiconductor device |
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