JPS63245902A - Method of regulating circuit characteristics of thick film hybrid integrated circuit - Google Patents
Method of regulating circuit characteristics of thick film hybrid integrated circuitInfo
- Publication number
- JPS63245902A JPS63245902A JP62077417A JP7741787A JPS63245902A JP S63245902 A JPS63245902 A JP S63245902A JP 62077417 A JP62077417 A JP 62077417A JP 7741787 A JP7741787 A JP 7741787A JP S63245902 A JPS63245902 A JP S63245902A
- Authority
- JP
- Japan
- Prior art keywords
- thick film
- integrated circuit
- circuit
- film hybrid
- hybrid integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims description 12
- 230000001105 regulatory effect Effects 0.000 title 1
- 239000012528 membrane Substances 0.000 claims 2
- 230000001419 dependent effect Effects 0.000 claims 1
- 238000009966 trimming Methods 0.000 description 10
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
Landscapes
- Parts Printed On Printed Circuit Boards (AREA)
- Apparatuses And Processes For Manufacturing Resistors (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は厚膜混成集積回路の機能トリミング方法に係り
、特に特性のバラツキ幅の狭い機能トリミング回路に好
適な厚膜混成集積回路の回路特性調整方法に関する。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a method for functional trimming of a thick film hybrid integrated circuit, and in particular to circuit characteristics of a thick film hybrid integrated circuit suitable for a functional trimming circuit with a narrow width of variation in characteristics. Regarding the adjustment method.
従来機能トリミングを施す混成集積回路の調整方法につ
いては特公昭５６−１０８４４号に示される様に回路素
子バラツキを考慮し、トリミング設定値を中心に設定し
、トリミング時間を短縮する方法がある。Regarding the conventional adjustment method of a hybrid integrated circuit that performs functional trimming, as shown in Japanese Patent Publication No. 10844/1984, there is a method in which the trimming setting value is set as the center in consideration of variations in circuit elements and the trimming time is shortened.
従来技術においては特性値がバラツキ中心値に入ってい
る場合でも、必ず１機能トリミング装置で判定し、取り
出すためトリミング工程を不要にできない欠点があった
。In the prior art, even if the characteristic value falls within the center value of the variation, it is always determined by a single-function trimming device and taken out, so there is a drawback that the trimming process cannot be made unnecessary.
本発明の目的はこれらの特性のバラツキを予測し、合理
的な回路特性調整方法を提供することにある。An object of the present invention is to predict variations in these characteristics and provide a rational method for adjusting circuit characteristics.
本発明の特徴はある物理量を調整する電圧を分圧によっ
て得るために集積回路中の電位差のある２点間に接続す
る抵抗に対していずれか一方に接続する抵抗を２本以上
のチップ抵抗を接続する構成とし、該物理量が設定値と
なるような平均的値にしておき、集積回路が完成した後
、特性検査を行ない規格から外れたものについて各選別
ランクに応じて、該チップ抵抗を回路より取りはずして
回路調整をする様にしている。A feature of the present invention is that two or more chip resistors are connected to one of the resistors connected between two points with a potential difference in the integrated circuit in order to obtain a voltage for adjusting a certain physical quantity by dividing the voltage. After the integrated circuit is completed, a characteristic test is performed, and if the chip resistor deviates from the standard, the chip resistor is changed into a circuit according to each selection rank. I try to remove it and adjust the circuit.
規格値から特性値が外れたものについてのみ選別し、ラ
ンク分調整を行なうため機能トリミングをなくすことが
出来る。Since only those whose characteristic values deviate from the standard values are selected and adjusted by rank, function trimming can be eliminated.
第１図は本発明の一実施例を示す集積回路の一部であり
、ＶＣＣの電位と、零電位との間に抵抗をそれぞれ鳥と
鳥とし、直列に接続する構成とし抵抗式、鳥は厚膜抵抗
で形成し、規定の設定値に抵抗トリミングしておく。そ
して、さらに、抵抗島に抵抗ｒ１ｍ’ｔを並列に接続さ
れる構成とし、チップ抵抗は第２図に示す様な方法で接
続する。すると中点電位Ｖ ｐ ＝＋ Ｖ ｃ ｃ−Ｒ
１／５ｉｒｓ ／Ｒ１＋ （Ｒｐａ／ｒｔ／ｒ＊）で決
まり、中点電位Ｖｐを自由に設定することが出来る。中
点電位Ｖｐの値の変化を小さくするためチップ抵抗の抵
抗値ｒｌ、ｒ＠＞鳥とする。抵抗Ｒ１，Ｒ１、チップ抵
抗の値は、実際、機能トリミングを要する回路の特性値
バラツキを確認して決める必要があり、本実施例の様に
特性のバラツキが第３図になっている場合、中点電位Ｖ
ｐが中心値になる様に抵抗焉、鳥、チップ抵抗ｒ１を決
めておく。FIG. 1 shows a part of an integrated circuit showing an embodiment of the present invention.The resistor is connected in series between the VCC potential and the zero potential. It is formed from a thick film resistor and the resistance is trimmed to a specified setting value. Further, a resistor r1m't is connected in parallel to the resistor island, and the chip resistor is connected as shown in FIG. Then, the midpoint potential V p =+ V c c-R
It is determined by 1/5irs/R1+ (Rpa/rt/r*), and the midpoint potential Vp can be freely set. In order to reduce the change in the value of the midpoint potential Vp, the resistance value rl of the chip resistor is set such that r@>bird. The values of the resistors R1 and R1 and the chip resistance must be determined by checking the variation in the characteristic values of the circuit that requires functional trimming, and if the variation in the characteristics is as shown in Fig. 3 as in this example, Midpoint potential V
The resistance, the resistance, and the chip resistance r1 are determined so that p becomes the center value.
電位ｖｐｍｉｎとなりた場合は、チップ抵抗ｒ！を接続
調整し、電位Ｖｍａｘとなった場合はチップ抵抗ｒ１を
回路より取り外すことにより調整する。実際の製造工程
においては、まず、回路が完成した後で、特性検査を行
ない、それぞれ選別しＡ、Ｂ、Ｃと選別しＢのものにつ
いては規格内で良品とし、両端に残ったＢ、Ｃについて
のみ、チップ抵抗の付け、外しで調整することが出来る
。When the potential reaches vpmin, the chip resistance r! When the potential reaches Vmax, adjustment is made by removing the chip resistor r1 from the circuit. In the actual manufacturing process, first, after the circuit is completed, the characteristics are inspected and sorted into A, B, and C. B is considered to be good within the specifications, and the B and C remaining at both ends are classified as A, B, and C. This can only be adjusted by adding or removing a chip resistor.
この様に本発明による回路調整方法では調整すべき物理
量は、はぼ設定値に近くなっており、規格値からはずれ
たものについてのみ調整するため、従来の様に一度、機
能トリミング装置へかける必要がなく、工程を短縮する
ことが出来、製造コスト低減を図ることが出来る。In this way, in the circuit adjustment method according to the present invention, the physical quantities to be adjusted are close to the set values, and only those that deviate from the standard values are adjusted, so it is not necessary to apply the function trimming device once as in the conventional method. There is no need for this process, the process can be shortened, and manufacturing costs can be reduced.
第１図は本発明の詳細な説明するための回路図、第２図
はそのパターン実施例を示す図、第３図は本実施例に関
係する調整項目に関する電位Ｖｐの調整後の値のばらつ
きを示すグラフである。
１．１′・・・チップ抵抗
第１図 第２図
章３図
−郵 ＶｐｍａｘFIG. 1 is a circuit diagram for explaining the present invention in detail, FIG. 2 is a diagram showing an example of its pattern, and FIG. 3 is a variation in the adjusted value of the potential Vp regarding adjustment items related to this example. This is a graph showing. 1.1'...Chip resistance Figure 1 Figure 2 Chapter 3 - Vpmax
Claims (1)
直列に接続し、該膜抵抗のいずれか一方に、２本以上の
チップ抵抗を並列接続しておき、前記２点間の中点電圧
に依存する物理量を該チップ抵抗体を必要に応じて取り
はずすことにより所定の値に調整することを特徴とした
厚膜混成集積回路の回路特性調整方法。 ２、電位差のある２点と中点の間に接続されるチップ抵
抗体の抵抗値は並列接続される膜抵抗の抵抗値より高く
設定されている特許請求の範囲第１項記載の厚膜混成集
積回路の回路特性調整方法。[Claims] 1. At least two membrane resistors are connected in series between two points with a potential difference, and two or more chip resistors are connected in parallel to either one of the membrane resistors, A method for adjusting circuit characteristics of a thick film hybrid integrated circuit, characterized in that a physical quantity dependent on a midpoint voltage between the two points is adjusted to a predetermined value by removing the chip resistor as necessary. 2. The thick film hybrid according to claim 1, wherein the resistance value of the chip resistor connected between two points having a potential difference and the midpoint is set higher than the resistance value of the film resistor connected in parallel. A method for adjusting circuit characteristics of integrated circuits.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62077417A JPS63245902A (en) | 1987-04-01 | 1987-04-01 | Method of regulating circuit characteristics of thick film hybrid integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62077417A JPS63245902A (en) | 1987-04-01 | 1987-04-01 | Method of regulating circuit characteristics of thick film hybrid integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63245902A true JPS63245902A (en) | 1988-10-13 |
Family
ID=13633375
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62077417A Pending JPS63245902A (en) | 1987-04-01 | 1987-04-01 | Method of regulating circuit characteristics of thick film hybrid integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63245902A (en) |
-
1987
- 1987-04-01 JP JP62077417A patent/JPS63245902A/en active Pending
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