JPH0358628A - D/a converter - Google Patents
D/a converterInfo
- Publication number
- JPH0358628A JPH0358628A JP19553089A JP19553089A JPH0358628A JP H0358628 A JPH0358628 A JP H0358628A JP 19553089 A JP19553089 A JP 19553089A JP 19553089 A JP19553089 A JP 19553089A JP H0358628 A JPH0358628 A JP H0358628A
- Authority
- JP
- Japan
- Prior art keywords
- resistance
- switching elements
- elements
- converter
- reference voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000009792 diffusion process Methods 0.000 abstract description 10
- 102220029346 rs34541442 Human genes 0.000 abstract description 2
- 102220065682 rs77311724 Human genes 0.000 abstract description 2
- 102220058910 rs786201402 Human genes 0.000 abstract description 2
- 239000006185 dispersion Substances 0.000 abstract 3
- 102220123496 rs557896607 Human genes 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Landscapes
- Analogue/Digital Conversion (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はD/A変換器に係り、特に高精度の出力レベル
が要求される用途に最適なはしご型D/A変換器に関す
る。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a D/A converter, and particularly to a ladder-type D/A converter that is most suitable for applications requiring a highly accurate output level.
そもそも、D/A変換器とは、複数のデジタル信号を入
力し、それに対応したアナログ値を表わす電流あるいは
電圧を出力して供給する回路であり、色々なタイプのも
のがあるが、はしご型D/A変換器もその一つで、3ビ
ットの従来例を第2図に示す。第2図において、本D/
A変換器の構成としては、デジタル入力信号I4,I5
,I6をインバータ24,25.26で受けて、それら
のインバータ24,25.26の出力を基準電圧源とし
、これらにそれぞれ接続された抵抗値2Rの抵抗素子2
7,28.29と、これらの抵抗素子27,28.29
の間に接続された抵抗値Rの抵抗素子30.31と,抵
抗値2Rの抵抗素子32と、出力端子33とを備えてい
る。To begin with, a D/A converter is a circuit that inputs multiple digital signals and outputs and supplies a current or voltage representing the corresponding analog value.There are various types, but the ladder type D The /A converter is one of them, and a conventional example of a 3-bit converter is shown in FIG. In Figure 2, book D/
The configuration of the A converter is as follows: digital input signals I4, I5
, I6 are received by inverters 24, 25.26, the outputs of these inverters 24, 25.26 are used as reference voltage sources, and resistive elements 2 with a resistance value of 2R are connected to these, respectively.
7, 28.29 and these resistance elements 27, 28.29
A resistance element 30, 31 with a resistance value R, a resistance element 32 with a resistance value 2R, and an output terminal 33 are provided.
例えば(I4,I5,I6)が(0,1.1)の様なデ
ジタル信号が入力されたとすると、第3図に示す等価回
路となる。同図で、■は基準電圧源である。まず、抵抗
素子29.32の合戒抵抗は、接点i−GNDに抵抗値
2Rの抵抗が並列に接続されているのと同じであるから
、オームの法則により、 l R l となる。同様に
、抵抗素子28,29,31.32の合戒抵抗値も、
l B + となる。For example, if a digital signal such that (I4, I5, I6) is (0, 1.1) is input, the equivalent circuit shown in FIG. 3 is obtained. In the figure, ■ is a reference voltage source. First, the combined resistance of the resistive elements 29 and 32 is equal to a resistor having a resistance value of 2R connected in parallel to the contact i-GND, so according to Ohm's law, it becomes l R l . Similarly, the combined resistance value of resistance elements 28, 29, 31.32 is also
It becomes l B + .
よって、接点g−GND間の合或抵抗は2Rとなる。以
上の結果から、次式となる。Therefore, the combined resistance between the contact g and GND is 2R. From the above results, the following formula is obtained.
デジタル入力信号(I4,I5,I6)が他の場合につ
いても、同様にして出力電圧V o u tを求めると
、第4図の真理値表示す様な出力レベルが得られる。If the output voltage V out is determined in the same manner for other digital input signals (I4, I5, I6), the output level as shown in the truth value display in FIG. 4 will be obtained.
前述した従来のはしご型D/A変換器は、半導体集積回
路に内蔵した時、拡散時のバラつきにより設計時の抵抗
値と差が生じる。その為、予想した出力レベルと出際の
出力レベルとの間には誤差が出てくる。その上、拡散後
この誤差の修正はできないという欠点がある。When the above-described conventional ladder-type D/A converter is built into a semiconductor integrated circuit, the resistance value differs from the designed resistance value due to variations during diffusion. Therefore, an error occurs between the predicted output level and the actual output level. Moreover, it has the disadvantage that this error cannot be corrected after diffusion.
本発明の目的は、前記欠点が解決され、抵抗値のバラつ
きを補正することができるようにしたD/A変換器を提
供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a D/A converter in which the above-mentioned drawbacks are solved and variations in resistance values can be corrected.
C課題を解決するための手段〕
本発明のD/A変換器の構戒は、各々デジタル信号を受
けて基準電圧を出力する第1乃至第nの基準電圧源と、
前記第1乃至第nの基準電圧源の出力にそれぞれ一端が
接続された複数の抵抗素子の直列体と、前記直列体の他
端同士間を接続する(n−1)個の抵抗素子とを備え、
前記第nの基準電圧源に接続された直列体の他端と接地
との間に抵抗素子を設け、前記第1の基準電圧源に接続
された前記直列体の他端を出力端子となし、前記複数の
抵抗素子のうちの所定の抵抗素子と並列接続された第】
乃至第nのスイッチング素子と、前記スイッチング素子
を適宜制御するデータを記憶する記憶素子とを備えたこ
とを特徴とする。Means for Solving Problem C] The D/A converter of the present invention has first to nth reference voltage sources each receiving a digital signal and outputting a reference voltage;
A series body of a plurality of resistance elements each having one end connected to the output of the first to nth reference voltage sources, and (n-1) resistance elements connecting the other ends of the series body. Prepare,
a resistance element is provided between the other end of the series body connected to the nth reference voltage source and ground, and the other end of the series body connected to the first reference voltage source is used as an output terminal; ] connected in parallel with a predetermined resistance element among the plurality of resistance elements;
The present invention is characterized in that it includes a switching element to an n-th switching element, and a storage element that stores data for appropriately controlling the switching element.
?実施例〕 次に本発明を図面を参照して説明する。? Example〕 Next, the present invention will be explained with reference to the drawings.
第1図は本発明の一実施例のD/A変換器として3ビッ
トのはしご型D/A変換器を示す回路図である。同図に
おいて、本実施例は、デジタル入力信号II,I2,I
3をそれぞれ受けるインバータ1,2.3の出力を基準
電圧源とし、それに直列に接続した抵抗素子11,14
,15;12,16,17;13,18.19と、これ
らの抵抗素子の他端の間に接続された抵抗素子20,2
1,及び一端がGNDに接続される抵抗素子22と、抵
抗素子14乃至17のそれぞれに並列接続されたスイッ
チング素子5乃至10と、例えばFROM等からなる記
憶素子4とを含み、構成される。この記憶素子4には、
スイッチング素子5乃至10のオンオフを制御するデー
タが書き込めるようになっている。FIG. 1 is a circuit diagram showing a 3-bit ladder type D/A converter as a D/A converter according to an embodiment of the present invention. In the same figure, in this embodiment, digital input signals II, I2, I
The outputs of inverters 1, 2.3, which respectively receive 3, are used as reference voltage sources, and resistance elements 11, 14 are connected in series thereto.
, 15; 12, 16, 17; 13, 18. 19, and the resistance elements 20, 2 connected between the other ends of these resistance elements.
1, and a resistance element 22 whose one end is connected to GND, switching elements 5 to 10 connected in parallel to each of the resistance elements 14 to 17, and a memory element 4 made of, for example, FROM. This memory element 4 has
Data for controlling on/off of the switching elements 5 to 10 can be written therein.
この時、接点a一接点b間の総抵抗なR。とすると、ス
イッチング素子5,6を共にオフさせると、R o ”
R l■+ R l 2 + R + 3となる。ま
た、スイッー5一
?ング素子6だけオンさせると、接点a′一接点b間で
短絡するので、Ro”:R11+R1■となる。At this time, the total resistance between contact a and contact b is R. Then, when both switching elements 5 and 6 are turned off, R o ”
R l■ + R l 2 + R + 3. Also, Sui 5-1? When only the switching element 6 is turned on, a short circuit occurs between contact a' and contact b, resulting in Ro'': R11+R1■.
但し、スイッチング素子の抵抗は無視できるものとする
。以下の説明でも同様に扱う。このように、スイッチン
グ素子のオン2オフの切り換えで、抵抗値は可変である
。そこで、設計時に、R=R20=R21,2R=R1
1+R12=R14+R15=Rl7+R1 8=R2
2としておく。そうすれば、拡散のバラつきが無ければ
、スイッチング素子5,7.9をオフさせ、スイッチン
グ素子6,8.10をオンさせておけばよい。また抵抗
値が、大きくなる方向に拡散がバラついた時は、スイッ
チング素子5乃至10すべてがオン状態にする。However, it is assumed that the resistance of the switching element can be ignored. The same applies in the explanation below. In this way, the resistance value can be varied by switching the switching element between on and off. Therefore, at the time of design, R=R20=R21, 2R=R1
1+R12=R14+R15=Rl7+R1 8=R2
Set it to 2. Then, if there is no variation in diffusion, switching elements 5, 7.9 may be turned off and switching elements 6, 8.10 may be turned on. Further, when the diffusion varies in the direction of increasing the resistance value, all of the switching elements 5 to 10 are turned on.
その逆に、小さくなる方四に拡散がバラついた時は、ス
イッチング素子5乃至10をすべてオフ状態にすれば良
い。On the other hand, when the diffusion varies in the direction of decreasing, all switching elements 5 to 10 may be turned off.
また接点a一接点b間,接点C一接点d間,接点e一接
点f間それぞれで、拡散のバラつき方も違うので、それ
に合せてスイッチング素子のオンオフを切り換えてやれ
ば良い。Furthermore, since the way of diffusion varies between contacts a and b, between contacts C and contacts d, and between contacts e and f, the switching elements can be turned on and off accordingly.
6一
そして、抵抗素子14乃至19と並列に接続されたスイ
ッチング素子5乃至10の制御データを記憶素子4に書
き込む事により、一度テストすれば常に正確な出力レベ
ルが得られる。この記憶素子4のデータ出力線,及びス
イッチング素子と並列に接続されている抵抗素子を増や
し、各々の抵抗値を今以上に小さく分割してやれば、さ
らに微調整ができるので精度がさらに上げられる。6- Then, by writing control data for the switching elements 5 to 10 connected in parallel to the resistance elements 14 to 19 into the memory element 4, an accurate output level can always be obtained once tested. By increasing the number of resistance elements connected in parallel with the data output line of the memory element 4 and the switching element, and dividing each resistance value into smaller values, finer adjustment can be made and accuracy can be further improved.
このように構戊することにより、拡散でバラついた抵抗
値を補正する事ができ、高精度のD/A変換器が得られ
る。By configuring in this way, it is possible to correct the resistance value that varies due to diffusion, and a highly accurate D/A converter can be obtained.
以上説明したように、本発明は、拡散終了後に出力レベ
ルの調整ができる事により、高精度のD/A変換器が得
られる効果がある。As described above, the present invention has the effect of providing a highly accurate D/A converter by being able to adjust the output level after completion of diffusion.
第1図は本発明の一実施例のD/A変換器の回路図、第
2図は従来のD/A変換器の回路図、第3図は第2図の
(I4,I5,I6)それぞれに(“I L I+,“
”H” ,”H” )という信号が入力された時の等価
回路図、第4図は第2図の回路の入力データと出力レベ
ルとの関係を示す図である。
1,2,3,24,25.26・・・・・・インバータ
、4・・・・・・書き込み可能な記憶素子、5乃至10
・・・・・・スイッチング素子、23.33・・・・・
・出力端子、11乃至22.27乃至32・・・・・・
抵抗素子。Figure 1 is a circuit diagram of a D/A converter according to an embodiment of the present invention, Figure 2 is a circuit diagram of a conventional D/A converter, and Figure 3 shows (I4, I5, I6) of Figure 2. To each (“I L I+,”
FIG. 4 is a diagram showing the relationship between the input data and the output level of the circuit of FIG. 2. 1, 2, 3, 24, 25.26... Inverter, 4... Writable storage element, 5 to 10
......Switching element, 23.33...
・Output terminals, 11 to 22. 27 to 32...
Resistance element.
Claims (1)
第nの基準電圧源と、前記第1乃至第nの基準電圧源の
出力にそれぞれ一端が接続された複数の抵抗素子の直列
体と、前記直列体の他端同士間を接続する(n−1)個
の抵抗素子とを備え、前記第nの基準電圧源に接続され
た直列体の他端と接地との間に抵抗素子を設け、前記第
1の基準電圧源に接続された前記直列体の他端を出力端
子となし、前記複数の抵抗素子のうちの所定の抵抗素子
と並列接続された第1乃至第nのスイッチング素子と、
前記スイッチング素子を適宜制御するデータを記憶する
記憶素子とを備えたことを特徴とするD/A変換器。first to nth reference voltage sources each receiving a digital signal and outputting a reference voltage; a series body of a plurality of resistance elements each having one end connected to the output of the first to nth reference voltage sources; (n-1) resistance elements connecting the other ends of the series body, the resistance element being provided between the other end of the series body connected to the n-th reference voltage source and ground; , the other end of the series body connected to the first reference voltage source serves as an output terminal, and first to nth switching elements are connected in parallel with a predetermined resistance element among the plurality of resistance elements; ,
A D/A converter comprising: a memory element that stores data for appropriately controlling the switching element.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19553089A JPH0358628A (en) | 1989-07-27 | 1989-07-27 | D/a converter |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19553089A JPH0358628A (en) | 1989-07-27 | 1989-07-27 | D/a converter |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0358628A true JPH0358628A (en) | 1991-03-13 |
Family
ID=16342623
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP19553089A Pending JPH0358628A (en) | 1989-07-27 | 1989-07-27 | D/a converter |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0358628A (en) |
-
1989
- 1989-07-27 JP JP19553089A patent/JPH0358628A/en active Pending
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