JPH04134563A - Logic simulation system - Google Patents

Abstract

PURPOSE:To reduce the number of elements by adding delay time at a part of all the input terminals of logic elements constituting a logic circuit to the delay time of the logic element in a preceding step to drive the respective input terminals and executing simulation while replacing the delay of the input terminal added the delay time to the preceding step with zero. CONSTITUTION:The delay time at one part of all the input terminals of logic elements 1 and 4 constituting the logic circuit is added to the delay time of the logic element 1 in the preceding step to drive the respective input terminals, and the simulation is executed while replacing the delay of the input terminal IN added the delay time to the preceding step with zero. For example, delay elements 2 and 3 having propagation delay time d1 and d2 are inserted to the input terminal side of the logic element 4, and this delay element 2 is driven by the logic element 1 having propagation delay time (t). Next, the delay time of the logic element 1 in the preceding step is set to (t+d1) and the delay time of the delay element 2 is turned to zero. Thus, by executing the logic simulation in the state of omitting the delay element 2, the number of elements is reduced and counting time required for the simulation can be shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a logic simulation method, and more particularly to a logic simulation method that takes into account the propagation delay of logic elements.

[Conventional technology]

A conventional logic simulation method for an element in a logic circuit is performed in consideration of one propagation delay of the element.

FIGS. 3(a) and 3(b) are logic circuit diagrams for explaining an example of such a conventional method.

As shown in FIG. 3(a), the conventional logic circuit represents a logic element with a propagation delay d, and has two inputs INI, IN
2 and a logic element 4 with a delay time O of
A delay element 7 having a propagation delay d is connected to the output of the delay element 7. In actual implementation as a logic simulator, the delay element 7 is equivalently implemented by registering an event caused by a change in the output of the logic element 4 in the time wheel as an event after time d.

As shown in FIG. 3(b), each element shown in FIG. 3(a) on the logic simulator is realized by one logic element 4 having a propagation delay d.

According to the methods shown in FIGS. 3(a) and 3(b), the propagation delay times from all input terminals INI and IN2 to the output terminal OUT are equal.
The delay time from the input terminal IN2 to the output terminal OUT and the delay time from the input terminal IN2 to the output terminal UT are equal to d. However, in actual logic circuits, the delay time differs depending on the combination of input terminals and output terminals. Therefore, when trying to accurately simulate it, Fig. 3(a),
A simulation method based on (b) cannot be used.

In order to solve this problem, delays are also taken into consideration at the input terminals, and the delay time is changed for each input terminal.

FIG. 4 is a logic circuit diagram for explaining another example of such conventional technology.

As shown in FIG. 4, in this logic circuit, a delay element 2 with a propagation delay time d1 is inserted on the input terminal INI side of the logic element 4, and a delay element 3 with a delay time d2 is inserted on the input terminal IN2 side of the logic element 4.
Insert. Here, if the delay of the logic element 4 is d, then
The delay from input terminal INI to output terminal OUT is dl+d
Therefore, the delay from the input terminal IN2 to the output terminal OUT is d2+d. That is, by providing a difference between delay times d1 and d2 of delay element 2.3, the delay times of each path can be made different.

[Problem to be solved by the invention]

The conventional logic simulation method described above, especially the logic simulation method shown in FIG.
Unlike the delay element 7 inserted on the output side shown in a), this cannot be realized by devising an event processing method, and therefore, it is necessary to treat it as if it were an actual element. In other words, in the latter example shown in FIG. 4, it must be treated as if there are three elements, delay elements 2 and 3, and logic element 4. In other words, in a simulation method in which the input terminal has a delay, the simulation target This effectively increases the number of elements in the logic circuit, which has the disadvantage of significantly increasing the calculation time required for simulation.

An object of the present invention is to provide a logic simulation method that can reduce the number of elements in such a logic circuit and shorten simulation calculation time.

[Means to solve the problem]

The logic simulation formula of the present invention adds the delay time of at least some of all the input terminals of the logic elements constituting the logic circuit to the delay time of the logic element in the previous stage that drives each input terminal. The configuration is such that simulation is performed by replacing the added input terminal delay with zero.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIGS. 1(a) and 1(b) are logic circuit diagrams for explaining one embodiment of the present invention, respectively.

As shown in FIG. 1(a), similar to the conventional example shown in FIG. insert. This delay element 2 is driven by a logic element l having a propagation delay time t.

Next, as shown in FIG. 1(b), the delay time of the logic element 1 in the previous stage is set to (t+dl), and the delay time of the delay element 2 is set to zero. It is clear that even in this case, the logic operation of the logic circuit and the propagation delay time are not affected. If logic simulation is performed with this delay element 2 omitted, the number of elements is small and the counting time required for the simulation can be shortened.

FIGS. 2(a) and 2(b) are logic circuit diagrams for explaining other embodiments of the present invention, respectively.

As shown in FIG. 2(a), in this embodiment, the logic element 1 driving the delay element 2 representing the delay of the input terminal of the logic element 4 simultaneously drives the delay element representing the delay of the input terminal of the logic element 5. It also drives 6.

In this way, in the case of logic element 1 driving multiple delay elements 2 and 6, focus on delay element 2 with the smallest delay time d1, add that delay time d1 to drive element 1, and The delay time db is subtracted from the delay element 6 having the delay time d3, and the delay element 2 is omitted.

As shown in FIG. 2(b), when the delay time is dl<d3, the propagation delay time of the preceding logic element 1 is set as (d + dl''), the delay element 2 is omitted, and the delay of the delay element 6 is Time (d
3-dl).

When a logic circuit in such a state is simulated, results similar to those of the above-mentioned embodiment can be obtained.

〔Effect of the invention〕

As explained above, the logic simulation method of the present invention can largely omit the delay elements connected to the inputs of the logic elements constituting the logic circuit, and is based on the combination of the input terminal and output terminal of each element. This has the effect of not only being able to represent the set of propagation delay times, but also reducing the calculation time required for simulation.

FIGS. 3(a) and 3(b) are logic circuit diagrams for explaining one conventional example, and FIG. 4 is a logic circuit diagram for explaining another conventional example.

1.4.5...Logic element, 2,3.6...Delay element, IN, INI, IN2...Input terminal, OUT...
Output terminal.

Claims (1)

[Claims] The delay time of at least some of all the input terminals of the logic elements constituting the logic circuit is added to the delay time of the logic element in the previous stage that drives each input terminal, and the delay of the input terminal added to the delay time of the previous stage is zero. A logical simulation method characterized by replacing the .