JPH03184175A - Simulation system for composite transfer switch - Google Patents

Abstract

PURPOSE:To shorten an arithmetic time while supplying delay information to only a wired element which gathers respective switch outputs to suppress ineffective noise generation by evaluating a cascaded transfer switch group by evaluating only one control gate and one transfer switch. CONSTITUTION:A simulation circuit performs AND operation by using control gates 13, 15, and 17 for every cascaded transfer switch control groups 102, 103, and 104, and inputs the results to transfer switches 14, 16, and 18. An output 105 obtained by the wired element 19 is obtained by the arithmetic circuit of the switches 14, 16, and 18. The control gates 13, 15, and 17 and transfer switches 14, 16, and 18 are zero-delay models and the wired element 19 is a delay model. The delay information is supplied to only the wired element and the generation of an ineffective noise is suppressed in simulation which is performed when each transfer switch is opened or closed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a simulation method for a composite transfer switch, and particularly to a simulation method for a gate-level composite transfer switch including an MO8 circuit.

[Technological environment]

With recent advances in semiconductor technology, the scale of LSIs has increased and the fields of their application are rapidly expanding.

Furthermore, the manufacturing style of LSIs has shifted from high-volume production of a small number of products to high-mix low-volume production, and product life cycles are also becoming shorter.

Along with this, design support systems that can quickly and correctly implement necessary functions are becoming more essential than ever.

For this reason, logic is developed before manufacturing the actual LSI.

Logic simulators that perform timing verification have been developed and are in use.

Further, with the development of MO3 circuit technology, accurate simulation of transfer switches (MOS switches) is required.

[Common technology]

Generally, transfer switches are often used in MO3 circuits, and a plurality of transfer switches are grouped together to form one logic circuit.

[Conventional technology]

In the conventional composite transfer switch simulation method, delay information is given to each transfer switch, the output state value is calculated from the input state value for each transfer switch, and the output state value is sent to the connected destination while adding delay information. It spreads.

[Problem to be solved by the invention]

The above-mentioned conventional composite transfer switch simulation method calculates and determines the output state for each individual transfer switch, which requires a large amount of time for calculation, and each transfer switch has a delay. This method has the disadvantage that it may detect glitch noise that does not actually occur.

[Means for Solving the Problems] The transfer switch simulation method of the present invention calculates the logical product of one zero-delay transfer switch and the gate input of the transfer switch group, which are connected in cascade, to simulate the transfer switch group. A cascade-connected transfer switch converter that converts a gate input of a switch into a zero-delay control gate, and a parallel-connected transfer switch converter that generates a delayed wired element that performs a wired operation on the output of a group of transfer switches connected in parallel. It consists of means.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a logic circuit diagram showing one embodiment of the present invention.

Figure 1(a) shows the circuit to be simulated, Figure 1(b)
) is a simulation circuit, 11, 14, 16, 18 are transfer switches, 12, 19 are wired elements, 13, 15, 17 are control elements, 101 is a data input, 102, 103, 104 are a group of cascaded transfer switch control signals , 105 is the output.

Actual circuit to be simulated [FIG. 1 (a) In 1, a data input 101 is controlled by a group of cascaded transfer switch control signals 102, 103, and 104 to obtain an output 105.

Simulation circuit [In Fig. 1 (b> 1, cascaded transfer switch control signal group 102.10
3,104, the control gate 13.15.17 calculates the AND, and transfer switch 14.1
6. Input to the gate input of 18.

The calculation circuit of each transfer switch 14, 16, 18 is wired and calculated by the wired element 19, and the output 1
Get 05.

Here, the control gates 13, 15, 17 and transfer switches 14, 16, 18 are zero delay models, and the wired element 19 is a delay model.

Delay information is for each transfer switch 14.16.18
Since it is applied only to the wired elements that combine the outputs, each transfer switch is turned on.

It is possible to suppress the generation of glitch noise that is ineffective in simulation that occurs when the power is off.

〔Effect of the invention〕

The composite transfer switch simulation method of the present invention only needs to evaluate one control gate and one transfer switch when evaluating a group of cascaded transfer switches, which can reduce calculation time and reduce delays. Since information is given only to the wired elements that combine the outputs of each transfer switch, each transfer switch is ON.

The simulation that occurs when the power is off has the effect of suppressing the generation of invalid glitch noise.

[Brief explanation of drawings]

FIGS. 1(a) and 1(b) are circuits showing one embodiment of the present invention. 11.14, 16.18... Transfer switch, 12゜l9... Wired element, 13.15.17... Control element.

Claims (1)

[Claims] A cascade-connected transfer switch that converts a cascade-connected transfer switch group into a zero-delay control gate that calculates the AND of one zero-delay transfer switch and the gate input of the transfer switch group and inputs the result to the gate input of the transfer switch. A simulation method for a composite transfer switch, comprising a converting means and a parallel-connected transfer switch converting means for generating a delayed wired element that performs a wired operation on the output of a group of transfer switches connected in parallel.