JPH04133355A - Insulated gate type bipolar transistor - Google Patents

Abstract

PURPOSE:To realize both low ON voltage and a short switching time by limiting the value of the resistivity of a low impurity concentration layer. CONSTITUTION:An n<+> buffer layer 2 and an n<-> layer 3 are laminated on a p<+> substrate 1 in succession. A silicon oxide film 6 is formed onto the surface of the n<-> layer 3, polycrystalline silicon is deposited on the oxide film 6, and a gate electrode 7 and the gate oxide film 6 are formed through patterning by the same mask. Ions are implanted by utilizing the gate electrode 7 as a mask, and a p<+> layer 4 is shaped through thermal diffusion. An n<+> layer 5 is formed through ion implantation while using the gate electrode 7 and a photo- resist film as masks and thermal diffusion. A source electrode is formed through an insulating film 10 and a drain electrode on a surface on the reverse side, thus completing an element. When the resistivity of the n<-> layer 3 as a third region is increased to high resistivity of 120OMEGA.cm or more at that time, a depletion layer quickly reaches a second region at a turn-OFF time. Accordingly, an insulated gate type bipolar transistor having small turn-OFF loss can be acquired without increasing ON voltage.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an insulated gate bipolar transistor (hereinafter referred to as IGBT) used as a power switching element.
).

[Conventional technology]

In recent years, IGBTs have generally begun to be used as power switching elements.
It has a structure with additional layers. That is, as shown in FIG. 2, a low-resistance n-layer 2 is formed on one surface of a p-silicon substrate 1, and a high-resistance n-layer 3 is laterally formed on the surface thereof. Then, a p' layer 4 is selectively formed on the surface of this n-layer 3, and further an n layer is selectively formed on the surface of this p° layer 4.
゛Layer 5 is formed. Then, the surface region 41 sandwiched between the n- layer 3 and the n-layer 5 in the layer 4 is set as a channel 11m,
A gate insulating film 7 is formed on this, which is connected to the gate terminal G via a gate insulating film I6. And p゛ layer 4n
A source electrode 8 connected to the source terminal S commonly in contact with the layers 5 is formed via the wA edge 1I110, and a drain electrode 8i is connected to the surface of the P substrate via the drain terminal.
Place 9.

In this element, when the source terminal S is grounded and a positive voltage is applied to the gate terminal G and drain terminal, the n' layer 2 and the n-
Layer 3. p layer 4. The MOS FET consisting of the n° layer 5, gate electrode 7, source electrode 8, etc. is turned on, and electrons flow into the n- layer 3 through the channel 41. , holes are injected in response to the inflow of electrons, and conductivity modulation occurs in n-N3, which lowers the resistance of this wIM and makes it conductive with low on-resistance.

(Sin that the invention seeks to solve: The above-mentioned conventional IGBT has a small on-voltage, but
Since the recombination rate of electrons and holes in n-13 is low, there is a problem that the switching time is long, which increases switching loss.

To solve this problem, there are methods to reduce the lifetime by irradiating the silicon element with an electron beam or by diffusing gold in order to increase the recombination rate of electrons and holes. However, when these methods are carried out, the on-voltage of the IGBT becomes larger, that is, there is a trade-off relationship between the on-voltage and the switching time, and it is extremely difficult to improve both characteristics at the same time.

An object of the present invention is to provide an IGET that can eliminate such trade-off relationships and realize both low on-voltage and short switching time.

[Means to solve the problem]

In order to achieve the above object, the present invention provides a first region with a high impurity concentration and a first conductivity type, a second region with a high impurity concentration and a second conductivity type laminated on the first region, and A third region of the second conductivity type with a low impurity concentration laminated on the two regions, a fourth region of the first conductivity type selectively formed on the surface of the third region, and a surface of the fourth region. A semiconductor substrate having a fifth region of a second conductivity type with a high impurity concentration selectively formed in and the semiconductor! The portion of the surface of the fourth region of the board sandwiched between the third region and the fifth HIM is used as a channel region, and a gate electrode is provided on the surface of the fourth region with a gate insulating film interposed therebetween; In an IGBT that includes a source electrode that commonly contacts the surface of the fifth region and a drain electrode that contacts the surface of the first region, the resistivity of the third region is 120Ω·1 or more. Further, the resistivity of the second region is O8 old Ω・1 or more and 0.05Ω・1 or less, and furthermore, the resistivity of the -MJ1t is 0.0
It is desirable that the resistance is 0.05Ω·1 or more and 0.02Ω·1 or less.

[Effect]

If the resistivity of the third region is high, such as 120Ω・0 or more, the depletion layer quickly transfers N11 to the second region at turn-off.
reach When the resistivity of the second region is set to 0.05Ω·1 or less, the injection efficiency is low, so the storage time and the Tilmi flow are reduced, and the turn-off time and turn-off loss can be suppressed. Further, by setting the resistance to 0.01Ω·1 or more, it is possible to suppress an increase in the on-resistance due to a decrease in the implantation 2h* of the pnp transistor. Also, the resistivity of the -fl filling is 0.0
By setting it in the range of 0.05 Ω·1 or more and 0.02 Ω·1 or less, it is possible to determine the upper limit of the on-resistance due to the decrease in injection efficiency from the first region.

〔Example〕

An IGBT having the structure shown in FIG. 2 was manufactured by the following method. First, an n'buff 1 layer 2 and an n' layer 3 are sequentially laminated on a p'' substrate 1 by an epitaxy method, and a silicon nitride film 6 is formed on the surface of the n-layer 3. Polycrystalline silicon is deposited thereon and patterned using a mask to form gate electrode 7 and gate oxide film 6. Then, using this gate electrode 7 as a mask, ion implantation is performed, and a p' layer 4 is formed by thermal diffusion. Furthermore, the n' layer 5 is formed by ion implantation and thermal diffusion using the gate electrode 7 and the photoresist film as a mask.

Subsequently, a source electrode is formed via the insulating film 10, and a drain electrode is formed on the opposite surface to complete the device. Note that this element was not subjected to electron beam irradiation or gold diffusion for the purpose of increasing the recombination rate.

The p-substrate 1 of such an IGBT has a resistivity of 0.01Ω.
N2 buffer layer 2 has a resistivity of 0.
．． 01Ω・1. The thickness is fixed at 5−, and the thickness n of 5Ofl is
- On-voltage V at current density IQOA/- when fabricated with resistivity of layer 3 varied in the range from 20Ω to 300Ω. 1(v) and turn-off loss E, ff(
■ Figure 1 shows the change in J). The on-voltage is constant regardless of the resistivity of the n-layer 3, and the turn-off loss is ρ-120.
It can be seen that the resistivity increases rapidly on the low resistivity side with Ω·1 as the boundary.

Next, an n
``Buff 1 layer 2 is 0.009Ω・Gloss to 0.IQ-ca
I when formed to a thickness of 5B by changing the resistivity during
Figure 3 shows the dependence of the on-voltage V Dam and the turn-off loss Eaff on the buffer layer resistivity at a voltage of GBT'/jL density of 1tloOA/-.The on-voltage is 0.01Ω.
It can be seen that the turn-off loss increases as the resistivity reaches the lower resistivity side after reaching 9 countries, and the turn-off loss increases as the resistivity reaches higher resistivity beyond 0.05Ω·1.

Furthermore, the resistivity of the p゛substrate l is changed from 0.004Ω・value to 0.
．． A resistivity of 200Ω and a thickness of 50n is applied through an n° buffer layer 2 with a resistivity of 0, an old Ω and a thickness of 5-. - On-voltage V in TGBT manufactured by laminating layer 3 1111
Figure 4 shows the dependence of the turn-off loss E*tt on the p″ substrate resistivity.The turn-off loss does not depend much on the p″ substrate resistivity, while the on-voltage is
It is flat in the range of 1 to 0.02Ω, but increases rapidly outside this range.

〔Effect of the invention〕

As can be seen from the above explanation, according to the present invention, the low rate A
The resistivity of the base is 1s, the resistivity of the base layer adjacent to it, or the high discontinuity of the reverse conductivity type below it! J
IGBT with a resistivity of 2 degrees and 1 (f-t) has no upper limit on the on-voltage and has small turn-off loss.
was able to obtain.

[Brief explanation of the drawing]

Figure 1 shows the on-voltage, turn-off loss and n-
Figure 2 is a cross-sectional diagram showing the structure of an IGBT, and Figures 3 and 4 are diagrams showing the relationship between the rGBT's on-voltage, turn-off loss, n'layer resistivity, and p'substrate resistivity, respectively. FIG. Plan 1 flash film, 7: gate electrode, 8: source electrode, 9 nitrogen electrode, 10: insulating film.

Claims (1)

[Claims] 1) A first region of a first conductivity type with a high impurity concentration, a second region of a second conductivity type with a high impurity concentration laminated on the first region, and a second region of a second conductivity type with a high impurity concentration laminated on the second region. a third region of the second conductivity type with a low impurity concentration; a fourth region of the first conductivity type selectively formed on the surface of the third region; and a fourth region of the first conductivity type selectively formed on the surface of the fourth region. A semiconductor substrate having a fifth region of the second conductivity type with a high impurity concentration and a portion sandwiched between the third region and the fifth region on the surface of the fourth region of the semiconductor substrate is used as a channel region. A gate electrode provided on the surface via a gate insulating film, a source electrode commonly in contact with the fourth region surface and the fifth region surface, and a drain electrode in contact with the first region surface, An insulated gate bipolar transistor characterized in that the resistivity of the third region is 120 Ω·cm or more. 2) An insulated gate bipolar transistor according to claim 1, wherein the second region has a resistivity of 0.01 Ω·cm or more and 0.05 Ω·cm or less. 3) In the transistor according to claim 1 or 2,
The resistivity of the first region is 0.005Ω・cm or more, 0.02
An insulated gate bipolar transistor with a resistance of Ω・cm or less.