JPH04129342A - Phase adjustment system - Google Patents

Abstract

PURPOSE:To realize the phase adjustment system for synchronizing frames of plural data having a different input timing with a small circuit scale. CONSTITUTION:The system is provided with a memory section comprising (n-1) memories with respect to n-channels of data inputs. The order of input of a reset signal synchronized at a head to a data of n-channel, a data of (n-1) channels in an early timing is selected and inputted to a memory section in response to the result of discrimination, a data of one channel in a slowest timing is inputted to a data select section and a data write address with respect to the memory section is generated by starting the count in response to the result of discrimination of the input order to write the data. Moreover, the input of a reset signal at a slowest time is discriminated and the count is started in response to the result of discrimination to generate a read address to the memory section and to read the data from the memory section, and the output location at n-channel data output is decided for the data read from the memory section in response to the input order to be discriminated and for the data of one channel selected by the memory select section to generate an output.

Description

[Detailed Description of the Invention] [Summary] Regarding the method of adjusting the phase of multiple data, the purpose is to reduce the memory by selecting the memory according to the input order of data, and to adjust the phase of multiple data. A memory unit consisting of n-1 memories is provided, and a ranking determining unit determines the input order of the reset signal indicating the beginning of each data, and data of the n-1 channel having an earlier timing is selected based on the result of this determination. A memory select section that inputs the data of one channel with the latest timing to the data select section; a write address generation section that generates a data write address for the memory section from the judgment result of the order judgment section; and a write address generation section that generates a reset signal. A read start determination unit that determines the slowest input; a read address counter that generates a read address for the memory unit according to the result of this determination; and read data and memory select from the memory unit according to the determined input order. The data selection section determines the output position of the n-channel data output with the l-channel data selected by the section.

[Industrial Field of Application] The present invention relates to a phase adjustment method, and particularly to a phase adjustment method for synchronizing a plurality of data frames having different input timings.

When a plurality of pieces of data are transmitted via different transmission paths, frame shifts occur due to differences in the transmission paths, so it may be necessary to synchronize the frames of the plurality of data on the receiving side.

The phase adjustment method in such a case is desired to be as small as possible (circuit scale) while maintaining the same function as the conventional one.

[Conventional technology]

FIG. 4 shows a conventional phase adjustment method,
1-1.12.1-3.14 is a memory provided corresponding to the 4-channel data input Dll-DT4; 2-1.
2 to 2.2-3.24 are each memory 1-1.1-2.1-
3. Write address counter that generates write address for 1-4, 3 is memory 1-11-213.1
-4 is a read start determination unit that determines when to start reading data; 4 is a memory 1-11-2.1-3.1;
This is a read address counter that generates a read address for data from -4.

In the phase adjustment method shown in FIG. 4, each of the data input data DIl to DI4 has the same bit length, but is input at different timings based on the difference in propagation path.

On the other hand, since the reset signals R3Tl to R3T4 are input in synchronization with the first bit of each data input DII to DI4, the write address counter 2-1.2-2.2-3
．． i4 generates a write address for each memory 1-1.1-2.1-3.1-4 by starting counting in response to the corresponding reset signal R3Tl-R3T4, thereby writing the memory 1- 1.1-2゜1
-3. Writing of each data input DIl to Dl4 in 1-4 is performed.

The read start determination unit 3 receives each reset signal R3T1 to
Among R3T4, detect the slowest manually operated one,
Start the read address counter 4. As a result, a read address is given to each memory 1-1.1-2゜1-3.1-4, so each memory 1-1.1
Reading is performed simultaneously from -2.1-3°1-4, and data outputs DO1 to DO4 are generated. Therefore, by the phase adjustment method shown in FIG. 4, data frames of four channels can be synchronized and output.

[Problems to be Solved by the Invention] In the conventional phase adjustment method shown in FIG. Since the frames of data of each channel are synchronized by reading data from each channel, it is necessary to provide a memory for each channel.

However, since the memory into which data is read at the latest timing does not store data, there are problems in that memory usage efficiency is poor and the circuit scale becomes large.

The present invention aims to solve the problems of the prior art, and by detecting the input order of data using a reset signal and selecting the memory, the memory for one channel is reduced and the circuit is The purpose is to provide a phase adjustment method with reduced scale.

[Means to solve the problem]

As shown in FIG. 1, the present invention is equipped with a memory section 1 consisting of n-1 memories for n-channel data input, and a ranking determination section 5 determines the starting position of the n-channel data. The input order of the reset signal synchronized with One channel of timing data is input to the data select section 7, and the write address generation section 2 starts counting according to the judgment result of the ranking judgment section 5, thereby generating respective data write addresses for the memory section 1. The read start determination section 3 determines the input of the slowest reset signal, and the read address counter 4 starts counting according to the determination result of the read start determination section 3, thereby determining the read address for the memory section 1. In the n-channel data output of the read data from the memory unit 1 and the 1-channel data selected by the memory select unit 6, the data select unit 7 determines the input order determined by the order determination unit 5. The output position is determined.

In addition, the ranking determination section 5 uses the reset signal that is first input when the apparatus is started up as the first input to determine the manual ranking.

Furthermore, the ranking determining section 5 uses the reset signal of the specific channel as the first manual input to determine the input ranking.

Furthermore, the order determining section 5 is configured to use the reset signal that is first input after the read address counter 4 finishes counting as the first input to determine the input order.

[Effect]

A memory section consisting of n-1 memories is provided for n-channel data input. Then, the input order of the reset signal synchronized with the beginning of the n-channel data is determined, and according to the result of this determination, the n-1 channel data with the earliest timing is selected and input to the memory section, and the one with the latest timing is selected. By inputting the channel data to the data select section and starting counting according to the input order determination result, a data write address to the memory section is generated and data is written. Furthermore, by determining the input of the slowest of the reset signals and starting counting according to this determination result, a read address for the memory section is generated, data is read from the memory section, and the determined input The output position of the data read from the memory section and the data of one channel selected by the memory select section in the n-channel data output is determined according to the order, and the output is generated, so different input timings can be generated. A phase adjustment method for synchronizing a plurality of data frames can be realized with a smaller circuit size by reducing the memory for one channel.

At this time, the input order may be determined by using the reset signal that is first input when the device starts up as the first input.

Alternatively, the input order may be determined by using the reset signal of a specific channel as the first input.

Furthermore, the input order may be determined by using the reset signal that is first input after counting the read addresses to the memory section as the first input.

[Example] FIG. 2 shows an example of the present invention.
The same parts as in the figure are indicated by the same numbers, 5 is a ranking determining unit that determines the input ranking of reset signals R3Tl to R3T4, and 6 is a memory 1 for each data input DIl to DI4.
- a memory select section that determines the allocation of 1 to 1-3, 7
is 4 from the data read from each memory 1-1 to 1-3 and the input data selected by the memory select section 6.
This is a data select section that selects the data outputs DOI to DO4 of the channels.

FIG. 3 is a diagram showing the timing of each part signal in the embodiment of FIG. 2.

In FIGS. 2 and 3, the ranking determining unit 5 determines the input ranking of the data inputs Ill to DI4 by determining the input ranking of the reset signal RSTI-R3T4. The memory selection section 6 selects the data of the three channels that were input earlier from among the data inputs DIl to DI4 based on the judgment result of the ranking judgment section 50, and stores them in the memory 1-1 respectively.
〜1-3C Two people can input the input data directly into the data selection section 7.

The write address counters 2 to 1 to 2-3 write to the memory 1-2 based on the data manual ranking determination result of the ranking determining unit 5.
Generate write addresses for 1 to 1-3. As a result, each data input in the memory 1-1.1-2.1-3 is written. In addition, memory 1-1.1
-2.1-3 can read and write data asynchronously by using dual ports RA and M.

The read start determination unit 3 receives each reset signal R3T1 to R3T1.
Among 3T4, the one inputted latest is detected to determine the start of reading, and the read address counter 4 is activated. The read start determination unit 3 includes, for example, latches corresponding to each of the reset signals R3Tl to R3T4 and an AND circuit that calculates the logical product of the outputs of each latch, detects when all reset signals are input, and starts reading. The start may be determined. Alternatively, the start of reading may be determined at the time of input ranking determination of the last reset signal in the ranking determination unit 5.

As a result, a read address is given to memory 1-L 1-2.1-3, and data is read out from each memory 1-1.1-2.1-3 at the same time. .

The data selection unit 7 selects four channels from the data read out from each memory 11 to 1-3 and the human data selected by the memory selection unit 6 based on the data input ranking determination result from the ranking determination unit 5. Data output DOI~D
Data matching the position of O4 is selected and output. Therefore, by the phase adjustment method shown in FIG. 2, data frames of four channels can be synchronized and output.

In this case, since the input order of the data inputs DII to DI4 is undefined, in order to determine the input order, it is necessary to specify the first input in one write/read operation. It can be arbitrarily determined which of the data inputs DIl to Dr4 is the first one to determine the input order. For example, the data of the first channel input when the device is started up may be used as the first data to determine the ranking, or the data of a specific channel may be used as the first data to determine the ranking. You may also do so. Alternatively, the determination may be made with the first data input after the read address counter 4 finishes counting as the first data.

[Effects of the Invention] As described above, according to the present invention, it is possible to realize a phase adjustment method for synchronizing a plurality of data frames having different input timings with a small circuit scale.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing the basic configuration of the present invention, Fig. 2 is a diagram showing an embodiment of the invention, Fig. 3 is a diagram showing the timing of various signals in the embodiment of Fig. 2, and Fig. 4 is a diagram showing the timing of each part signal in the embodiment of Fig. 2. 1 is a diagram showing a conventional phase adjustment method. 1 is a memory section, 2 is a write address generation section, 3 is a read start determination section, 4 is a read address counter, 5 is a ranking determination section, 6 is a memory selection section, and 7 is a data selection section.

Claims (4)

[Claims] (1) A memory unit (1) consisting of n-1 memories for n-channel data input, and a ranking determination unit (1) that determines the input ranking of reset signals synchronized with the beginning of the n-channel data. 5), and according to the judgment result of the ranking judgment section (5), the data of the n-1 channel with the earliest timing is selected and inputted to the memory section (1), and the data of the one channel with the latest timing is selected as data. A memory select section (6) that is input to the select section (7), and a write address that generates a data write address for the memory section (1) by starting counting according to the judgment result of the ranking judgment section (5). a generating section (2); a read start determining section (3) that determines the input of the slowest one of the reset signals; and a reading start determining section (3) that starts counting in accordance with the determination result of the read start determining section (3), thereby increasing the memory count. A read address counter (4) that generates a read address for part (1).
) and n-channel data of the read data from the memory unit (1) and the data of the one channel selected by the memory select unit (6) according to the input order determined by the rank determination unit (5). A phase adjustment method characterized by comprising a data selection section (7) that determines an output position in data output. (2) The phase adjustment method according to claim 1, wherein the order determining unit (5) determines the input order using a reset signal that is first input when the device is started up as the first input. (3) The phase adjustment method according to claim 1, wherein the order determining unit (5) determines the input order by using a reset signal of a specific channel as the first input. (4) The order determining unit (5) determines the input order by using as the first input a reset signal that is input first after the reading address counter (4) finishes counting. Phase adjustment method described in section.