JPS62254256A - Recording system for history of common bus information - Google Patents

Abstract

PURPOSE:To know the temporal relation-ship between the pieces of information in a common bus by using a time information memory which records the time information. CONSTITUTION:The bus information on a common bus 11 is fetched by a bus interface 1 and supplied to a control circuit 2 and a data register 3. The bus information is temporarily stored in the register 3 by the clock received from the circuit 2 and recorded to a prescribed address in a bus information recording memory 8. A time interval selecting circuit 5 divides the output of a clock circuit 4 and outputs them to a synchronizing circuit 6. The circuit 6 detects the synchronization of the time information from the outputs of both circuits 2 and 5 and controls the address of an address control circuit 7 based on said detecting information. Then the writing positions of memories 8 and 9 are decided by the address of the circuit 7 and the time information passed through the circuit 6 is recorded to the memory 9.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a common bus information history recording method, and in particular to a history of information communication between a CPLJ (central processing unit), memory, and l10 (input/output device) on a common bus in an information processing device. This relates to a common bus information history recording method for recording.

Traditionally, this type of information recording method has been such that one bus cycle corresponds to one address in a recording memory, and when a bus cycle occurs, this bus cycle is monitored and written into the memory. It has become. Since bus cycles occur so-called asynchronously, it is not possible to know the time relationship between each bus cycle or the number of times a bus cycle has occurred within a certain period of time.

In this way, in the conventional common bus information history recording method, information on bus cycles that occur asynchronously is only recorded at the time they occur, so the time relationship between the recorded information is completely unknown. There is a drawback.

OBJECTS OF THE INVENTION An object of the present invention is to provide a common bus information history recording system that allows the time relationship of recorded bus information to be known.

Structure of the Invention The common bus information history recording method according to the present invention includes a bus information memory section that records information on the common bus, and a time information memory section that records time information corresponding to the time at each fixed time interval. and controlling recording address positions in the memory section of each piece of information so that the bus information recorded in the bus information memory section and the time information recorded in the time information memory section are correlated with each other. It is said that

1 emperor 3 Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a block diagram of an embodiment of the invention.

In the figure, bus information on a common bus 11 is taken in by a bus interface 1 and supplied to a control circuit 2 and a data register 3. In the data register 3, the bus information is temporarily stored by the clock from the control circuit 2.
This stored information will be recorded at a predetermined location in the memory 8 for recording bus information.

A clock circuit 4 is provided, and the time count output of this clock circuit is frequency-divided by a time interval selection circuit 5, set to a desired time interval, and inputted to a synchronization circuit 6. The output of the control circuit 2 is supplied to the other input of the synchronous circuit 6, and the output of the control circuit 2 is bus information generation timing information indicating the timing when the bus information is taken into the bus interface 1. shall be.

This synchronization circuit 6 detects that the bus information on the common bus and the time information from the time interval selection circuit 5 occur in synchronization, and the address of the address control circuit 7 is controlled based on this detection information. With this address, memory 8.
The writing position of 9 is determined. The time information passed through the synchronization circuit 6 is recorded in the memory 9.

All information on the common bus is temporarily stored in the data register 3 through the bus interface 1 and then recorded in the memory 8. At this time, the data on the common bus is controlled by the address control circuit 7 so that the memory address is updated one by one. be done.

On the other hand, the clock circuit 4 outputs pulses at regular intervals, and the frequency is divided by a counter included in the time interval selection circuit 5.

The time interval selection circuit 5 outputs pulses at constant time intervals selected by an internal time selection switch and selector. For example, when the output of the time circuit 4 is a pulse with a time interval of 1 microsecond, the output of the time interval selection circuit 5 can be obtained with an interval of 2 microseconds, 4 microseconds, 8 microseconds, etc. . Time interval selection circuit 5
The output pulses of are synchronized with information from the common bus by a synchronization circuit 6. That is, if the output pulse of the time interval circuit 5 is input when the common bus information is input, the common bus information and the time interval information are recorded at the same address in the memories 8 and 9, respectively.

If the common bus information and the output pulse of the time interval selection circuit 5 are obtained without matching in time, they are recorded at different addresses in the memories 8 and 9, respectively.

FIG. 2 shows a common bus information history recording device 110 (abbreviated as a monitor in the figure) according to the embodiment of the present invention shown in FIG.
indicates the data processing device to which the common bus 1 is connected.
In addition to the monitor 10, the CPU 12, main memory 13, and l1014 are connected to the computer 1.

Effects of the Invention As described above, according to the present invention, by recording time information in addition to common bus information in memory, it is possible to extremely count the number of times common bus information that occurs asynchronously occurs within a fixed time interval. This has the effect of being easily known, making it possible to perform data analysis, performance analysis, etc. in the event of a failure of the information processing device.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a system block diagram of an information processing apparatus to which the present invention is applied. Explanation of symbols of main parts 4... Clock circuit 6... Synchronous circuit

Claims (1)

[Claims] A bus information memory section that records information on a common bus and a time information memory section that records time information corresponding to the time at regular time intervals are provided, and the bus information recorded in the bus information memory section and the time information memory section are provided. A common bus information history recording method characterized in that the recording address position of each piece of information in the memory section is controlled so that the time information recorded in the time information memory section is correlated with each other.