JP3038773B2 - Frame synchronization circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame synchronization circuit in a PCM communication device, and more particularly, to a plurality of multiplexed signals having the same frame configuration.
The present invention relates to a frame synchronization circuit of a PCM communication device.

[Conventional technology]

Conventionally, a frame synchronization circuit of this type has a synchronization pulse information memory (hereinafter referred to as RA) having a W bit capacity for each input / output terminal.
M) has a circuit configuration in which the input signal is sequentially forwarded every W bits and repeated every frame.

This will be described with reference to FIGS. 4 and 5.

FIG. 4 is a block diagram showing an example of a conventional device, and FIG. 5 is a time chart showing an example of input / output signals according to FIG.

As shown in FIG. 4, the frame synchronization circuit includes a buffer circuit 1, 91 to 96, a synchronization protection counter unit 4, a frame counter 5, a synchronization state display unit 6, a synchronization pulse detection unit 30, a synchronization pulse information memory (RAM). 70, and shift register 81
~ 87.

The synchronization protection counter unit 4 determines a protection counter value B in the synchronization state in advance, and every time an irregular value signal is received from the synchronization pulse detection unit 30, the count value is decremented and a protection counter value A (A <B) indicating loss of synchronization. ). When the synchronization protection counter unit 4 receives the coincidence signal in the state of the protection counter value A, it increments the count value to obtain the protection counter value A. The frame counter 5 counts the frame synchronization pulse and indicates the frame position of the received signal S1. The synchronization state display unit 6 displays whether or not frame synchronization is completely achieved in accordance with information from the synchronization protection counter unit 4.

The synchronization pulse detector 30 receives and detects seven frame synchronization pulses from the shift registers 81 to 87, and outputs a match / mismatch to the synchronization protection counter unit 4. The synchronization pulse information memory (RAM) 70 is a writable memory for protecting the synchronization protection counter value of the synchronization protection counter unit 4, the frame counter value of the frame counter unit 5, and the synchronization state value of the synchronization state display unit 6, and Each of the terminals IO1 to IO8 has a memory capacity of W bits.

Shift registers 81 to 87 are for W bits,
The input is connected to the input / output terminals IO1 to IO8 of 0, and the output is connected to the synchronous pulse detector 30. The buffer circuit 1 connects the received signal S1 to the input / output terminal IO1 of the RAM 70. Each of the buffer circuits 91 to 96 connects the output of each of the shift registers 81 to 86 to the input, and outputs the output to the input / output terminals IO2 to IO2 of the RAM 70.
Connect to each of IO7.

As shown in FIG. 5, the received signal S1 is composed of two channels CH1 and CH2 for each W bit in which one frame has frame synchronization pulses F1 to F7. Therefore,
Since the continuous W bits are formed by arranging the frame synchronization bits F1 to F7 at the head and center, the frame synchronization pulses F1 to F1 output sequentially from the W bit shift registers 81 to 87
Each of the F7s line up at a particular time. The synchronization pulse detector 30 detects the frame synchronization pulses F1 to F7, confirms that they are aligned at a specific time, and outputs a coincidence signal. If they are not aligned at the specific time, the synchronization pulse detector 30 outputs a mismatch signal.

As shown in FIG. 5, the frame counter value, the synchronization protection counter value, and the synchronization state are determined by the W of the input / output terminal IO8 of the RAM 70.
Write / read data for two channels in the bit storage area. RA
The reading signal R / W of M70 is input one for one bit code, and the position area is specified by the address signal input separately,
Write or read input signals.

As described above, the synchronization pulse detection unit 30 that distributes and inputs the reception signal S1 for each W bit via the shift registers 81 to 87 detects that the frame synchronization pulses F1 to F7 are aligned and input at a specific time. Therefore, a coincidence signal is output to notify the synchronization protection counter unit 4 that synchronization is in progress. If the frame synchronization pulses F1 to F7 are irregular at this specific time, a non-coincidence signal is output to notify the synchronization protection counter unit 4 of the loss of synchronization.

[Problems to be solved by the invention]

The above-described conventional frame synchronization circuit uses a synchronization pulse information memory as a shift register in order to synchronously output a plurality of frame synchronization pulses in parallel when a frame synchronization pulse is detected. As a result, the number of data input / output terminals of the synchronization pulse information memory is required to be at least the same as the number of frame synchronization pulses. Therefore, when the number of frame synchronization pulses is larger than the number of data input / output terminals of one synchronization pulse information memory, another synchronization pulse information memory is required. Since a pulse information memory must be provided, there is a problem that the circuit scale is increased.

An object of the present invention is to solve the above-described problem by providing a shift register that connects one input / output terminal of a synchronization pulse information memory to an input and connects a predetermined number of outputs in parallel to a synchronization pulse detection unit sequentially. A frame synchronization circuit is provided.

[Means for solving the problem]

A frame synchronization circuit according to the present invention is a frame synchronization circuit of a PCM communication apparatus in which a plurality of signals having the same frame configuration are multiplexed. In the frame synchronization circuit, a synchronization pulse information memory for sequentially storing received signals and storing state information of the received synchronization signals. One shift register for continuously reading and writing the synchronization pulse information stored and held by the synchronization pulse information memory, and outputting a predetermined number of synchronization pulse information while moving forward;
A synchronous pulse detector that receives the output of the shift register as input and outputs coincidence / non-coincidence of the synchronous pulse information at a predetermined time.

〔Example〕

Next, the frame synchronization circuit of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing an example of a 7-bit shift register of FIG. 1, and FIG. 3 is the same S1 signal as the conventional example of FIG. FIG. 4 is a time chart showing an example of forming a frame synchronization pulse according to FIG.

As shown, the S1 signal has two channels (CH1, CH1).
2) The signal of each channel is a frame synchronization pulse F1 to F
7 and 7 bits are multiplexed, and the interval between each frame synchronization pulse is W bits.

As shown in FIG. 1, the frame synchronization circuit includes a buffer circuit 1, a 7-bit shift register 2, a synchronization pulse detection unit 3,
It has a synchronization protection counter section 4, a frame counter section 5, a synchronization state display section 6, and a synchronization pulse information memory (RAM) 7. In FIG. 1, the same components as those shown in FIG. 4 described above, the buffer circuit 1, the synchronization protection counter unit 4, the frame counter unit 5, and the synchronization state display unit 6, are assigned the same reference numerals. The description is omitted.

The RAM 7 has RAM terminals IO1 to IO8 for data input / output, and each terminal has a memory capacity of W bits. RAM7
The RAM terminal IO1 receives the S1 signal via the buffer circuit and is connected to the input of the shift register 2.

As shown in FIG. 2, the shift register 2 has seven flip-flop circuits (FF), sequentially shifts the input of the serial code to each of the output terminals 011, 012... Connect to input 3 The input of the shift register 2 is RA as shown in FIG.
Time slots B1 to B7 for holding the frame synchronization pulses F1 to F7 output from the M terminal IO1 are continuously arranged.
Therefore, in the time slots B1 to B7, data is transferred from the time slot B1 to the time slot B1 to B7 by the shift register 2 every time T.
Move in order.

The output of the shift register 2 is connected to the input of the synchronization pulse detector 3. When the frame synchronization pulses F1 to F7 are input to the time slots B1 to B7, the shift register 2 has an output terminal.
011, 012,... 017, respectively, frame synchronization pulses F1 to F7
Are sequentially output. For example, first, only the output terminal 011 outputs the frame synchronization pulse F1, and then each of the output terminals 011 and 012 outputs each of the frame synchronization pulses F2 and F1. Accordingly, at a specific time, the frame synchronization pulses F7 to F1 are arranged and output to the output terminals 011 to 017, respectively, in order.

The synchronization pulse detector 3 detects the coincidence / mismatch of the frame synchronization pulses with the time when the frame synchronization pulses F7 to F1 are output together from the shift register 2 as a predetermined timing, and connects the detection output to the input of the synchronization protection counter 4. . Subsequent operations are the same as those in the related art, and a description thereof will be omitted.

〔The invention's effect〕

As described above, the frame synchronization circuit of the present invention forms a shift register in which only the frame synchronization pulse operates continuously at one data input / output terminal of the synchronization pulse information memory for detecting the frame synchronization pulse. Each time a frame sync pulse is received, write data is transferred to a shift register in the sync pulse information memory and read out to a shift register outside the sync pulse information memory, and its output is connected to an input of a frame sync pulse detection circuit. With such a configuration, there is an effect that the circuit scale can be reduced as compared with the conventional circuit.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a frame synchronization circuit according to the present invention, FIG. 2 is a block diagram showing an example of a part of FIG. 1, and FIG. 3 is a diagram for explaining the operation of FIG. FIG. 4 is a time chart showing one example, FIG. 4 is a block diagram showing one example of a conventional example, and FIG. 5 is a time chart showing one example for explaining the operation of FIG. 2 ... shift register, 3 ... sync pulse detector, 7 ...
... Synchronous pulse information memory (RAM).

Claims (1)

(57) [Claims] A frame synchronization circuit for a PCM communication apparatus in which a plurality of signals having the same frame structure are multiplexed, a synchronization pulse information memory for sequentially storing received signals and storing state information of the received synchronization signals. A shift register that continuously reads, writes, and forwards a predetermined number of pieces of synchronization pulse information while sequentially reading and writing the synchronization pulse information stored and held in the synchronization pulse information memory; A synchronization pulse detection unit for outputting a match / mismatch of information.