JPH0412864B2 - - Google Patents

Info

Publication number
JPH0412864B2
JPH0412864B2 JP59185188A JP18518884A JPH0412864B2 JP H0412864 B2 JPH0412864 B2 JP H0412864B2 JP 59185188 A JP59185188 A JP 59185188A JP 18518884 A JP18518884 A JP 18518884A JP H0412864 B2 JPH0412864 B2 JP H0412864B2
Authority
JP
Japan
Prior art keywords
communication control
data table
communication
data
external memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP59185188A
Other languages
Japanese (ja)
Other versions
JPS6162957A (en
Inventor
Ei Hayakawa
Hiroyuki Ichikawa
Megumi Koshirae
Shuichi Tonami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP59185188A priority Critical patent/JPS6162957A/en
Publication of JPS6162957A publication Critical patent/JPS6162957A/en
Publication of JPH0412864B2 publication Critical patent/JPH0412864B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/382Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer And Data Communications (AREA)
  • Communication Control (AREA)

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は、通信制御方式に関し、特に通信制御
手順が変更可能、かつ、通信速度が高速可能な通
信制御方式に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a communication control method, and more particularly to a communication control method that allows for changeable communication control procedures and high communication speed.

〔発明の背景〕[Background of the invention]

従来の通信制御方式を説明するための半導体通
信制御装置の構成図を、第2図、第3図に示す。
2 and 3 are block diagrams of a semiconductor communication control device for explaining a conventional communication control method.

第2図において、1は半導体通信制御装置(通
信制御用LSI)、2は受信制御回路、3は送信制
御回路、4は制御回路、5は内部メモリ
(ROM:リードオンメモリ)、6は上位プロセツ
サ、7は受信回線、8は送信回線、9は上位プロ
セツサ6からの制御回線である。
In Figure 2, 1 is a semiconductor communication control device (LSI for communication control), 2 is a reception control circuit, 3 is a transmission control circuit, 4 is a control circuit, 5 is an internal memory (ROM: read-on memory), and 6 is an upper 7 is a receiving line, 8 is a transmitting line, and 9 is a control line from the upper processor 6.

半導体通信制御装置1は、上位プロセツサ6か
らの命令に基づき動作する。上位プロセツサ6か
らの起動後は、半導体通信制御装置1は、データ
受信時には受信制御回路2で受信したデータをも
とに内部メモリ5に格納されている通信制御手順
規定データの内容に従つて制御回路4の制御のも
とで通信制御手順処理を実現し、処理終了後上位
プロセツサ6に報告する。データ送信時について
も同様に、上位プロセツサ6からの命令に従い、
内部メモリ5の内容に従つて制御回路4の制御の
もとで送信制御回路3を介してデータを送信す
る。
The semiconductor communication control device 1 operates based on instructions from the upper processor 6. After startup from the host processor 6, the semiconductor communication control device 1 performs control according to the contents of the communication control procedure regulation data stored in the internal memory 5 based on the data received by the reception control circuit 2 when receiving data. Communication control procedure processing is realized under the control of the circuit 4, and a report is sent to the upper processor 6 after the processing is completed. Similarly, when transmitting data, according to instructions from the upper processor 6,
Data is transmitted via the transmission control circuit 3 under the control of the control circuit 4 according to the contents of the internal memory 5.

また、第3図は、第2図で内部メモリ5に格納
されていた通信制御手順規定データを、外部メモ
リ10に格納する場合であつて、半導体通信制御
装置1に外部メモリ10を接続し、その中に伝送
制御手順規定データを格納する。この場合にも、
第2図と同様の動作を行う。
3 shows a case where the communication control procedure regulation data stored in the internal memory 5 in FIG. 2 is stored in the external memory 10, and the external memory 10 is connected to the semiconductor communication control device 1, Transmission control procedure regulation data is stored therein. Also in this case,
The same operation as in FIG. 2 is performed.

第2図の構成では、半導体通信制御装置1内の
内部メモリ5(ROM)の内容で通信制御手順処
理を規定するため、通信制御手順の変更等に柔軟
に対処出来ない欠点がある。また、第3図に示す
ように、通信制御手順規定データを半導体通信制
御装置1の外部メモリ10内に設置する構成を採
ると、通信制御手順の変更等には柔軟に対処可能
となるが、外部メモリアクセスを行うためのアク
セスタイムの制約から制御回路4の処理速度が制
限され、高速の通信制御手順処理には第3図の構
成をとる半導体通信制御装置1を適用出来ない欠
点がある。
In the configuration shown in FIG. 2, the communication control procedure processing is defined by the contents of the internal memory 5 (ROM) in the semiconductor communication control device 1, so there is a drawback that changes in the communication control procedure cannot be dealt with flexibly. Furthermore, as shown in FIG. 3, if a configuration is adopted in which the communication control procedure regulation data is installed in the external memory 10 of the semiconductor communication control device 1, changes in the communication control procedure etc. can be dealt with flexibly. There is a drawback that the processing speed of the control circuit 4 is limited due to access time constraints for external memory access, and the semiconductor communication control device 1 having the configuration shown in FIG. 3 cannot be applied to high-speed communication control procedure processing.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、これらの欠点を解決するた
め、通信制御手順の変更に対する融通性を持ち、
高速の通信速度を満足する通信制御方式を提供す
ることにある。
An object of the present invention is to provide flexibility in changing communication control procedures in order to solve these drawbacks.
The object of the present invention is to provide a communication control method that satisfies high communication speeds.

〔発明の概要〕[Summary of the invention]

上記目的を達成するために、本発明では、半導
体通信制御装置において、該装置外部には通信制
御手順を規定するデータを格納するデータテーブ
ルを持つ外部メモリを持ち、該装置内部には伝送
制御手順規定データを格納する高速アクセス可能
なデータテーブル、およびデータテーブルの制御
情報を格納しているデータテーブル制御レジスタ
を有し、事前に前記外部メモリ内のデータテーブ
ルに通信制御手順規定データを格納しておき、初
期設定時点または、例えばISDN通信回線を用い
たパケツト通信では、Dチヤンネル用のLAP−
DとBチヤンネル用のLAP−Bの通信手順があ
り、これらを混在した処理を通信制御装置で行う
場合、通信相手の要求により通信手順の変更を必
要とするような特定の状態に遷移する時点で即時
性を要求される処理で用いる通信制御手順規定デ
ータを、前記外部メモリ内のデータテーブルから
高速アクセス可能な前記半導体通信制御装置内の
データテーブルに取り込み、通信制御手順規定デ
ータを用いる処理の発生時点には、前記データテ
ーブル制御レジスタの内容にもとづいて、即時性
が要求される処理の場合には前記半導体通信制御
装置内のデータテーブルをもとに制御を実行し、
上記以外の処理の場合には前記外部メモリ内のデ
ータテーブルをもとに制御を実行することに特徴
がある。
In order to achieve the above object, the present invention provides a semiconductor communication control device, which has an external memory having a data table storing data that defines a communication control procedure outside the device, and a transmission control procedure inside the device. It has a data table that can be accessed at high speed for storing prescribed data, and a data table control register that stores control information for the data table, and the communication control procedure prescribed data is stored in advance in the data table in the external memory. At the time of initial setup or, for example, in packet communication using an ISDN communication line, the LAP-
When there are LAP-B communication procedures for D and B channels, and a communication control device performs processing that involves a mixture of these, there is a point at which the communication procedure changes to a specific state that requires a change in the communication procedure due to a request from the communication partner. Communication control procedure regulation data used in processing that requires immediacy is imported from the data table in the external memory to a data table in the semiconductor communication control device that can be accessed at high speed, and processing using the communication control procedure regulation data is At the time of occurrence, based on the contents of the data table control register, in the case of processing requiring immediacy, control is executed based on the data table in the semiconductor communication control device;
In the case of processing other than the above, a feature is that control is executed based on the data table in the external memory.

〔発明の実施例〕[Embodiments of the invention]

以下、本発明の実施例を図面により説明する。 Embodiments of the present invention will be described below with reference to the drawings.

第1図は、本発明の一実施例を示す通信制御方
式を説明するための半導体通信制御装置構成図で
ある。
FIG. 1 is a configuration diagram of a semiconductor communication control device for explaining a communication control method showing an embodiment of the present invention.

第1図において、1は半導体通信制御装置、2
は受信制御回路、3は送信制御回路、4は制御回
路、6は上位プロセツサ、7は受信回線、8は送
信回線、9は上位プロセツサ6からの制御回線、
10は外部メモリ、11は内部メモリ(RAM:
ランダムアクセスメモリ)、12はデータテーブ
ル制御レジスタ、13は半導体通信制御装置内の
データテーブル、14は外部メモリ内のデータテ
ーブルである。
In FIG. 1, 1 is a semiconductor communication control device, 2 is a semiconductor communication control device;
3 is a reception control circuit, 3 is a transmission control circuit, 4 is a control circuit, 6 is an upper processor, 7 is a reception line, 8 is a transmission line, 9 is a control line from the upper processor 6,
10 is external memory, 11 is internal memory (RAM:
12 is a data table control register, 13 is a data table in the semiconductor communication control device, and 14 is a data table in external memory.

外部メモリ内のデータテーブル14には、通信
制御手順規定データを事前に設定しておき、初期
設定あるいは特定の状態に遷移した時点に、即時
性を要求される処理で用いる通信制御手順規定デ
ータを、外部メモリ内のデータテーブル14から
半導体通信制御装置内のデータテーブル13に転
送する。このことにより、外部メモリ10の内容
修正により、容易に通信制御手順を変更できる。
Communication control procedure regulation data is set in advance in the data table 14 in the external memory, and communication control procedure regulation data used in processing that requires immediacy is set at the initial setting or at the time of transition to a specific state. , is transferred from the data table 14 in the external memory to the data table 13 in the semiconductor communication control device. This allows the communication control procedure to be easily changed by modifying the contents of the external memory 10.

半導体通信制御装置1は、上位プロセツサ6か
らの命令に基づき動作する。データ受信時には、
受信回線7からの受信データを受信制御回路2で
受信し、受信制御回路2はデータ受信を制御回路
4に報告する。制御回路4は、データテーブル制
御レジスタ12の内容をもとに半導体通信制御装
置内のデータテーブル13の内容を読み込み、そ
の内容をもとに即時性を要求される処理か即時性
を要求されない処理かの判定を行い、即時性を要
求される処理の場合は、半導体通信制御装置内の
データテーブル13のデータをもとに迅速に制御
を実行し、即時性を要求されない処理の場合には
外部メモリ内のデータテーブル14のデータをも
とに制御を実行する。制御回路4は、当該処理終
了後、必要に応じ上位プロセツサ6に上位プロセ
ツサからの制御回線9を介して処理終了を報告す
る。データ送信時には、制御回線9を介した上位
プロセツサ6からの制御回路4への命令に従い、
受信処理と同様に、制御回路4は、即時性を要求
される処理の場合は半導体通信制御装置内のデー
タテーブル13のデータをもとに迅速に制御を実
行し、即時性を要求されない場合には外部メモリ
内のデータテーブル14のデータをもとに制御を
実行し、送信制御回路3を用い送信回線8を介し
てデータを送出する。また、データ送出終了時点
には、送信制御回路3は制御回路4にデータ送出
終了を通知し、制御回路4は、必要に応じ上位プ
ロセツサ6に上位プロセツサからの制御回線9を
介して処理終了を報告する。
The semiconductor communication control device 1 operates based on instructions from the upper processor 6. When receiving data,
Reception data from the reception line 7 is received by the reception control circuit 2, and the reception control circuit 2 reports data reception to the control circuit 4. The control circuit 4 reads the contents of the data table 13 in the semiconductor communication control device based on the contents of the data table control register 12, and based on the contents, selects a process that requires immediacy or a process that does not require immediacy. In the case of processing that requires immediacy, control is quickly executed based on the data in the data table 13 in the semiconductor communication control device, and in the case of processing that does not require immediacy, control is executed quickly based on the data in the data table 13 in the semiconductor communication control device. Control is executed based on data in a data table 14 in memory. After the processing is completed, the control circuit 4 reports the completion of the processing to the upper processor 6 via the control line 9 from the upper processor as necessary. When transmitting data, according to instructions from the upper processor 6 to the control circuit 4 via the control line 9,
Similarly to the reception process, the control circuit 4 quickly executes control based on the data in the data table 13 in the semiconductor communication control device when processing requires immediacy, and when processing does not require immediacy. performs control based on the data in the data table 14 in the external memory, and sends out data via the transmission line 8 using the transmission control circuit 3. Furthermore, at the end of data transmission, the transmission control circuit 3 notifies the control circuit 4 of the completion of data transmission, and the control circuit 4 instructs the upper processor 6 to terminate processing via the control line 9 from the upper processor as necessary. Report.

このように、半導体通信制御装置1を構成する
際に、通信制御手順を規定するデータであるデー
タテーブル14を格納する外部メモリ10と、半
導体通信制御装置1内に高速でアクセス可能な小
規模なデータテーブル13と、それらを制御する
データテーブル制御レジスタ12を持ち、初期設
定あるいは特定の状態に遷移した時点に即時性を
要求される処理で用いる通信制御手順規定データ
を外部メモリ内のデータテーブル14から半導体
通信制御装置内のデータテーブル13に転送して
制御することにより高速の通信制御手順処理が可
能となる。
In this way, when configuring the semiconductor communication control device 1, the external memory 10 that stores the data table 14, which is data that defines the communication control procedure, and the small-scale memory that can be accessed at high speed are installed in the semiconductor communication control device 1. It has a data table 13 and a data table control register 12 that controls them, and a data table 14 in an external memory stores communication control procedure regulation data used in processing that requires immediacy at the time of initial setting or transition to a specific state. By transferring the data from the data table to the data table 13 in the semiconductor communication control device for control, high-speed communication control procedure processing becomes possible.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明によれば、通信制
御手順の変更に対する融通性を持つようになり、
高速の通信速度を満足する通信制御方式が実現で
きる。
As explained above, according to the present invention, it is possible to have flexibility in changing the communication control procedure,
A communication control method that satisfies high communication speeds can be realized.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例を示す通信制御方式
説明図、第2図、第3図は従来の通信制御方式説
明図である。 1:半導体通信制御装置、2:受信制御回路、
3:送信制御回路、4:制御回路、5:内部メモ
リ、6:上位プロセツサ、7:受信回線、8:送
信回線、9:制御回線、10:外部メモリ、1
1:内部メモリ、12:データテーブル制御レジ
スタ、13:半導体通信制御装置内のデータテー
ブル、14:外部メモリ内のデータテーブル。
FIG. 1 is an explanatory diagram of a communication control system showing an embodiment of the present invention, and FIGS. 2 and 3 are diagrams explanatory of a conventional communication control system. 1: semiconductor communication control device, 2: reception control circuit,
3: Transmission control circuit, 4: Control circuit, 5: Internal memory, 6: Upper processor, 7: Receiving line, 8: Transmitting line, 9: Control line, 10: External memory, 1
1: internal memory, 12: data table control register, 13: data table within the semiconductor communication control device, 14: data table within external memory.

Claims (1)

【特許請求の範囲】[Claims] 1 半導体通信制御装置において、該装置外部に
は通信制御手順を規定するデータを格納するデー
タテーブルを持つ外部メモリを持ち、該装置内部
には伝送制御手順規定データを格納する高速アク
セス可能なデータテーブル、および該データテー
ブルの制御情報を格納しているデータテーブル制
御レジスタを有し、事前に前記外部メモリ内のデ
ータテーブルに通信制御手順規定データを格納し
ておき、初期設定時点または、例えば、ISDN通
信回線を用いたパケツト通信では、Dチヤネル用
のLAP−DとBチヤネル用のLAP−Bの通信手
順があり、これらを混在した処理を通信制御装置
で行う場合、通信相手の要求により通信手順の変
更を必要とするような特定の状態に遷移する時点
で、即時性を要求される処理で用いる通信制御手
順規定データを、前記外部メモリ内のデータテー
ブルから高速アクセス可能な前記半導体通信制御
装置内のデータテーブルに取り込み、通信制御手
順規定データを用いる処理の発生時点には、前記
データテーブル制御レジスタの内容にもとづい
て、即時性が要求される処理の場合には、前記半
導体通信制御装置内のデータテーブルをもとに制
御を実行し、前記以外の処理の場合には前記外部
メモリ内のデータテーブルをもとに制御を実行す
ることを特徴とする通信制御方式。
1. A semiconductor communication control device has an external memory having a data table storing data specifying communication control procedures outside the device, and a high-speed accessible data table storing data specifying transmission control procedures inside the device. , and a data table control register storing control information of the data table, and communication control procedure regulation data is stored in the data table in the external memory in advance, and at the time of initial setting or, for example, ISDN In packet communication using a communication line, there are communication procedures for LAP-D for the D channel and LAP-B for the B channel, and when a communication control device performs processing that involves a mixture of these, the communication procedure can be changed depending on the request of the communication partner. The semiconductor communication control device can access communication control procedure regulation data used in processing requiring immediacy from a data table in the external memory at high speed at the time of transition to a specific state that requires a change in the communication control device. Based on the contents of the data table control register, at the time of occurrence of a process using the data table in the semiconductor communication control device and using communication control procedure regulation data, if the process requires immediacy, A communication control method characterized in that control is executed based on a data table in the external memory, and in the case of processing other than the above, control is executed based on a data table in the external memory.
JP59185188A 1984-09-04 1984-09-04 Communication control system Granted JPS6162957A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59185188A JPS6162957A (en) 1984-09-04 1984-09-04 Communication control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59185188A JPS6162957A (en) 1984-09-04 1984-09-04 Communication control system

Publications (2)

Publication Number Publication Date
JPS6162957A JPS6162957A (en) 1986-03-31
JPH0412864B2 true JPH0412864B2 (en) 1992-03-05

Family

ID=16166388

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59185188A Granted JPS6162957A (en) 1984-09-04 1984-09-04 Communication control system

Country Status (1)

Country Link
JP (1) JPS6162957A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6373737A (en) * 1986-09-16 1988-04-04 Nec Corp Switching system for device attribute in data communication
JPH0193236A (en) * 1987-10-02 1989-04-12 Yokogawa Electric Corp Communication system

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52112240A (en) * 1976-03-17 1977-09-20 Fujitsu Ltd Data processing unit
JPS5472644A (en) * 1977-11-22 1979-06-11 Nec Corp Remote data communication processing device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52112240A (en) * 1976-03-17 1977-09-20 Fujitsu Ltd Data processing unit
JPS5472644A (en) * 1977-11-22 1979-06-11 Nec Corp Remote data communication processing device

Also Published As

Publication number Publication date
JPS6162957A (en) 1986-03-31

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