JPS62114050A - Communication control equipment - Google Patents

Abstract

PURPOSE:To execute monitoring of the use of a common bus control part by a central processor, and to reduce a load by providing a line control part register for receiving an instruction from the central processor, on the common bus control part in accordance with the line. CONSTITUTION:A start instruction of a line from a central processor is set to a line control register 3-11 in a common bus control part 3-1 of a communication control device 3 through a common bus 5. The line control register 3-11 is provided in accordance with the line, and when the start instruction is executed, a processing request to a processing part 3-2 is generated through a transfer control part 3-12. The processing part 3-2 outputs an address of a main storage device and a transfer request to the transfer control part 3-12 and a DMA control part 3-13 in order to obtain detailed information related to the start, from the main storage device. The detailed information from the main storage device is stored in a storage part 3-3, and transmission and reception of a data are started thereby.

Description

[Detailed Description of the Invention] [Summary] In a communication control device connected to a central processing unit and a main storage device by a common bus, a line control register for receiving instructions from the central processing unit in a common bus control unit is made line-compatible. In addition, a configuration is shown in which a circuit is provided for performing data transfer with the main memory by switching between cycle steal transfer and program transfer.

[Industrial application field]

The present invention relates to a 1ffi communication control device, and more particularly to a communication control device that efficiently performs startup control from a central processing unit and mixed control of program transfer processing during cycle steal transfer between an internal control unit and a storage unit.

[Prior art and problems to be solved by the invention] Conventionally, the line control register for starting control from the central processing unit is common to all lines. There was a drawback in that it was not possible to control the activation of the line, and that the program in the central processing unit had to monitor the status of the line control register until it was released from use.

Furthermore, in cycle steal transfer, the line on which the program is to be transferred is forced to wait until the specified number of bytes have been transferred.

Lines that transfer programs transfer one byte or several bytes at a time, and if the cycle steal operation is not completed during that time, the transfer will not be possible and an overrun will occur. Therefore, lines that accumulate large amounts of data and transfer them by cycle steal are ,
There was a drawback that there were restrictions on accommodating a mixture of lines for transferring programs of small amounts of data.

[Means for solving problems]

In order to solve the above points, the present invention provides a central processing unit (1
), a communication control device (3) connected to a common bus (5) together with a main storage device (2), and a common bus control unit (3-
1), a processing section (3-2), and a storage section (3-3) are connected to each other by an internal bus (3-5). -1), a line control register (3-11) which is provided corresponding to the line and receives and holds various instructions from the central processing unit (1);
and a DMA that controls data transfer with the main storage device (2).
a control unit (113); and a transfer control unit (3-12) that controls data transfer between the processing unit (3-2) and the storage unit (3-3); The I control unit (3-13) includes a cycle steal transfer unit (10), a program transfer unit (11), and a transfer switching unit (12) that switches between cycle steal transfer and program transfer, and the transfer control unit By controlling the bipedal transfer switching unit (12) between (3-12) and the interval between cycle steal transfers, it is possible to switch from cycle steal transfer to program transfer and return from program transfer to cycle steal transfer. It is characterized by being configured as follows.

[For production]

In the present invention, in a 1tTl communication control device that is connected to a central processing unit and a main storage device by a common 1m bus, a line-side register for receiving instructions from the central processing unit is provided in the common bus control unit for each line. , a circuit is provided for switching data transfer between cycle steal transfer and program transfer to and from the main memory.

This makes it possible to set startup instructions from the central processing unit directly to the line control register corresponding to the line without waiting, and also allows program transfer to be performed during cycle steal transfer. It is possible to reduce the load on the device and improve processing capacity when different transmission control procedures coexist.

〔Example〕

FIG. 3 shows an example of the configuration of an information processing system to which the present invention is applied, where ■ is a central processing unit, 2 is a main storage device, 3 is a communication control device, 4 is a peripheral device, and 5 is connected to each device. It is a common bus.

FIG. 1 shows the internal configuration of a communication control bag W3 according to an embodiment of the present invention, in which 3-1 is a common bus control section, 3-2 is a processing section, 3-3 is a storage section, and 3-4 is a line. A control section, 3-5 is an internal bus, 3-11 is a line control register group, 3-12 is a transfer control section, and 3-13 is a DMA control section.

Central processing unit 1. In a system in which a main storage device 21, a communication control device 3, and a peripheral device 4 are connected to a common bus 5,
A line activation instruction from the central processing unit 1 is set in the line control register 3-11 in the common bus control unit 3-1 of the 1ffl communication control unit 3 via the common bus 5. The line control register 3-11 is provided corresponding to the line, and when a start-up instruction is given, the transfer control unit 3-12 is immutable and the processing unit 3-2
A processing request is generated. The processing unit 3-2 uses the transfer control unit 3-12 to obtain detailed information regarding startup from the main storage device 2.
, issues the address of the main storage device 2 and a transfer request to the DMA control unit 3-13.

The detailed information from the main storage device 2 is stored in the storage section 3-3, and data transmission and reception is thereby started.

Data transmission/reception is carried out according to a transmission control procedure in which, in the case of a bit-oriented procedure, the transfer unit of cycle steal is, for example, 256 bytes, and in the case of the byte-oriented procedure, the unit of program transfer is, for example, 4 bytes.

In the case of the conventional method, the bit-oriented line is connected to the DMA control unit 3-13 for data transfer.
While cycle stealing was being performed between the storage unit 12 and the storage unit 3-3, data could not be transferred from the Hyde-Oriented line, making it impossible to accommodate the high-speed line.

In the case of the present invention, circuits for cycle steal transfer and program transfer are provided, and the transfer control unit 3-12 performs the program transfer operation between cycle steal operations.

FIG. 2 shows the internal configuration of the DMA control unit 3-13, in which 3-12 is a transfer control unit, 3-13 is an I) MA control unit, 3-51 is a data bus in the internal bus, and 3- 52 is a control bus in the internal bus, 5-1 is a data bus in the common bus, 5-2 is an address bus in the common bus, 10 is a program transfer section, 11 is a cycle steal transfer section, 12 is a multiplexer MPX, and 13 is a data buffer. Register DBR,14 is memory address register MARO115 is byte count register BCR1
16 is a +0 circuit, 17 is a -0 circuit, 18 is a memory address register MΔR1, and 19 is a +0 circuit.

As shown in FIG. 2, the memory address register MAR01 for cycle steal transfer to the control unit 3-13
There is a 4I byte count register and a memory address register MAR118 for program transfer.

Data buffer register DBR13 is commonly used in any transfer mode.

Memory address register MAR. 14 and MAR.

One of 18 is selected by multiplexer MPX12. All these controls are managed by the transfer control unit 3-12.

Data transfer with the processing unit 3-2 is performed using an IN10UT command, and data transfer with the storage unit 3-3 is performed using a cycle steal.

〔Effect of the invention〕

According to the present invention, there is no need for the central processing unit to monitor when the common bus control unit is in use, thereby reducing the load on the central processing unit, and in internal control, program transfer can be performed during cycle steal transfer. It is possible to efficiently accommodate a mixture of lines with different transmission control procedures, and it is also possible to process high-speed lines.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the internal configuration of a communication control device according to an embodiment of the present invention, FIG. 2 is a diagram showing the internal configuration of a DMA control section, and FIG. 3 is a diagram showing the configuration of an information processing system to which the present invention is applied. It is a figure which shows an example. In the figure, 3 is a communication control device, 3-1 is a common bus control unit, 3
-2 is a processing unit, 3-3 is a storage unit, 3-11 is a line control lens group, 3-12 is a transfer control unit, 3-13 is a DMA
This is the control section.

Claims (1)

[Claims] A communication control device (3) connected to a common bus (5) together with a central processing unit (1) and a main storage device (2), the common bus being connected to the common bus (5). Control unit (3-1)
, a communication control device (
In 3), the common bus control unit (3-1) is provided with a line control register (3-11) corresponding to the line, which receives and holds various instructions from the central processing unit (1).
and a DMA that controls data transfer with the main storage device (2).
a transfer control unit (3-12) that controls data transfer between the control unit (3-13), the processing unit (3-2), and the storage unit (3-3); -13) includes a cycle steal transfer unit (10), a program transfer unit (11), and a transfer switching unit (12) that switches between cycle steal transfer and program transfer, and the transfer control unit (3-12) By controlling the transfer switching unit (12) between the cycle steal transfer and the cycle steal transfer, switching from the cycle steal transfer to the program transfer and returning from the program transfer to the cycle steal transfer is possible. communication control device.