JPH01189258A - Communication control device - Google Patents

Abstract

PURPOSE:To improve a processing speed and to expand a function by connecting plural serial communication processing circuits to execute protocol processings to be respectively different or the same protocol to one DMA controller in parallel. CONSTITUTION:A receiving frame sent through respective channels by an LSI for controlling a communication is resolved into individual fields by frame processing circuits 1a-1c. A receiving condition signal, etc., are generated, and the frame processing circuits 1a-1c are set so as to execute the processings of three ways, for example, protocols A, B and C, respectely. Receiving data for plural channels are time-division-multiplexed by a TDM circuit 2 and stored into an FIFO memory 3. A DMA control circuit 4 grasps the condition of the receiving frame according to the protocol, sets a transfer parameter, and DMA- transfers the receiving data to a host memory. For the DMA controller, a null time for waiting for a processing completion can be reduced, and the processings of plural channels can be simultaneously executed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a technology that is particularly effective when applied to data communication technology and digital communication processing. A discussion of effective techniques that can be used.

[Prior Art] Conventionally, a serial communication control unit constituting a local area network includes a communication processing circuit that performs serial communication processing, a FIFO memory that holds transmitted and received data, and this FIFO memory and host memory (main memory). It has been proposed that a DMA controller that performs DMA transfer between
2-31456).

[Problems to be Solved by the Invention] In the communication control unit (LSI), there is only one communication processing circuit that performs serial communication processing,
It is configured to perform communication processing only for one specific protocol. For example, if the communication processing circuit is LAP
If the mode is set to process B, LAPB processing is performed on the received frame, the DMA controller waits for the processing in the communication processing circuit to finish, and when the processing is finished, it transfers the received data from the FIF○ memory. It was supposed to take it out and transfer the data to host memory. As described above, in the conventional system, the waiting time until the end of processing in the communication processing circuit of the DMA controller is long, resulting in blank time during which the operation is stopped, and the processing capacity is reduced.

Additionally, since it can only process a single protocol, systems that want to connect multiple channels with different protocols have the problem of having to prepare a communication control unit with different protocol processing functions for each channel. Ta.

An object of the present invention is to improve processing speed and expand functionality by enabling processing of multiple channels and multiple protocols at the same time in a communication control unit that constitutes a digital communication network.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for Solving the Problems] Representative inventions disclosed in this application will be summarized as follows.

In other words, a communication processing circuit performs serial communication processing according to a communication protocol, a DMA control circuit performs DMA transfer of transmitted and received data between FIFO memory and host memory, and a microprogram system performs overall control of these circuits. In a communication unit consisting of a controller, for one DMA controller,
A plurality of serial communication processing circuits each performing different protocol processing or the same protocol are connected in parallel.

[Operation] According to the above means, in each serial communication processing circuit,
Processing is executed in parallel for each protocol, and when the processing is completed, data is sequentially transferred to the DMA controller, so the operations of the DMA controller are multiplexed.

This greatly reduces the idle time during which the DMA controller waits for the serial communication processing circuit to complete processing, making it possible to process multiple protocols on a single LSI, and to simultaneously process multiple channels. This makes it possible to achieve the above-mentioned purpose of increasing the processing speed and functionality of the entire system.

[Example] Hereinafter, by taking the present invention as an example, HDLC (High
Level Data Link Control
An embodiment will be described in which the present invention is applied to a communication control LSI that executes processing according to a protocol called 1 Procedure, which has various subsets.

The communication control LSI of this embodiment has a data transmission system and a data reception system integrally constructed.

The communication control LSI of this embodiment includes a plurality of frame processing circuits 1a, lb, and lc for processing frame data sent from a communication line (channel) and forming frame data to be transmitted, and a plurality of channels. A TDM circuit 2 for time-division multiplexing data from the TDM circuit 2, a FIFO memory 3 for successively capturing and holding data from the TDM circuit 2, and a FIFO memory 3 for transmitting data from the FIFO memory 3 to a host CP.
DMA to data buffer (host memory) managed by U
It is composed of a DMA control circuit 4 for transferring, and a microcontroller 5 using a microprogram control system for overall control.

In the above communication control LSI, a received frame having a configuration as shown in FIG. Status signals etc. are generated. The frame processing circuits 1a to 1c have H
It is set up to be able to process three protocols, A, B, and C, which are subsets of DLC, so that it can process multiple channels at the same time. The frame processing circuits 18 to 1c add the number of bytes of the transfer data and the number of bytes of the transfer data as shown in FIG. A new data string is generated and transferred by adding transfer control information TC such as status information and a channel identifier CD. Then, the received data for multiple channels is time-division multiplexed in the TDM circuit 2, and F
It is stored in the IF○ memory 3.

The DMA control circuit 4 grasps the state of the received frame according to the protocol based on the channel management table set in the microcontroller 5.

It accepts transfer requests, sets transfer parameters such as transfer addresses in the host memory, and transfers received data to the host memory by DMA.

On the other hand, regarding transmission data, the DMA control circuit 4 generates a data string by adding transfer control information TD and a channel identifier CD to the transmission data transferred from the host memory according to the channel management table in the microcontroller 5. and send it to FIF○ memory 3. Then, the TDM circuit 2 distributes the transmission data to the corresponding channels according to the channel identifier CD, and the frame processing circuits 1a to I
Based on the contents of the channel management table in the microcontroller 5, a frame according to a desired protocol is constructed and transmitted on one communication line.

Note that in the above embodiment, a different protocol A is used.

Although frame processing circuits 1a, lb, and IC for B and C are provided, a plurality of frame processing circuits for the same protocol may be provided.

Further, the number of frame processing circuits is not limited to three, and two or four or more may be provided.

As mentioned above, frame processing units are provided corresponding to multiple protocols or multiple channels, and they are connected in parallel to one DMA control unit. As a result, the idle time during which the DMA controller waits for the serial communication processing circuit to complete processing is greatly reduced, and processing for multiple channels can be executed simultaneously, which improves the overall system efficiency. This has the effect of improving processing capacity.

In addition, frame processing units are provided for multiple protocols, and they are connected in parallel to one DMA control unit, so processing for multiple protocols can be executed on a single SI, and communication This has the effect of improving the functionality of the control LSI.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, in the above embodiment, a system in which a communication processing circuit and a DMA controller are formed on the same chip has been described, but it is of course applicable to a case where these are formed on separate LSIs.

In addition, although the embodiment has been described as an example in which it is applied to a device that performs serial communication according to the HDLC protocol, the communication protocol is not limited to HDLC, but can also be applied to serial communication control according to other formats of protocols. can do.

In the above description, the invention made by the present inventor was mainly applied to a serial communication control device constituting a local area network, which is the background field of application, but the invention is not limited thereto. It can be used in general communication control devices.

[Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below.

In other words, in the communication control unit that constitutes the digital communication network, the idle time during which the DMA controller waits for the processing of the serial communication control circuit to finish is significantly reduced, and the processing of multiple protocols can be executed on a single LSI. It is also possible to execute processing for multiple channels simultaneously, and it is possible to improve the processing speed and functionality of the entire system.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a configuration example of a transmission/reception frame of a serial communication control device according to the present invention. m (B) is a diagram showing an example of the format of data transferred between the frame processing circuit and the DMA controller. 1a to 1c...Communication processing circuit (frame processing circuit)
, 2... TDM circuit, 3... FIFO memory,
4...DMA control path, 5...Micro control unit. Frame processing circuit 7ry 4th figure 2

Claims (1)

[Claims] 1. A communication processing circuit that performs serial communication processing according to a communication protocol, a DMA control circuit that transfers transmitted and received data by DMA between a FIFO memory and a host memory, and an overall control thereof. 1. A communication control device comprising a control section and a DMA controller, characterized in that a plurality of communication processing circuits are prepared and connected in parallel to one DMA controller via a multiplexing circuit. . 2. The communication control device according to claim 1, wherein each of the plurality of communication processing circuits is configured to perform different protocol processing. 3. The communication control device according to claim 1, wherein at least some of the plurality of communication processing circuits are configured to perform the same protocol processing.