JP2855542B2 - Communication control device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data communication technique, and more particularly to a technique which is particularly effective when applied to a protocol control of bit-synchronous communication, for example, serial communication forming a local area network The present invention relates to a technology that is effective for use in the configuration of a control device.

[Prior Art] Conventionally, as a serial communication control unit constituting a local area network, as shown in FIG. 4, a line control circuit 61 for performing serial communication processing, a FIFO memory 62 for holding transmission / reception data, and this FIFO There has been proposed a configuration including a DMA controller 63 for executing a DMA transfer between a memory and a main memory (main storage device) and a control unit 64 for integrally controlling these and performing protocol processing (Intelligent). Published by “LAN COMPONENTS USER′SM
ANUAL ”p.2-62 to p.2-63).

[Problems to be Solved by the Invention] In the above conventional communication control device, a transmission byte machine 66 for constructing a transmission frame through a transmission FIFO (first-in first-out) memory 62a in which a transmission command and transmission data are common. Is forwarded to The received data and status decomposed and generated by the receiving byte machine 67 are transferred to the DMA controller 63 through the common receiving FIFO 62b. Moreover, the transmission command, transmission data, reception data and status are all transmitted via one bus 65.
The transfer is performed between the DMA controller 63 and the line control circuit 61.

The communication control apparatus performs line control for only one channel, and there is no particular problem in protocol processing such as Ethernet (Ethernet) in which transmission and reception are separately performed in a time-division manner.

However, line control of multiple channels, and processing of multiple types of protocols by one CPU,
When processing a protocol that permits transmission and reception at the same time, such as a DLC (high-level data link control) protocol, there was a problem that the processing could not be speeded up due to a spring.

An object of the present invention is to provide an architecture of a communication control device that speeds up protocol processing and facilitates multi-channel operation.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[Means for Solving the Problems] The outline of a typical invention among the inventions disclosed in the present application is as follows.

That is, the reception FIFO is divided into an event FIFO for storing the result of the event analysis of the reception frame and a reception data FIFO for storing the reception data, and the transmission FIFO is divided into a command FIFO for storing the command code and a transmission data for storing the transmission data. In addition to being divided into FIFOs, the buses connected to the FIFOs are also divided into event buses with event codes, command buses with command codes, and data buses with transmission / reception data. It enables data transfer.

[Operation] According to the above-described means, the event FIFO stores an event sequence corresponding to one event in one received frame, and the received data is stored in another dedicated FIFO. The maximum transfer speed is not limited by the maximum processing time per frame as in the sequential frame processing, and the speed can be increased.

In addition, since events, commands, and data are transferred through different buses, contention on the bus is reduced, and the protocol control unit does not have the overhead of switching between events, commands, and data as in the shared bus system, so that simultaneous processing can be performed. Since it becomes possible, high speed becomes possible. In addition, since each bus can be controlled by one CPU, it is advantageous in terms of cost when multi-channels are used.

[Embodiment] FIG. 1 shows an embodiment of a communication control apparatus according to the present invention.

Although not particularly limited, each circuit block surrounded by a one-dot chain line 20 is formed on one semiconductor chip such as a single crystal silicon substrate.

The communication control device 20 of this embodiment includes, but is not limited to, four line control units, enables connection of four serial communication lines, and functions as a four-channel protocol controller capable of transmitting and receiving in parallel with each other. Has functions.

In FIG. 1, reference numerals 11a, 11b, 11c, and 11d denote a function of assembling a transmission frame, converting the frame into serial data, and transmitting the frame, converting a received frame (serial data) into parallel data, separating the data into fields, and The line control unit has a function of storing received data or analyzing an event to generate and store an event code. The line control units 11a to 11d are connected to a DMA controller 13 via a data bus 12a and to a protocol control unit 14 via two buses (an event bus 12b and a command bus 12c).

The DMA controller 13 reads out transmission data from the external main memory 22 via the system bus 21 and transfers it to the designated line control unit (one of 11a to 11d) in accordance with a transfer command from the protocol control unit 14. And a function of transferring block data received by any one of the line control units to an external main memory 22 via an internal data bus 12a and a system bus 21.

The protocol control unit 14 is, for example, a microprogram-based control unit and an execution unit, a CPU 41 in the form of a general-purpose microprocessor including registers and the like, an event code EVT supplied from the line control units 11a to 11d, and a previous state number. From the reception state table 42 that generates the next operation code OP and its state number ST.No to be executed by the CPU 41, and the next command code CMD and state number from the control code CD output from the CPU 41 and the previous state number And a transmission state table 43 for generating ST.No.

Above reception state table 42 and transmission state table
Reference numeral 43 denotes a ROM (Read Only Memory). The next state number ST.No of the codes output from the tables 42 and 43 is latched by the latch circuits 44a and 44b, respectively, and the next table is referred to. Sometimes supplied as part of an address. At the preceding stage of the reception state table 42, the state number ST.No latched by the latch circuit 44a and the event code supplied from the line control units 11a to 11d via the event bus 12b are combined to form an address signal. A multiplexer 45a for supplying to the reception state table 42 is provided. Further, in the preceding stage of the transmission state table 43, a control code CD output from the CPU 41 is provided.
And a previous state number ST.No latched by the latch circuit 44b, and a multiplexer 45 for supplying the same to the transmission state table 43 as a reference address.
b is provided.

Here, the event code means that the state (control state) of the communication control device 20 is, for example, disabled state → opening flag transmission → address transmission → data transmission → CR
In the case of a transition such as transmission of C → transmission of a closing flag, a code indicates a state transition factor such as generation of an enable signal and completion of preparation of data in a data FIFO.

If it is determined in the address transmission state that no data is contained in the FIFO, the process proceeds to underrun processing. Therefore, “no FIFO data” is also one of the events.

In this way, if the previous state and the type of event that causes the state transition are known, the CPU 4
The processing to be executed by 1 is inevitably determined. Although such processing can be executed by a micro sequence of the CPU 41, in the above embodiment, the reference tables 42 and 43 are provided,
It is realized by hardware.

FIG. 2 shows a configuration example of the line control units 11a to 11d.

The line control units 11a to 11d monitor the opening flag, receive serial data in synchronization with the reception clock RXC, convert this into parallel data, and convert the reception frame having the field configuration as shown in FIG. A frame decomposing unit 31 having a function of decomposing each field,
A frame as shown in FIG. 3 in which the transmission data transferred from the main memory 22 by the DMA controller 13 is put in the information field IFM is assembled, converted into serial data, and output to the outside in synchronization with the transmission clock TXC. A frame assembly 32 is provided.

The functions of the frame disassembling unit 31 and the frame assembling unit 32 are the same as those provided in the conventional communication control device, and can be realized by the same hardware.

However, in this embodiment, the FIFO memory on the receiving side is divided into two parts, a receiving data FIFO 35a for receiving data and an event FIFO 35b for entering an event code, and the FIFO on the transmitting side stores transmission data. Transmission data FIFO
36a and a command FIFO 36b for storing command data. The code of the information field IFM in the received frame decomposed by the frame decomposing unit 31 is stored in the received data FIFO 35b via the prebuffer 33.

Also, the control field of the decomposed received frame
The CNT code is sent to the event analysis unit 34, where an event code is generated and stored in the event FIFO 35a. By passing the received data through the pre-buffer 33, the event analysis unit
The time delay required to determine the event code in 34 can be adjusted and stored in the FIFO simultaneously with the storage of the event code. At this time, it is preferable that the received data be put in the FIFO with a flag indicating the correspondence with the event code.

In this embodiment, the reception data FIFO 35a and the event FIF
O35b is the DMA controller 13 or protocol controller 14
From the data bus 12a and the event bus 12b via ports 39a and 39b controlled by signals from the
The code stored in the FO is transmitted to the protocol controller 14 via the buses 12a and 12b at the request of the DMA controller 13.
Transferred to

On the other hand, the transmission data FIFO 36a and the command FIFO 36b are
Data bus 12a and command bus 12 via ports 39c and 39d
c, and the transmission data transferred from the main memory 22 by the DMA controller 13 is the transmission data.
Command codes sent from the FIFO 36a and from the protocol control unit 14 are sequentially stored in the command FIFO 36b.
Then, the command code stored in the command FIFO 36b is sent to the command analysis unit 37 and decoded, and the corresponding process is notified to the command execution unit 38. Then, the command execution unit 38 forms a control signal for sequentially operating the frame assembling unit 32 including the flag generation circuit, the abort generation circuit, the CRC code generation circuit, the parallel-serial converter, etc., according to the processing content, Output sequentially.

As a result, in the frame assembling unit 32, the address field ADD and the control field CNT are generated after the opening flag Fo, the transmission data in the transmission data FIFO 36a is added as the information field IFM, and the CRC as the check field FCS is finally set. A frame as shown in FIG. 3 to which a code and a closing flag Fc are added is formed and output. However, it is not always necessary to add a CRC code.

In the above embodiment, the buses in the communication control device 20 are the data bus 12a, the event bus 12b, and the command bus 12c.
However, the present invention is not limited to this, and two types of buses may be used, and one may carry transmission data and the other may carry an event code or a command code.

Further, in the embodiment, the FIFO on the receiving side is replaced with the reception data FIFO 35a.
And the event FIFO 35b are provided separately. However, in a communication control device which analyzes a received frame and forms a status, a status FIFO for storing the status may be provided in addition to the FIFO.

As described above, in the above embodiment, the reception FIFO is used to store the event after the event analysis of the received frame.
The event analysis means and command execution means are divided into a FIFO and a receive data FIFO for storing received data, and the transmit FIFO is divided into a command FIFO for storing command codes and a transmit data FIFO for transmitting data. In this case, the event FIFO stores an event sequence corresponding to one event in one received frame, and the received data is stored in another dedicated FIFO. As described above, the maximum transfer speed is not limited by the maximum processing time per frame, and the line speed is increased.

Also, a bus connected to the FIFO is provided separately for an event bus on which an event code rides, a command bus on which a command code rides, and a data bus on which transmission / reception data rides, and transfers events, commands, and data through different buses. This reduces contention on the bus, eliminates the overhead of switching events, commands, and data as in the shared bus method, and eliminates the need for protocol processing during DMA transfer of transmitted / received data. In addition, since transmission and reception can be performed simultaneously, the line speed is increased. Furthermore, since each common bus can be controlled by one CPU, if it is desired to increase the number of channels, it is only necessary to increase the number of line control units, which is advantageous in terms of cost. Although the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and various changes can be made without departing from the gist of the invention. Nor. For example, in the above embodiment, four line control units are provided to support four channels, but the number of channels may be three or less or five or more.

Further, in the embodiment, the transmission clock and the reception clock are externally supplied. However, a system clock may be used as the transmission clock, or the reception clock may be formed from the reception data.

In the above embodiment, the system in which the line control unit and the protocol control unit are configured on the same chip has been described. However, it is needless to say that the present invention can be applied to the case where these are formed on separate LSIs.

Further, the embodiment has been described as an example in which the present invention is applied to a device that performs serial communication according to the HDLC protocol. However, the communication protocol is not limited to HDLC, and a bit-synchronous serial communication control device generally follows another type of protocol. Can be applied.

In the above description, the invention made mainly by the inventor has been described in terms of the local area,
Although the present invention has been described as applied to a serial communication control device constituting a network, the present invention is not limited to this and can be used in general communication control devices.

[Effects of the Invention] The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, in the bit-synchronous serial communication control device, it is possible to speed up the protocol processing and easily realize multi-channel.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a communication control device according to the present invention, FIG. 2 is a block diagram showing an example of a line control unit, and FIG. 3 is a block diagram of data transmitted and received by the communication control device of the present invention. FIG. 4 is a block diagram showing an example of a conventional communication control device. 11a to 11d: Line control unit, 12a: Data bus, 1
2b Event bus, 12c Command bus, 14 Protocol control unit, 44a, 44b Latch circuit, 45a, 45b
Multiplexer.

Claims (3)

(57) [Claims] A line controller for storing transmission data in a FIFO format and a memory for storing reception data in a FIFO format, for constructing and disassembling a transmission / reception frame according to a communication protocol; In a communication control device comprising a DMA control circuit for transferring DNA to and from the main memory and a protocol control unit for controlling the overall control of the DMA control circuit, the rotation control unit is provided separately from the transmission / reception data storage FIFO memory. The FI that stores the event code generated from the received frame
An FO memory and a FIFO memory for storing a command code supplied from the protocol control unit are provided, and the event code memory and the command code memory are provided by separate buses from a bus for transmitting and receiving data. A communication control device connected to a protocol control unit. 2. The communication control device according to claim 1, wherein the event code memory and the command code memory are respectively connected to a protocol control unit by separate buses. 3. The communication control device according to claim 1, wherein a plurality of said line control units are provided, and each of the FIFO memories therein is commonly connected to the corresponding bus.