JPH0491538A - Communication controller - Google Patents

Abstract

PURPOSE:To make the protocol processing speed faster so that multiple channels can be used easily by storing event strings, each event of which corresponds to one received frame, in an event FIFO and received data in another exclusively used FIFO. CONSTITUTION:A reception FIFO is divided into an event FIFO for storing event analyzed results of received frames and received data FIFO for storing received data and a transmission FIFO is divided into a command FIFO for storing command codes and transmitting data FIFO for storing transmitting data. At the same time, buses connected to the above-mentioned FIFOs are also divided into an event bus 12b for carrying event codes, command bus 12c for carrying command codes, and data bus 12a for carrying transmitting/ received data and the buses 12a, 12b, and 12c are driven in parallel with each other so that data can be transferred simultaneously.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data communication technology and a technology that is particularly effective when applied to protocol control of bit synchronous communication, such as serial communication that constitutes a local area network. This invention relates to techniques that are effective when used in the configuration of control devices.

[Prior Art] Conventionally, as a serial communication control unit constituting a local area network, as shown in FIG. A system has been proposed that includes a DMA controller 63 that executes DMA transfer between memory and main memory (main storage device), and a control unit 64 that centrally controls these and performs protocol processing (Intel). Published by rLA
N COMPONENTS tJsER' SM
ANUALJ p, 2-62-p, 2-63).

[Problems to be Solved by the Invention] In the above-mentioned conventional communication control device, the transmission byte machine 66 constructs a transmission frame through a transmission FIFO (first-in, first-out) memory 62a in which transmission commands and transmission data are common. will be forwarded to. Also, the received data and status disassembled and generated by the receiving byte machine 67 are as follows.

It is transferred to the DMA controller 63 through the common reception FIFO 62b. Moreover, all transmission commands, transmission data, reception data, and status are transmitted via one bus 6.
5 to the DMA controller 63 and the line control circuit 61
Transfers were made between.

The above-mentioned communication control device performs line control for only one channel, and also uses Ethernet (Ethernet).
There is no particular problem in protocol processing such as t) in which transmission and reception are performed separately in a time-division manner.

However, line control of multiple channels and multiple types of protocols can be handled by a single CPU,
When processing a protocol that allows simultaneous transmission and reception, such as the HDLC (High Level Data Link Control) protocol, there is a problem in that the bus becomes a bottleneck, making it impossible to speed up the processing.

An object of the present invention is to provide an architecture for a communication control device that speeds up protocol processing and facilitates multichannelization.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for Solving the Problems] Representative inventions disclosed in this application will be summarized as follows.

In other words, the reception FIFO is divided into an event FIFO that stores the results after event analysis of the received frame, and a reception data FIFO that stores the received data.
is divided into a command FIFO that stores command codes and a transmission data FIFO that stores transmission data, and the buses connected to the F'IFO are also divided into an event bus for event codes, a command bus for command codes, and a transmission/reception bus. The bus is separated into a data bus for carrying data, and these buses are driven in parallel so that data can be transferred at the same time.

[Operation] According to the above-described means, the event FIFO stores an event string in which one event corresponds to one received frame, and the received data is stored in another dedicated FIFO. Unlike sequential frame processing, the maximum transfer rate is no longer limited by the maximum processing time per frame, making it possible to increase the speed.

Furthermore, since events, commands, and data are transferred through separate buses, contention on the bus is reduced, and the protocol control section does not have the overhead of switching events, commands, and data as in the shared bus method.
Since simultaneous processing becomes possible, speeding up becomes possible. Moreover, since each bus can be controlled by one CPU, it is advantageous in terms of cost when increasing the number of channels.

[Embodiment] FIG. 1 shows an embodiment of a communication control device according to the present invention.

Although not particularly limited, each circuit block surrounded by a dashed line 20 in the figure is formed on one semiconductor chip such as a single crystal silicon substrate.

The communication control device 20 of this embodiment is equipped with four line control units, although not particularly limited, and can be connected to four serial communication lines, and functions as a four-channel protocol controller that can transmit and receive data in parallel with each other. Has a function.

In Figure 1, 11 a, 1 l b, 11
c and 11d are functions for assembling transmission frames, converting them into serial data, and transmitting them, and functions for transmitting received frames (
This line control unit has the functions of converting (serial data) into parallel data and separating it into each field, storing the obtained received data, and generating and storing event codes by analyzing events. The line control units lla to 11d are connected to the DM via the data bus 12a.
It is connected to the A controller 13 and to the protocol control unit 14 via two buses (event bus 12b and command bus 12C).

The DMA controller 13 includes a protocol control section 14
According to the transfer command from the external main memory 22 via the system bus 21, the transmission data is read out from the external main memory 22 and transferred to a designated line control unit (one of 118 to lld), or received by any line control unit. The received data is transferred to the internal data bus 12a and system bus 21.
It has a function of block transfer to the external main memory 22 via the main memory 22.

The protocol ff1JflJ unit 14 includes a CPU 41 in the form of a general-purpose microprocessor comprising, for example, a microprogram type control unit, an execution unit, registers, etc., and an event code EVT and previous state number supplied from the line control units lla to 11d. from CPU
The next operation code ○P to be executed in 41 and its state number ST.

A reception state table 42 that generates NO, and a CPU
The next command code CMD and state number ST are determined from the control code CD output from 41 and the previous state number.
, No. , and a transmission state table 43 that generates.

The reception state table 42 and the transmission state table 43 are constituted by ROM (read only memory), and among the codes outputted from each table 42 and 43, the next state number ST and No are respectively stored in a latch circuit 44a and a latch circuit 44a. 44b and supplied as part of the address when the next table is referenced. At the front stage of the reception state table 42, the state numbers ST and No latched in the latch circuit 44a and the event code supplied from the line control units lla to lid via the event bus 12b are combined and used as an address signal. multiplexer 4 for feeding the receive state table 42;
5a is provided.

Furthermore, at the front stage of the transmission state table 43, the CPU 4
The control code CD output from 1 and the latch circuit 44
A multiplexer 45b is provided for synthesizing the previous state numbers ST and No latched in B and supplying the synthesized result to the transmission state table 43 as a reference address.

Note that the event code here means that the state (control state) of the communication control device 20 is, for example, disabled state → opening flag transmission → address transmission → data transmission → C
In the case of a transition such as RC transmission → closing flag transmission, factors of state transition such as generation of an enable signal and completion of preparation of data to the data FIFO are shown in codes.

Note that when it is determined that no data is stored in the FIFO in the address sending state, the process shifts to underrun processing. Therefore, "no FIFO data" is also one of the events.

In this way, if the previous state and the type of event that caused the state transition are known, the next CPU
41 is necessarily determined. Although such processing can be executed by a microsequence of the CPU 41, in the above embodiment, the reference tables 42 and 4
3, and it is realized by hardware.

FIG. 2 shows an example of the configuration of the line control units lla to 11 (I).

The line control units lla to lid monitor the opening flag, receive serial data in synchronization with the reception clock RXC, convert it into parallel data,
A frame disassembly unit 31 having a function of disassembling a received frame having a field configuration as shown in FIG. 3 into each field.
And conversely, the main memory 22 is controlled by the DMA controller 13.
Assemble a frame like the one shown in Figure 3 in which the transmitted data is put into the information field IFM, convert it into serial data, and set the transmission clock T.
It includes a frame assembly section 32 that outputs to the outside in synchronization with the XC.

The functions of the frame disassembly section 31 and the frame assembly section 32 are the same as those provided in a conventional communication control device, and can be realized with similar hardware.

However, in this embodiment, the FIFO memory on the receiving side is
The FIFO on the transmitting side is divided into two: a receive data FIFO 35a that stores received data and an event FIFO 35b that stores event codes.The FIFO on the transmitting side is also divided into a transmit data FIFO 36a that stores transmit data and a command FIFO 36b that stores command data. It is provided. Of the received frame decomposed by the frame decomposition section 31, the code of the information field IFM is passed through the pre-buffer 33 to the received data FI.
Stored in FO35b.

Also, control field C of the decomposed received frame
The NT code is sent to the event analysis section 34, an event code is generated, and is stored in the event FIFO 35a. By passing the received data through the pre-buffer 33, the time delay required for determining the event code in the event analysis unit 34 can be adjusted, and the FI
Can be stored in FO. Note that at this time, it is preferable to add a flag to the received data to indicate the correspondence with the event code, and then input the received data into the FIFO.

In this embodiment, the reception data FIFO 35a and event FIFO 35b are connectable to the data bus 12a and event bus 12b via ports 39a and 39b controlled by signals from the DMA controller 13 or the protocol control unit 14, and the FIFO The stored code is processed according to the request of the DMA controller 13 mentioned above.
The data is transferred to the protocol control unit 14 via buses 12a and 12b.

On the other hand, the above transmission data FIFO 36a and command FIF
O36b is connectable to data bus 12a and command bus 12c via ports 39c and 39d,
The transmission data transferred from the main memory 22 by the DMA controller 13 is stored in the transmission data FIFO 36a.
Also, command codes sent from the protocol control unit 14 are sequentially stored in the command FIFO 36b. The command code stored in the command FIFO 36b is sent to the command analysis section 37 and decoded, and the corresponding processing is notified to the command execution section 38. Then, the command execution unit 38 forms a control signal that sequentially operates the frame assembly unit 32, which includes a flag generation circuit, an abort generation circuit, a CRC code generation circuit, a parallel-to-serial converter, etc., according to the processing content, and sequentially Output.

As a result, in the frame assembling unit 32, the address field ADD and the control field CNT are generated after the opening flag FO, and then the information field IF
The transmission data in the transmission data FIF036a is added as M, and finally CR as check field FC3.
A frame as shown in FIG. 3 with the C code and closing flag Fc added is formed and output. However, the CRC code does not necessarily need to be added.

In the above embodiment, the bus in the communication control device 20 is divided into three parts: the data bus 12a, the event bus 12b, and the command bus 12c. However, the bus is not necessarily limited to this, and there are two buses. It is also possible to put the transmission data on one side and the event code or command code on the other.

In addition, in the embodiment, the FIFO on the receiving side is used as the receiving data FIFO.
Although the FIFO 35a and the event FIFO 35b are provided separately, in a communication control device that analyzes a received frame to form a status, a status FIFO for storing the status may be provided in addition to the above-mentioned FIFO.

As explained above, in the above embodiment, the reception FIFO is divided into an event FIFO that stores the results of event analysis of the received frame and a reception data FIFO that stores the received data, and the transmission FIFO is divided into the command FIFO that stores the command code. and send data FI to put the send data
Since the event analysis means and command execution means are configured with hardware, the event FIFO stores an event string in which one event corresponds to one received frame, and the received data is stored in a separate dedicated FIFO. Since the data is stored in , the protocol control unit has a margin for processing, and the maximum transfer rate is no longer limited by the maximum processing time per frame as in sequential frame processing, and the line speed is increased.

The buses connected to the FIFO are also divided into an event bus for event codes, a command bus for command codes, and a data bus for transmitted and received data, and events, commands, and data are transferred through separate buses. This reduces contention on the bus, eliminates the overhead of switching events, commands, and data in the protocol control unit as in the shared bus method, and allows protocol processing to be performed during DMA transfer of sent and received data. Moreover, since simultaneous transmission and reception processing becomes possible, the line speed becomes faster. Furthermore, since each common bus can be controlled by one CPU, if it is desired to increase the number of channels, it is only necessary to increase the number of line control units, which is advantageous in terms of cost. Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor.

For example, in the above embodiment, four line control units are provided,
Although four channels are supported, the number of channels may be three or less or five or more.

Further, in the embodiment, the transmit clock and the receive clock are provided externally, but the system clock may be used as the transmit clock, or the receive clock may be formed from received data.

Further, in the above embodiment, a system in which a line control unit and a protocol control section are formed on the same chip has been described, but it is of course applicable to a case where these are formed on separate LSIs.

Furthermore, although the embodiment has been described as an example in which it is applied to a device that performs serial communication according to the HDLC protocol, the communication protocol is not limited to HDLC, and can generally be applied to a bit-synchronized serial communication control device according to other types of protocols. Can be applied.

In the above description, the invention made by the present inventor was mainly applied to a serial communication control device constituting a local area network, which is the background field of application, but the invention is not limited thereto. It can be used in general communication control devices.

[Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below.

That is, in the bit-synchronized serial communication control device, it is possible to speed up protocol processing and easily realize multiple channels.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a communication control device according to the present invention, FIG. 2 is a block diagram showing an example of a line control unit, and FIG. 3 is a block diagram showing an example of a line control unit. FIG. 4 is a block diagram showing an example of a conventional communication control device. 11a-lid... line control unit, 12a...
...Data bus, 12b...Event bus, 12c
...Command bus, 14...Protocol control section, 44a, 44b...Latch circuit, 45a. 45b...Multiplexer.

Claims (1)

[Claims] 1. A line control device that includes a memory for storing transmission data in a FIFO format and a memory for storing reception data in a FIFO format, and that constructs and disassembles transmission and reception frames according to a communication protocol, and In a communication control device that includes a DMA control circuit that performs DMA transfer between the FIFO memory and the main memory, and a protocol control unit that controls them overall, the line control unit includes the FIFO memory for storing transmitted and received data. Separately from this, a FIFO memory for storing an event code generated from a received frame and a FIFO memory for storing a command code supplied from the protocol control section are provided, and the memory for the event code and the memory for the command code are provided. A communication control device characterized in that the memory is connected to a protocol control unit by a bus separate from a bus for transmitting and receiving data. 2. The communication control device according to claim 1, wherein the event code memory and the command code memory are each connected to the protocol control unit via separate buses. 3. A plurality of the above-mentioned line control units are provided, and each F
3. The communication control device according to claim 1, wherein the IFO memories are commonly connected to the corresponding buses.