JPH04125936A - Forming method of thin film transistor - Google Patents

Forming method of thin film transistor

Info

Publication number
JPH04125936A
JPH04125936A JP24847190A JP24847190A JPH04125936A JP H04125936 A JPH04125936 A JP H04125936A JP 24847190 A JP24847190 A JP 24847190A JP 24847190 A JP24847190 A JP 24847190A JP H04125936 A JPH04125936 A JP H04125936A
Authority
JP
Japan
Prior art keywords
gate electrode
source
electrode
drain
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP24847190A
Other languages
Japanese (ja)
Inventor
Yoshihiko Toyoda
吉彦 豊田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP24847190A priority Critical patent/JPH04125936A/en
Publication of JPH04125936A publication Critical patent/JPH04125936A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To exclude the overlapping parts between electrodes of a base, a source, and a drain, and reduce capacitances between the electrodes, by diffusing impurities by the effect of temperature rise of a semiconductor layer caused by projecting laser light from the substrate side while using a gate electrode as a mask. CONSTITUTION:A gate insulating film 4, a semiconductor layer 3, a impurity containing layer 7 are formed in order on a gate electrode 2 on a substrate 1. From the substrate 1 side, laser light 11 is projected; the impurities in the layer 7 are diffused in the semiconductor layer 3 by the effect of temperature rise in the layer 3, thereby forming a source.drain region, on which a source electrode 5 and a drain electrode 6 are formed. The temperature rise caused by the laser light 11 is restricted within a region which does not overlap at all with the gate electrode 2 irradiated with the laser light 11 while the gate electrode 2 is used as a mask, so that overlapping parts between the gate electrode and the source and the drain electrodes are not generated. Thereby capacitances between electrodes are reduced, and the rise time characteristics of a gate signal can be improved.

Description

【発明の詳細な説明】 [産業上の利用分野コ この発明は、例えば液晶空間光度wI4器に用いられる
薄膜トランジスタの作成方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method for manufacturing a thin film transistor used, for example, in a liquid crystal space luminosity wI4 device.

[従来の技術] 第4図は例えば特開昭61−174673号公報に示さ
れた従来の逆スタガー型薄膜トランジスタの断面図であ
る。図に於て、 (11は透明絶縁基板、 (2)はゲ
ート電極、 (3)は半導体層、(4)はゲート絶縁膜
、 (5)はソース電極、 (6)はドレイン電極であ
る。
[Prior Art] FIG. 4 is a sectional view of a conventional inverted staggered thin film transistor disclosed in, for example, Japanese Patent Laid-Open No. 174673/1983. In the figure, (11 is a transparent insulating substrate, (2) is a gate electrode, (3) is a semiconductor layer, (4) is a gate insulating film, (5) is a source electrode, and (6) is a drain electrode.

次に動作について説明する。ゲート電極(2)に電圧が
印加されると半導体層(3)にキャリアーが誘起され薄
膜トランジスタはON状態となる。
Next, the operation will be explained. When a voltage is applied to the gate electrode (2), carriers are induced in the semiconductor layer (3) and the thin film transistor is turned on.

ゲート電極(2)に電圧が印加されていないときはOF
F状態である。
OF when no voltage is applied to the gate electrode (2)
It is in F state.

[発明が解決しようとする課題コ 従来の逆スタガー型薄膜トランジスタは以上のように構
成されており、ソース電極(5)またはドレイン電極(
6)とゲート電極(2)との間に重なり合う部分がある
ためゲート電極(2)とソース電極(5)間の容量(以
下ゲート・ソース容量と呼ぶ)やゲート電極(2)とド
レイン電極(6)間の容量(以下ゲート・ドレイン容量
と呼ぶ)が大きくなってしまう欠点があった。このため
、■ゲート信号が立ち下がる時にゲート・ドレイン容量
による放電が生じドレイン電圧が低下する、■ゲート・
ソース容量やゲート・ドレイン容量とゲート抵抗により
ゲート信号の立ち上がりが遅くなる等の問題点があった
[Problems to be Solved by the Invention] The conventional inverted stagger type thin film transistor is configured as described above, and the source electrode (5) or the drain electrode (
6) and the gate electrode (2), the capacitance between the gate electrode (2) and the source electrode (5) (hereinafter referred to as gate-source capacitance) and the gate electrode (2) and the drain electrode ( 6) There was a drawback that the capacitance between them (hereinafter referred to as gate-drain capacitance) became large. For this reason, ■ When the gate signal falls, discharge occurs due to the gate-drain capacitance and the drain voltage decreases.
There were problems such as a slow rise of the gate signal due to the source capacitance, gate/drain capacitance, and gate resistance.

二の発明は上記のような問題点を解消するために成され
たもので、ソース電極やドレイン電極とゲーI・電極と
の重なり部分をなくすことを目的とする。
The second invention was made to solve the above-mentioned problems, and its purpose is to eliminate the overlap between the source electrode or drain electrode and the gate I electrode.

[課題を解決するための手段] この発明に係る薄膜トランジスタの作成方法は、基板側
よりゲート電極をマスクとして光を入射し、半導体膜の
温度を上昇せしめで不純物の拡散を行い、ソース領域及
びドレイン領域を形成するものである。
[Means for Solving the Problems] A method for manufacturing a thin film transistor according to the present invention involves injecting light from the substrate side using the gate electrode as a mask, increasing the temperature of the semiconductor film, diffusing impurities, and forming the source region and the drain. It forms a region.

[作用コ この発明における薄膜トランジスタの作成方法では、ゲ
ート電極をマスクとして不純物の拡散を行い、ソース領
域及びドレイン領域を形成するのでゲート電極とソース
電極及びドレイン電極の重なり部分をなくすことができ
る。
[Operations] In the method for manufacturing a thin film transistor according to the present invention, impurities are diffused using the gate electrode as a mask to form the source region and the drain region, so it is possible to eliminate the overlapping portions of the gate electrode, the source electrode, and the drain electrode.

[実施例] 以下、この発明の一実施例を図について説明する。第1
図(a)(b)(c)はそれぞれこの発明の一実施例に
よる薄膜トランジスタの作成方法の工程を示す断面図で
ある。この図に於て、 (1)は透明絶縁基板である。
[Example] Hereinafter, an example of the present invention will be described with reference to the drawings. 1st
Figures (a), (b), and (c) are cross-sectional views showing steps in a method for manufacturing a thin film transistor according to an embodiment of the present invention. In this figure, (1) is a transparent insulating substrate.

 (2)はゲート電極であり、一般にCr等の高融点金
属が用いられる。 (3)は半導体層で、一般に非晶質
シリコン、多結晶シリコン等が用いられる。 (4)は
ケート絶縁膜である。 (7)は不純物含有層でPSG
等を用いればよい。
(2) is a gate electrode, and generally a high melting point metal such as Cr is used. (3) is a semiconductor layer, which is generally made of amorphous silicon, polycrystalline silicon, or the like. (4) is a Kate insulating film. (7) is PSG in the impurity-containing layer
etc. may be used.

次に作成方法について説明する。まず、第1図(a)に
示すようにゲート電極(2)上にゲート絶縁膜(4)、
半導体層(3)を形成した後、不純物含有層(7)を形
成する。次に、第1図(b)に示すように、この基板(
1)に基板側よりエキシマレーザ−光(11)を入射す
ると、ゲート電極(2)をマスクとしたエキシマレーザ
−光(11)が半導体11m1 (3)に入射し吸収さ
れ温度上昇を引き起こす。この温度上昇により不純物含
有層(7)内の不純物が半導体膜(3)に拡散し、ソー
ス、 ドレイン領域が形成される。温度上昇が生じてい
るのはゲート電極(2)をマスクとしてエキシマレーザ
ー光(11)が当たっている部分であり、これらの部分
はゲート電極(2)と全く重ならない。このためゲート
電極(2)とソース電極(5)及びドレイン電極(6)
の重なり部分をなくすことができる。この後、第1図(
C)に示すように、ソース、 ドレイン領域上にソース
、 ドレイン電極(5)(6)を形成すればよい。
Next, the creation method will be explained. First, as shown in FIG. 1(a), a gate insulating film (4) is placed on a gate electrode (2),
After forming the semiconductor layer (3), an impurity-containing layer (7) is formed. Next, as shown in FIG. 1(b), this substrate (
When excimer laser light (11) is incident on 1) from the substrate side, the excimer laser light (11) using the gate electrode (2) as a mask enters the semiconductor 11m1 (3) and is absorbed, causing a temperature rise. This temperature rise causes impurities in the impurity-containing layer (7) to diffuse into the semiconductor film (3), forming source and drain regions. The temperature rise occurs in the portions that are irradiated with the excimer laser beam (11) using the gate electrode (2) as a mask, and these portions do not overlap with the gate electrode (2) at all. Therefore, the gate electrode (2), the source electrode (5) and the drain electrode (6)
The overlapping part can be eliminated. After this, Figure 1 (
As shown in C), source and drain electrodes (5) and (6) may be formed on the source and drain regions.

尚、上記実施例では光源としてエキシマレーザ−を用い
たが、半導体層(3)に吸収がある波長領域内であれば
他のレーザー(例えばArレーザXeレーザー等)でも
良(、またパルス輻もQスイッチを使った物からCW発
扱の物までいずれでもよい。また、レーザー以外のフラ
ッシュランプなどの光源でもよい。
In the above embodiment, an excimer laser was used as the light source, but other lasers (for example, Ar laser, Any light source may be used, from a Q-switch to a CW light source.Furthermore, a light source other than a laser, such as a flash lamp, may be used.

また、今回不純物の供給源としてはPSG等の不純物含
有層(7)を用いたが、不純物含有層として不純物をド
ーピングした半導体層或は不純物を含有する樹脂或は不
純物そのものでもよい。不純物をドーピングした半導体
層の作成にはCVD法などによる成膜やイオン注入を用
いることができる。
Furthermore, although an impurity-containing layer (7) such as PSG was used as the impurity supply source this time, the impurity-containing layer may be a semiconductor layer doped with an impurity, a resin containing an impurity, or the impurity itself. To create a semiconductor layer doped with impurities, film formation using a CVD method or the like or ion implantation can be used.

また、第2図(a)に示すように、半導体層(3)上に
ゲート電極(2)を覆う広さの絶縁膜(8)を設けるこ
とにより半導体層表面に不純物が拡散することが防げる
と共に半導体層(3)に不純物が拡散する領域をより精
密に制御することができる。第2図(b)(c)に示す
他の工程は第1図(b)(C)場合と同様である。
Further, as shown in FIG. 2(a), by providing an insulating film (8) on the semiconductor layer (3) with a width that covers the gate electrode (2), it is possible to prevent impurities from diffusing into the surface of the semiconductor layer. At the same time, the region in which impurities are diffused into the semiconductor layer (3) can be controlled more precisely. The other steps shown in FIGS. 2(b) and 2(c) are the same as those in FIGS. 1(b) and (C).

また、第3図に示すように、光によるゲート電極(2)
の損傷を防ぐため、ゲート電[i!(2)と絶縁基板(
1)の間に反射膜(9)を設けてもよい。
In addition, as shown in FIG. 3, the gate electrode (2) is formed by light.
To prevent damage to the gate electrode [i! (2) and an insulating substrate (
A reflective film (9) may be provided between 1).

[発明の効果コ 以上のように、この発明によれば、基板側よりゲート電
極をマスクとして光を入射し、半導体膜の温度を上昇せ
しめで不純物の拡散を行い、ソース領域及びドレイン領
域を形成するので、ゲート電極及びソース電極とドレイ
ン電極との重なり部分をなくすことかでき、ソース・ゲ
ート容量およびドレイン・ゲート容量を低減することが
でき、ゲート信号の立ち上がり特性やドレイン電圧の保
持特性が改善され性能が良いものが得られる。
[Effects of the Invention] As described above, according to the present invention, light is incident from the substrate side using the gate electrode as a mask to increase the temperature of the semiconductor film and diffuse impurities, thereby forming a source region and a drain region. Therefore, it is possible to eliminate the overlap between the gate electrode, source electrode, and drain electrode, reduce the source-gate capacitance and drain-gate capacitance, and improve the rise characteristics of the gate signal and the retention characteristics of the drain voltage. It is possible to obtain a product with good performance.

【図面の簡単な説明】[Brief explanation of drawings]

第1図<a)(b)(c)はそれぞれこの発明の一実施
例による薄膜I・ランジスタの作成方法を工程順に示す
断面図、第2図(a)(b)(c)はそれぞれこの発明
の他の実施例による薄膜トランジスタの作成方法を工程
順に示す断面図、第3図はこの発明のさらに他の実施例
に係わる薄膜トランジスタの作成工程の一部を示す断面
図、第4図は従来の方法で作成された薄膜トランジスタ
を示す断面図である。 図において、 (1)は透明絶縁基板、 (2)はゲー
ト電極、 (3)は半導体層、 (4)はゲート絶縁膜
、 (5)はソース電極、 (6)はドレイン電極、 
(7)は不純物含有層、 (8)は絶縁膜、(9)は反
射膜である。 尚、図中同一符号は同一または相当部分を示す。 代  理  人   大  岩  増  雄M2図
Figures 1(a), (b), and (c) are cross-sectional views showing the method for manufacturing a thin film I transistor according to an embodiment of the present invention in the order of steps, and Figures 2(a), (b), and (c) are sectional views of this method, respectively. FIG. 3 is a sectional view showing a part of the manufacturing process of a thin film transistor according to still another embodiment of the invention, and FIG. FIG. 3 is a cross-sectional view showing a thin film transistor manufactured by the method. In the figure, (1) is a transparent insulating substrate, (2) is a gate electrode, (3) is a semiconductor layer, (4) is a gate insulating film, (5) is a source electrode, (6) is a drain electrode,
(7) is an impurity-containing layer, (8) is an insulating film, and (9) is a reflective film. Note that the same reference numerals in the figures indicate the same or corresponding parts. Agent Masu Oiwa M2 figure

Claims (1)

【特許請求の範囲】[Claims] 少なくともその表面が絶縁物からなる基板上に設けられ
ているゲート電極と、このゲート電極上に設けられてい
るゲート絶縁膜と、このゲート絶縁膜上に設けられてい
る半導体膜と、この半導体膜上に形成されているソース
領域及びドレイン領域と、これらソース領域及びドレイ
ン領域上に各々設けられているソース電極及びドレイン
電極とより成る逆スタガー型の薄膜トランジスタの作成
方法において、上記基板側より上記ゲート電極をマスク
として光を入射し、上記半導体膜の温度を上昇せしめで
不純物の拡散を行い、上記ソース領域及びドレイン領域
を形成することを特徴とする薄膜トランジスタの作成方
法。
A gate electrode provided on a substrate at least the surface of which is made of an insulator, a gate insulating film provided on this gate electrode, a semiconductor film provided on this gate insulating film, and this semiconductor film. In the method for manufacturing an inverted stagger type thin film transistor, the thin film transistor is formed of a source region and a drain region formed on the substrate, and a source electrode and a drain electrode provided on the source region and the drain region, respectively. 1. A method of manufacturing a thin film transistor, comprising the steps of: applying light using an electrode as a mask to increase the temperature of the semiconductor film and diffusing impurities to form the source region and the drain region.
JP24847190A 1990-09-17 1990-09-17 Forming method of thin film transistor Pending JPH04125936A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24847190A JPH04125936A (en) 1990-09-17 1990-09-17 Forming method of thin film transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24847190A JPH04125936A (en) 1990-09-17 1990-09-17 Forming method of thin film transistor

Publications (1)

Publication Number Publication Date
JPH04125936A true JPH04125936A (en) 1992-04-27

Family

ID=17178643

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24847190A Pending JPH04125936A (en) 1990-09-17 1990-09-17 Forming method of thin film transistor

Country Status (1)

Country Link
JP (1) JPH04125936A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08204205A (en) * 1995-01-19 1996-08-09 Sony Corp Fabrication of bottom gate type thin film transistor
CN107464848A (en) * 2017-06-21 2017-12-12 北京大学深圳研究生院 Bottom gate oxide semiconductor thin-film transistor and preparation method thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08204205A (en) * 1995-01-19 1996-08-09 Sony Corp Fabrication of bottom gate type thin film transistor
CN107464848A (en) * 2017-06-21 2017-12-12 北京大学深圳研究生院 Bottom gate oxide semiconductor thin-film transistor and preparation method thereof
CN107464848B (en) * 2017-06-21 2020-08-25 北京大学深圳研究生院 Bottom gate oxide semiconductor thin film transistor and preparation method thereof

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