JPH04125731A - Program breading point setting system - Google Patents

Abstract

PURPOSE:To interrupt a program to perform a debugging or the like even in a ROM program system by substituting the ROM program instruction in an arbitrarily designatable address with an arbitrarily settable instruction at the time of program fetch. CONSTITUTION:The address of a breading point is written in a register 18. When the program stored in a ROM is executed, a processor CPU sets the CPU status to program fetch and puts the ROM address on an address bus AB. A decoding circuit 14 decodes the CPU status and finds the program fetch to output a memory read MEMRD, and an address coincidence detecting circuit 26 compares the address in the register 18 with the address on the address bus AB. When addresses coincide with each other, a control circuit 22 does not output an output enable signal OE (inversion of the high level and the low level) and causes an instruction register 24 to output its set data (an inter rupt instruction or the like) to a data bus DB.

Description

[Detailed Description of the Invention] [Summary of the Invention] Regarding a program breakpoint setting method in a processing device in which a processor executes a program stored in a ROM, the breakpoint setting method interrupts execution of a program on a ROM at any desired point. In a breakpoint setting method for a program stored in ROM, there is a register that stores the breakpoint address of the program, and an address match that compares the address output by the processor and the contents of the register when fetching the program. A ROM data change circuit is provided that changes the ROM read data to the processor to other data by the output of the circuit and the 8-address matching circuit, and sets the address at the point in time when program execution is desired to be interrupted in the register, and when the program is fetched. When the address output by the processor matches the address of the register, the ROM data change circuit receives the output of the address-number circuit and changes the data sent to the processor to other data instead of ROM successive data. do.

[Industrial application field]

The present invention relates to a method for setting breakpoints in a program in a processing device in which a processor executes a block diagram stored in a ROM.

In software debugging, a method is often adopted in which program execution is interrupted at an appropriate point (breakpoint) and data in registers, RAM, etc. at that time is checked. The present invention relates to a method for setting breakpoints in such a program.

[Conventional technology]

To interrupt program execution and check the status of each part at that time, start the motor program equipped with a man-machine interface just before executing the command at the point where you want to interrupt (breakpoint), and then change each part from the keyboard etc. All you have to do is input a read command, etc. However, since programs are generally stored in a ROM that cannot be rewritten, and breakpoints are desired to be arbitrarily variable, the above processing requires some ingenuity.

FIG. 3 shows the basic configuration of a ROM type CPU. A program is stored in the ROM, and the CPU and ROM are connected by an address bus AB and a data bus DB. When the CPU reads a program from the ROM, it issues a ROM address and a program fetch command. The ROM address/number circuit 12 outputs a ROM chip select C8 signal when the address on bus AB is a ROM address, and the decode circuit 14 outputs a memory read MEMRD (ROM output enable signal) when the CPU status signal is a program fetch. output signal OE). The ROM then reads the data (program command) at the specified address and places it on the data bus DB. The response circuit 16 is R
When the OM address number circuit 12 generates the C3 signal and the decode circuit 14 generates the OE multiplication signal, this is notified to the CPU. In response to this, the CPU takes in the data (program instructions) on the data bus DB and executes it.

In the CPU, the program counter outputs the next address, and the above process is repeated to execute each instruction of the ROM program one after another.

Conventionally, in software debugging of a processing device in which a program is stored in a ROM, the program is read from the ROM (read-only memory), expanded on a RAM (random access memory), and then moved to a desired address as appropriate. A method is adopted in which the program is interrupted by rewriting the instruction, for example, the above instruction is rewritten to an interrupt instruction, and a monitor program equipped with a man-machine interface is started in the interrupt processing section to check each section.

When the program restarts running, the rewritten command is replaced with the original command, the command counter is reset by 1, and the program starts running.

After the vehicle has traveled appropriately, the same process is performed again, and this process is repeated a desired number of times.

[Problem to be solved by the invention]

If a program is on RAM, it is possible to rewrite the appropriate instructions to interrupt instructions, check the status of each part of the processor, etc., and even check for bugs in the program. method), even if the program is stored in ROM,
The above processing can be performed by reading it out and developing it in RAM.

However, the method of expanding a program on ROM onto RAM and debugging it can be adopted if the system has sufficient RAM capacity; otherwise, this method cannot be adopted.

However, even if there is not enough RAM, it may be necessary to interrupt the execution of the ROM program. Further, programs are usually stored in ROM and used, and therefore there is a need to run a program in its final form in ROM rather than a program in RAM, and to interrupt execution and check for bugs.

The present invention has been made in view of these points, and it is an object of the present invention to provide a breakpoint setting method for interrupting the execution of a program on R0M at any desired point.

[Means for Solving the Problems] As shown in FIG. 1, the present invention includes a register 18 for setting the address of a desired breakpoint, and
An address number circuit 26 that compares the address set to 8 with the address on the address bus AB, and a ROM data change circuit 20 are provided. The ROM data change circuit 20 includes a control circuit 22 and an instruction register 24.
receives a match output from the address/number circuit 22 and outputs a signal to the instruction register 24 and ROM. An instruction to be executed at a breakpoint, such as an interrupt instruction, is written in the instruction register 24.

As in all figures, parts in this figure that are the same as in other figures are given the same reference numerals. If you compare it with Figure 3, the first
The main difference between the figures is that a break address register 18, a ROM data change circuit 20, and an address number circuit 26 are added.

[Operation] In the present invention, the address of the point at which the running is to be interrupted, that is, the address of the breakpoint, is written in the register 18. When executing a program stored in ROM, the processor CP
U sets the CPU status to program fetch and puts the ROM address on address bus AB, but when the decoding circuit 14 decodes the CPU status and finds that it is program fetch, it outputs memory read MEM.
RD is output, causing the address-number circuit 26 to compare the address of the register 18 and the address of the address bus AB. While these addresses do not match, the control circuit 22
The control circuit 22 outputs the output enable signal OE to M, and when they match, the control circuit 22 does not output the output enable signal OE (inverts H and L), but instead outputs the data (interrupt command, etc.) set in the instruction register 24. is output to the data bus DB. This will interrupt program execution and allow you to perform depacking, etc. The breakpoint can be changed arbitrarily by the address set in the register 18.

(Example) The execution of the ROM stored program in FIG. 1 is the same as that in FIG. , this becomes the output enable OE of the ROM, but in FIG. 1, the decode circuit 14 outputs MEMRD1, and in this case, there is an address mismatch in the address-number circuit 26, so MEMRDI enters the control circuit 22 and is output to MEMRD2. This is RO
Becomes an OE of M. Also, if the address on bus AB is a ROM address, the ROM address/number circuit 12 outputs the chip select (C3), so in this example, the ROM address/number circuit 12 outputs the chip select (C5) and O
E enters, an address enters from bus AB, and now R
OM performs reading using the address on the bus AB and puts the read data on the bus DB. Further, the response circuit 16 is
When it receives MHMRLII from the decode circuit 14 and C8 from the ROM address/number circuit 12, it notifies the CPU of this fact, so the CPU takes in the data (program instructions) on the data bus DB. The address counter of the CPU generates the next address one after another, and the above process is repeated as the program progresses.

FIG. 2 shows an embodiment of the invention. Address-number circuit 2
In this example, 6 indicates exclusive OR gates EOR as many as the number of address bits, and an AND gate A that receives the outputs of these.
Consists of ND. Exclusive or game) One input of EOR is register 1 where the breakpoint address is set.
8 to each bit, and the other input is the address bus AB.
are connected to each line (there are as many as the number of bits in the address). When each bit of the address matches, the output of each EOR is 0, when it is inverted, it is 1, and this is connected to the AND gate AN
When input to D, the output of the AND gate becomes 1, which is the coincidence output (CHANGE signal) of the address-number circuit 26.
become. Note that the )'ETC)I output (CP
MEM when U status is program fetch
(which appears with RD) is also manually input, and when this is present (when it is 1), the output of the AND gate AND becomes 1.

In this example, the ROM data change circuit 20 includes an inverter INV, an ant gate AND, and an instruction register 24, which constitute a control circuit 22. When there is a match output from the address-number circuit 26, it enters the instruction register 24 and outputs the data (instruction) set therein to the data bus DB. At this time, the above -dispersed output is inverted by the inverter and 1 becomes 0, so the gate AND is closed and the output MEM)iDl of the decoder 14 does not become the output enable OE of the ROM. In other words, output of read data from the ROM is prohibited. On the other hand, when there is a mismatch output, no data is sent from the instruction register 24 to the data bus DB, and instead the mismatch output is inverted by the inverter INV and O becomes 1.
Game) AND opens. Therefore, at this time, the output MEMRDI of the decoder 14 passes through the gate AND
12 and is input to the output enable terminal OE of the ROM. The ROM is now capable of outputting read data and sends the read data to the data bus DB.

〔Effect of the invention〕

As explained above, according to the present invention, a ROM program instruction at an address that can be specified arbitrarily can be replaced with an instruction that can be arbitrarily set when fetching a program, so that a program can be interrupted even in a ROM program system. You can perform debugging, etc.

[Brief explanation of drawings]

Fig. 1 is a principle diagram of the present invention, Fig. 2 is a block diagram showing an embodiment of the present invention, and Fig. 3 is a R
FIG. 2 is a block diagram showing the basic configuration of an OM type CPU. In FIG. 1, 18 is a register, 20 is a ROM data changing circuit, and 26 is an address/number circuit.

Claims (1)

[Claims] 1. In a breakpoint setting method for a program stored in a ROM, a register (18) that stores a breakpoint address of the program is compared with the address output by the processor and the contents of the register when fetching the program. and a ROM data change circuit (20) that changes the ROM read data to the processor to other data based on the output of the address match circuit. When an address is set and the address output by the processor at the time of program fetch matches the address of the register, the ROM data change circuit receives the output of the address match circuit and changes the data sent to the processor to other data instead of ROM read data. A breakpoint setting method for a program that is characterized by changing data.