JPH04122983A - Driving method for liquid crystal display device - Google Patents

Abstract

PURPOSE:To make the number of circuits less than before by dividing a horizontal scanning period into N (N: integer larger than two), dividing and displaying a video signal, and sampling and holding only video signals by as many as signals displayed in the divided periods. CONSTITUTION:As shown in (a), 160X3=480 picture elements are written in a memory 5 in the order of R, G, and B horizontally from the 1st picture ele ment in the 1st column, and picture elements in the 2nd and succeeding columns are written and stored in the memory 5 similarly. When they are read out, the R signal of the 1st column is read out successively by 160 picture elements under the control of a memory control circuit 7, the G signal of the 1st column is then readout, and the B signal of the 1st column is read out lastly. Then the picture elements in the 2nd and succeeding columns are read out by the same procedure. Thus, the horizontal scanning period is divided, the video signal to be displayed is divided and supplied in the divided periods, and a sample holding circuit holds only the video signals by as many as signals dis played in the respective divided periods,so the number of circuits can be de creased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for driving an active matrix type liquid crystal display device in which a transistor is incorporated in each pixel.

[Prior Art] Conventionally, a signal processing circuit as shown in FIG. 4 and a drive circuit as shown in FIG. 5 have been used to drive an active matrix type liquid crystal display device.

That is, in FIG. 4, the television signal Stv input from the television signal input terminal 31 is input to the television signal processing circuit 32. The television signal processing circuit 32 is
R (red), G (
It generates green), B (blue) signals, a display driver control signal C1, and a driving driver control signal C2 (horizontal synchronization signal SR), and outputs the R, G, and B signals to the video signal output terminals 33 to 33, respectively. 35, the control signal C1 is output to the display driver control signal output terminal 36, and the control signal C2 is output to the drive driver control signal output terminal 37.

On the other hand, FIG. 5 shows a liquid crystal television and its driving means.

The liquid crystal television is an active matrix type in which a plurality of R and G transistors are directly formed.

The B pixels 41 are arranged in a matrix, and the gates of the transistors 42 of the pixels 41 arranged in the horizontal direction are connected to each other, and the sources of the transistors 42 of the pixels 41 arranged in the vertical direction are connected to each other.

R, G, B signals and display driver control signal C
1 are input to the display drivers 43 and 44 via the video signal input terminals 46 to 48 and the display driver control signal input terminal 49, respectively. Display driver 4
3, based on the control by the control circuit 51,
Switch the multiplex circuit 50 and input R, G
, B signal sample and hold circuit 52□~5
Sort into 2□4o in order. Sorted RlG,
The B signal is passed through output buffers 53□ to 5324o,
The signal is supplied to odd-numbered pixels 41 in the horizontal direction. Similarly, in the display driver 44, the control circuit 5
The multiplex circuit 54 is switched based on the control by 5, and the input RlG and B signals are sampled and
It is distributed to hold circuits 58 to 57240 in order.

The distributed R, G, and B signals are sent to the output buffer 57.
~57240, even horizontal pixel 41
is supplied to

On the other hand, the driving driver control signal C2 is input to the driving driver 45 via the driving driver control signal input terminal 58. The drive driver 45 switches the shift register 59 according to the input control signal C2, and outputs the output buffers 601 to 60°4o.
Each line of the matrix of pixels 41 is sequentially driven through the pixel 41.

[Problems to be Solved by the Invention] However, the above-described conventional method for driving a liquid crystal display device has a problem in that it requires a large number of samples and holds for display.

For example, 24041ii in the vertical direction 480 in the horizontal direction
As is clear from Figure 5, when driving a liquid crystal panel with 480 pixels, the conventional method requires 480 samples.
Requires an and-hold circuit.

Since the sample-and-hold circuit handles the display voltage as an analog signal, unless the output offset voltage between each sample-and-hold circuit is brought close to OV extremely accurately, it may adversely affect the display. become. In this sense, a large number of sample-and-hold circuits is a major factor in deteriorating display quality.

In addition, when a sample-and-hold circuit is formed on a chip, it has a larger number of circuit elements than an output buffer circuit, and also requires a capacitor. It requires 2 to 3 times as much area.

For this reason, with current device technology, it is extremely difficult to fit as many as 480 sample-and-hold circuits into one chip, and eventually they must be divided into multiple chips, leading to increased costs.

As described above, the need for a large number of sample-and-hold circuits is disadvantageous in terms of characteristics and cost.

The present invention has been made in view of these problems, and can reduce the number of sample-and-hold circuits relative to the number of pixels compared to conventional methods, improving display quality and reducing costs by reducing chip area. An object of the present invention is to provide a method for driving a liquid crystal display device that can achieve the following.

[Means for Solving the Problems] A method for driving a liquid crystal display device according to the present invention divides each horizontal scanning period into N (N is an integer of 2 or more), and divides a video signal to be displayed in each horizontal scanning period into two parts. It is characterized in that it is divided and displayed, and that only the amount of video signal to be displayed in each divided period is sampled and held.

[Function] According to the present invention, each horizontal scanning period is divided into N parts, the video signal is time-divisionally displayed within each horizontal scanning period, and only the amount of video signal to be displayed within each divided period is sampled.
Since the AND-hold is performed, the number of sample-and-hold circuits can be reduced to 1/H compared to the conventional one. Therefore, the output offset voltage is reduced to OV
This makes it easy to set the display quality, and it is possible to improve display quality and reduce costs by reducing the chip area.

[Embodiments] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 1 shows a signal processing means for applying a method for driving a liquid crystal television according to an embodiment of the present invention, and FIG. 2 shows a means for driving a liquid crystal television using a signal processed by the signal processing means. FIG.

In FIG. 1, a television signal STv input to a television signal input terminal 1 is input to a television signal processing circuit 2. As shown in FIG. The television signal processing circuit 2 receives input television signals STv to RlG.

It outputs the B signal, the display driver control signal c1, and the horizontal synchronization signal SH. The R, G, and B signals are input to a multiplex circuit 3. The multiplex circuit 3 selects R, G based on the control signal C3.
, B signals are sequentially switched and output. The R, G, and B signals switched by the multiplex circuit 3 are supplied to an A/D converter 4, where they are A/D converted and then stored in a memory 5. On the other hand, the display driver control signal C1 and the horizontal synchronization signal S8 are input to the memory control circuit 7. The memory control circuit 7 switches the order of the RGB signals from the order shown in FIG. 3(a) to the order shown in FIG. 3(b).
It controls the write and read operations of the memory 5 and outputs a driving driver control signal C2. The R, G, and B signals read from the memory 5 are sent to the D/A converter 6.
After being D/A converted, the signal is serially output from the video signal output terminal 8.

Further, control signals C1 and C2 outputted from the television signal processing circuit 2 and the memory control circuit 7, respectively, are outputted to a display driver control signal output terminal 9 and a drive driver control signal output terminal 10, respectively.

On the other hand, FIG. 2 shows a liquid crystal television and its driving means. In addition, here, the LCD television is vertically 24
A case will be described in which the pixel is composed of 0 pixels and 480 pixels in the horizontal direction.

The LCD TV is an active matrix type in which a plurality of R and G transistors are directly formed.

B pixels 41 are arranged in a matrix, and among the pixels 11 arranged in the horizontal direction, the transistors 12 of the pixels 11 of the same color are arranged in a matrix.
The gates of the pixels 11 are connected to each other, and the sources of the transistors 12 of the pixels 11 of three vertical rows are connected to each other.

R, G, B signals and display driver control signal C
I is input to the display driver 15 via a video signal input terminal 17 and a display driver control signal input terminal 18, respectively. In the display driver 15, R and G signals are serially input based on the control by the control [1l19.

A fist-and-hold circuit 20 that sequentially samples the B signal.
Sample and hold at 20I6o. Here, sample and hold circuit 20. ~20 +eo is provided for each of the three rows of commonly connected pixels 11, so for an LCD TV with 480 pixels per column, only 160 pixels, which is 1/3 of the number, are provided. .

The sampled and held R, G, and B signals are sent to three rows of pixels 11 through output buffers 211 to 2116o, respectively.
is supplied to.

On the other hand, the driving driver control signal c2 is input to the driving driver 16 via the driving driver control signal input terminal 24. In the drive driver 16, the shift register 23 is controlled by the control signal c2.
and output buffer 22. Each line of the matrix of pixels 11 is sequentially driven through .about.227.degree.

Next, the operation of the circuit configured as described above will be explained.

When the television input signal STv is input to the television signal processing circuit 2, R, G, and B signals are generated as video signals. Here, X is a horizontal pixel position, Y is a vertical pixel position, and R, G, B at pixel positions
If the signals are expressed as RX, Y IGx, y + Bx, y, then the R, G, and B signals immediately after being converted by the television signal processing circuit 2 and switched by the multiplex circuit 3 are the third
The data are written into the memory 5 in the order shown in FIG. 5(a), and read out from the memory 5 in the order shown in FIG. 5(b).

That is, first, when writing to the memory 5, as shown in FIG.
As shown in a), from the first pixel in the first row, the horizontal direction is 1.
60X3=480 pixels are R and G.

The pixels are written into the memory 5 in the order of B, and then the pixels in the second column are written in the same way. Then, when the pixels in the 240th column are written, data for one screen is stored in the memory 5.

Next, when reading, under the control of the memory control circuit 7, as shown in FIG.
The signal is read out continuously for 160 pixels, then the G signal in the first column is read out continuously for 160 pixels, and finally 1
The B signal in the column is read out continuously for 160 pixels. Next, the pixels in the second column are read out using the same procedure. Then, when the pixels in the 240th column are read out, data for one screen is read out from the memory 5.

When the array-converted R, G, and B signals are supplied to the display driver 15, the display driver 15, under the control of the control circuit 19, first divides the R signal into one column. AND HOLD CIRCUIT 20. ~20.6. Hold on. Then, when the R signal is displayed in synchronization with the output of the shift register 23, the G signal is sent to the sample-and-hold circuit 20. Hold at ~20,6o. After the G signal is displayed, the B signal is sent to the sample and hold circuit 20. ~201eo
It is held and displayed. This completes the display of one column. When this display operation is performed for 240 columns in the vertical direction, display for one screen is completed.

Note that in order to perform such a display operation, the driving driver control signal C2 is 3 times the normal horizontal synchronizing signal SH.
It needs to be a signal with twice the frequency. This is generated by the memory control circuit 7.

As described above, according to this embodiment, the arrangement of the R, G, and B signals is converted and the R, G, and B signals are supplied to the pixels 11 in a time-sharing manner within one horizontal scanning period. Sample and hold circuit 20°~20, number of eo 16
The number can be reduced to 0, which is 1/3 of the conventional number.

Therefore, not only the display quality is improved, but also the display driver 15 can be contained in one chip, so that the cost of the liquid crystal driving means can be reduced.

Note that in the above embodiments, the video signals are R and G.

Although the display is divided into three parts corresponding to B, the number of divisions is not limited to three.

[Effects of the Invention] As described above, according to the present invention, each horizontal scanning period is divided into N parts, the video signal to be displayed within each horizontal scanning period is divided and supplied, and the video signal to be displayed within each divided period is Since only the video signal of the amount displayed in the sample-and-hold circuit is held in the sample-and-hold circuit, the number of sample-and-hold circuits can be reduced to 1/H compared to the conventional one.

Therefore, according to the present invention, the output offset voltage is
v can be easily set, and the display quality can be improved. Furthermore, since the area occupied by the sample-and-hold circuit can be reduced, costs can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a signal processing circuit in a liquid crystal display device to which a method for driving a liquid crystal television according to an embodiment of the present invention is applied; FIG. 2 is a block diagram of a liquid crystal television and its driving circuit in the same liquid crystal display device; Figure 3 is a schematic diagram for explaining an example of video signal arrangement conversion in the signal processing circuit in the same liquid crystal display device, Figure 4 is a block diagram of the signal processing circuit in the conventional liquid crystal display device, and Figure 5 is the same liquid crystal display device. FIG. 2 is a block diagram of a liquid crystal television and its driving circuit in a display device. 1.31; TV signal input terminal, 1, 32; TV signal processing circuit, 3.50, 54; Multiplex circuit, 4
; A/D converter, 5; memory, 6; D/A
Humbata, 7; Memory control signal, 8, 33~
35; Video signal output terminal, 9° 36; Display driver control signal output terminal, 10.37; Driving driver control signal output terminal, 11.41; Pixel, 12,
42;) Transistor, 15, 43.44; Display driver, 16.45; Drive driver, 17.46-48;
Video signal input terminal, 18, 49; display driver control signal input terminal, 19, 51, 55; control circuit, 20. ~20. ．． . , 52. ~5224o, 53
．． 〜53゜401571〜57゜4゜. 56, ~56240; Sample and φ hold circuit, 21. ~2L6o, 22□~22□2o, 60□~6
0□4o; Output buffer, 23, 59; Shift register, 24.58; Drive driver control signal input terminal

Claims (1)

[Claims] (1) Each horizontal scanning period is divided into N (N is an integer of 2 or more), the video signal to be displayed in each horizontal scanning period is divided and displayed, and the amount of video to be displayed in each divided period is A method for driving a liquid crystal display device characterized by sampling and holding only signals.