JPH04122842A - Inspecting method of misalignment between layers of multilayer printed wiring board - Google Patents
Inspecting method of misalignment between layers of multilayer printed wiring boardInfo
- Publication number
- JPH04122842A JPH04122842A JP24533390A JP24533390A JPH04122842A JP H04122842 A JPH04122842 A JP H04122842A JP 24533390 A JP24533390 A JP 24533390A JP 24533390 A JP24533390 A JP 24533390A JP H04122842 A JPH04122842 A JP H04122842A
- Authority
- JP
- Japan
- Prior art keywords
- line
- inspection
- circuit
- lines
- layers
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 8
- 238000007689 inspection Methods 0.000 claims abstract description 80
- 239000010410 layer Substances 0.000 claims description 52
- 239000011229 interlayer Substances 0.000 claims description 5
- 238000005259 measurement Methods 0.000 abstract description 4
- 239000002184 metal Substances 0.000 description 6
- 239000011888 foil Substances 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- 238000003475 lamination Methods 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 238000010030 laminating Methods 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 108091036429 KCNQ1OT1 Proteins 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
Landscapes
- Length Measuring Devices With Unspecified Measuring Means (AREA)
- Investigating Materials By The Use Of Optical Means Adapted For Particular Applications (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
本発明は、多層プリント配線板の各回路層の層間ずれを
測定して検査する方法に関するものである。The present invention relates to a method for measuring and inspecting interlayer misalignment of each circuit layer of a multilayer printed wiring board.
多層プリント配線板は例えば、銅張り積層板なと金属箔
張り積層板の金属箔をエツチング加工等して回路層を設
けた複数枚の回路板を積層成形することによって作成す
ることができる。そしてこの多層プリント配線板にあっ
て、各回路板の積層位置が位置ずれして各回路層に相互
の層間のずれが発生すると、スルーホールなどで各回路
層の回路を接続することができなくなる等の不良が生じ
るおそれがある。
このために、多層プリント配線板においては各回路層の
層間ずれを検査してこのような不良発生を未然に防ぐよ
うにする必要がある。そしてこの回路層の層間ずれを検
査するにあたっては、例えば、各回路層の回路の位置を
顕微鏡で観察してずれの程度を測定したり、測長機など
を使用して各回路層の回路の位置のずれの寸法を測定し
たりしておこなわれていた。A multilayer printed wiring board can be produced, for example, by laminating and molding a plurality of circuit boards each having a circuit layer formed by etching the metal foil of a copper-clad laminate or a metal foil-clad laminate. In this multilayer printed wiring board, if the laminated positions of each circuit board are misaligned and misalignment occurs between each circuit layer, it becomes impossible to connect the circuits of each circuit layer with through holes etc. There is a risk that such defects may occur. For this reason, in a multilayer printed wiring board, it is necessary to inspect the interlayer misalignment of each circuit layer to prevent such defects from occurring. In order to inspect the misalignment between the circuit layers, for example, the position of the circuit on each circuit layer can be observed with a microscope to measure the degree of misalignment, or a length measuring machine can be used to measure the position of the circuit on each circuit layer. This was done by measuring the size of the positional deviation.
しかし回路層の層間ずれを検査するにあたってこのよう
に、各回路層の回路を観察しておこなうようにすると、
そのずれの寸法は上記のように測長機などを使用して測
定をおこなわなければならず、回路層のずれの測定検査
に大掛かりな装置が必要になるものであった。
本発明は上記の点に鑑みて為されたものであり、回路層
のずれの測定検査を容易に且つ簡易におこなうことがで
きる多層プリント配線板の層間ずれ検査方法を提供する
ことを目的とするものである。However, when inspecting the misalignment between circuit layers, if you observe the circuit of each circuit layer in this way,
The size of the deviation must be measured using a length measuring machine or the like as described above, and a large-scale device is required to measure and inspect the deviation of the circuit layer. The present invention has been made in view of the above points, and it is an object of the present invention to provide a method for inspecting interlayer misalignment of a multilayer printed wiring board that can easily and simply measure and inspect misalignment of circuit layers. It is something.
本発明に係る多層プリント配線板の層間ずれ検査方法は
、複数層に回路３を設けて形成される多層プリント配線
板において、等間隔で平行に配列される複数本の検査線
１ａ、ｌｂ・・・を各回路層２ａ、２ｂ・・・にそれぞ
れ互いに平行に対向させて設けると共に、隣り合う一方
の検査線１ａの間隔寸法と他方の検査線１ｂの間隔寸法
とを異なる寸法に設定し、各回路層２ａ、２ｂ・・・の
一方の検査線１ａと他方の検査線１ｂの合致する線を測
定することを特徴とするものである。The method for inspecting interlayer misalignment of a multilayer printed wiring board according to the present invention includes a plurality of inspection lines 1a, lb... are provided in each circuit layer 2a, 2b, . This method is characterized by measuring a matching line between the inspection line 1a of one of the circuit layers 2a, 2b, . . . and the inspection line 1b of the other.
本発明にあっては、等間隔で平行に配列される複数本の
検査線１ａ、ｌｂ・・・を各回路層２ａ、２ｂ・・・に
それぞれ互いに平行に対向させて設けると共に、隣り合
う一方の検査線１ａの間隔寸法と他方の検査線１ｂの間
隔寸法とを異なる寸法に設定し、各回路層２ａ、２ｂ・
・・の一方の検査線１ａと他方の検査線１ｂの合致する
線を測定するようにしているために、検査線１ａ、ｌｂ
・・・の合致する線を測定することによって、測長機な
どを用いるような必要なく、ノギスのバーニヤ目盛りに
よる測長と同じ原理で各回路層２ａ、２ｂ・・・のずれ
の寸法を知ることができる。In the present invention, a plurality of inspection lines 1a, lb... arranged in parallel at equal intervals are provided in each circuit layer 2a, 2b... parallel to each other and facing each other, and one of the adjacent inspection lines 1a, lb... The interval dimension between the inspection lines 1a and the interval dimension between the other inspection lines 1b are set to different dimensions, and each circuit layer 2a, 2b.
Since the measurement is performed on a line where one inspection line 1a and the other inspection line 1b match, the inspection lines 1a, lb
By measuring the matching lines of ..., the size of the deviation of each circuit layer 2a, 2b, etc. can be determined using the same principle as length measurement using the vernier scale of a caliper, without the need to use a length measuring device, etc. be able to.
以下本発明を実施例によって詳述する。
多層プリント配線板Ａは、例えば、銅張りエポキシ樹脂
積層板など金属箔張り積層板を用い、この積層板の金属
箔をエツチング加工等して回路３を形成することによっ
て回路層２ａ、２ｂ・・・をＫけ、この複数枚の回路板
をボンディング用のプリプレ１を介して重ねて加熱加圧
して積層成形をおこなうことによって作成される。そし
て各回路層２ａ、２ｂ・・・にはそれぞれ検査線１ａ、
ｌｂ・・・が設けである。この検査線１ａ、ｌｂ・・・
の形成は、金属箔をエツチング加工して回路３を形成す
る際に、回路３以外の部分においてこの金属箔の一部を
エツチング加工することでおこなうことができる。
この検査線１ａ、ｌｂ・・・は等間隔で平行に配列され
る目盛り線のような複数本の線で形成されるものである
。第１図は本発明の一実施例を示すものであって、二層
の回路層２ａ、２ｂにそれぞれ検査線１ａと検査線１ｂ
が設けてあり、各検査線ｌａ、ｌｂは検査線１ａの各線
１ａｏ、１ａ＋、１ａ２１１ ａ ｓ”’と検査線１ｂ
の各線１ｂ０ １ｂ１ｂ２．ｌｂ、・・・とがそれぞれ
平行に近接対向するように設けである。これらの線１
ａｏ、 １ ａ＋、 １ａｚ＋１ａ コ・−、１ｂｅ
、 １ ｂｌ＋ １ ｂ２＋ １
ｂｓ−の幅Ｗはそれぞれ等しく設定してあり、また検査
線１ａの各線１ ａｎ、 １ ａｌ、 １ ａ２＋ １
ミコ・・・の間隔寸法！、と、検査線１ｂの各線１ｂ
、、ｌｂｌ、１ｂ２，１ｂｓ・・・の間隔１２とは、異
なる間隔寸法になるように設定しである６例えばｗ＝０
．１５ｍｍ ＋ ｆ ＋ ＝ ０ 、 １０ ｍ ｍ
−１ｔ ＝ ０ 、 １６２５ ｍ ｍに設定しである
。また検査線１ａの各線１ａｏ。
１ ａｌ、 １ ａ２．１ ａコ−と検査線１ｂの各線
１ｂ。
、 １ ｂｌ、 １ ｂｘ、１ ｂｓ・・・にはその中
央に位置するものに「０」の符号を付すると共にその両
側のものに外側へ順番に「１」、「２」、「３」・・・
の符号が付しである。そして多層プリント配線板Ａを作
成するにあたって、回路層２ａ、２ｂの積層の位置合わ
せが正確におこなわれていれば、符号「０」を付した線
１ａｏと線１ｂ、とが一直線上に合致するように、検査
線１ａ、ｌｂを回路層２ａ、２ｂに配置して設けるよう
にしである。尚、検査線１ａ、ｌｂはＸ方向に−か所、
Ｘ方向と垂直なＹ方向に−か所、それぞれ設けて回路層
２ａ。
２ｂのＸ方向とＹ方向の位置ずれを検査できるようにし
である（第２区、第３図参照）。
第２図は、回路３，３・・・を設けて形成される二つの
回路層２ａ、２ｂのうち回路層２ａの上に回路層２ｂを
積層するようにして多層プリント配線板Ａを作成するに
あたって、上の回路層２ｂに開口部８を設けて下の回路
層２ａの一部が露出されるようにしたものを示している
。このものでは開口部８の内側において回路層２ａに検
査線１ａを、開口部８の縁部において回路層２ｂに検査
線ｌｂを、それぞれ設けるようにしである。従ってこの
ものでは、表面に露出する検査線１ａ、ｌｂをそれぞれ
直接目視して検査をおこなうことができる。また第３図
のように下の回路層２ａが上の回路層２ｂに完全に覆わ
れて下の回路層２ａが露出されない場合には、下の回路
層２ａに形成した検査線１ａは目で見ることができない
ことがある。
従ってこの場合にはＸ線透過により検査線１ａ。
１ｂを検出して検査をおこなうことになる。
しかして多層プリント配線板Ａの回路層２ａ。
２ｂに設けた検査線１ａ、ｌｂを測定して回路層２ａ、
２ｂの位置ずれを検査するにあたっては、検査線１ａの
各線１ ａｏ、 １ ａ ｌ＋ １ ａ２＋ １
ａ３・・・と検査線１ｂの各線１ ｂｏ、 １ ｂｌ
、 １ ｂ２． １ ｂｘ・・・の位置を対比させ、
−直線上に合致している線を顕微鏡などの拡大鏡を用い
て測定することによっておこなうことができる。すなわ
ち、第１図〈ａ）のように検査線１ａの符号「０」の線
１ａｏと検査線１ｂの符号「０」の線１ｂｏとが一直線
上に合致していれば、回路層２ａ、２ｂの積層の位置合
わせは正確におこなわれている。また検査線１ａの符号
「０」の線１ａａと検査線１ｂの符号「０」の線１ｂｏ
とが一直線上に合致していないと、回路層２ａ、２ｂの
積層の位置合わせにずれがあるということであり、この
ときの位置ずれの寸法は、例えば第１図（ｂ）のように
検査線１ａの符号「４」の線１ａｎと検査線１ｂの符号
ｒ ３ Ｊの線１ｂｓとが一直線上に合致していれば、
Ｌ、−Ｌ２＝ （ｗＸ４＋７＋Ｘ４）−（ＷＸ３＋／２
ｘ３）＝０．０６２５ｍｍであり、また例えば第１図（
Ｃ）のように検査線１ａの符号「３」の線１ａコと検査
線１ｂの符号「２」の線１ｂ２とが一直線上に合致して
いれば、Ｌｌ−Ｌ４＝ （ｗＸ３＋／。
Ｘ３）−（Ｗｘ２＋７ｚＸ２）＝０．１２５ｍｍである
。従って、検査線１ａの各線１ａｏ、１ａ＋１ ａ２．
１ ａ２・−と検査線１ｂの各線１ｂ、、１ｂ＋、ｌｂ
ｚ、ｌｂコ・・・の−直線上に合致している線を測定す
ることによって、回路層２ａ、２ｂの位置ずれの有無、
及び位置ずれの寸法を検査することができる。尚、検査
線１ａ、ｌｂの合致する線に対応して計算した位置ずれ
寸法の検定表を予め作成しておけば、位置ずれの寸法を
直ちに知ることができると共に、位置ずれが許容範囲が
否かの判定も直ちにおこなうこともできる。
第４図の実施例は、三層の回路層２ａ、２ｂ２ｃにそれ
ぞれ検査１１１１ａと検査線１ｂと検査線１ｃが設けて
あり、各検査線１ｂの各ｌｉｔ １ ｂ ｏ 。
１ｂ＋、ｌｂｚ、ｌｂｓ・・・に対して検査線１ａの各
線１ ａｏ、 １ ａ、、 １ ａ２＋ １ ａ３”・
と検査線１ｃの各１ｉ１ ｃｏ、 Ｉ ＣＩ＋ Ｉ Ｃ
２，１ｃコ・・・がそれぞれ平行に近接対向するよう設
けである。これらの線１ａｓ、 １ ａｔ、 １ ａ
ｔ、 １ ａｓ−，１ａｏ＋ ｌｂｌ、１ｂ ２
、 １ ｂ コ・＝ 、 Ｉ Ｃｏ、 １ ｃ
ｌ＋ Ｉ Ｃ２，Ｉ Ｃｚ−の幅Ｗはそれぞ
れ等しく設定してあり、また検査線１ａの各線１ ａＱ
、 １ ａｔ、 １ ａ２＋ １ ａ３・・・の間隔寸
法！１と検査線１ｃの各線ｉｃｅ、ＩＣＩ、ＩＣ２，１
ｃ＝・・・の間隔寸法！、はそれぞれ等しく設定すると
共に、検査線１ｂの各線１ｂｏ、１ｂ＋、ｌｂ２、ｌｂ
、・・・の間隔１２は！１とは興なる間隔寸法になるよ
うに設定しである１例えばｗ＝０．１５ｍｍ、ｉ＝０．
１０ｍｍ、１ｚ＝０．１６２５ｍｍに設定しである。ま
た検査線１ａの各線１ａｏ。
１ ａｔ、 １ ａ２＋ １ ミニ−１検査線１ｂの各
線１ｂ。
１ ｂ８．１ ｂ２．１ ｂｓ・＝、検査線１ｃの各線
ＩＣｏ＋ ＩＣＩＩ ＩＣ２１１Ｃ３・・・にはその中
央に位置するものに「Ｏｊの符号を付すると共にその両
側のものに外側へ順番に「１」、「２」、「３」・・・
の符号が付しである。そして多層プリント配線板Ａを作
成するにあたって、回路層２ａ、２ｂ、２Ｃの積層の位
置合わせが正確におこなわれていれば、符号「０」を付
した線１ａｏと線１ｂ０と線ＩＣｏが一直線上に合致す
るように、検査線１ａ。
１ｂを回路層２ａ、２ｂに配置して設けるようにしであ
る。この実施例にあっては、検査線１ａと検査線１ｂと
を既述したように測定することによって回路層２ａと回
路層２ｂの相互の位置ずれを検査することができ、また
検査線１ｂと検査線ＩＣとを既述したように測定するこ
とによって回路層２ｂと回路層２ｃの相互の位置ずれを
検査することができる。The present invention will be explained in detail below with reference to Examples. The multilayer printed wiring board A uses, for example, a metal foil-clad laminate such as a copper-clad epoxy resin laminate, and etches the metal foil of this laminate to form a circuit 3, thereby forming circuit layers 2a, 2b, etc.・This circuit board is made by stacking the plurality of circuit boards via a bonding prepreg 1 and applying heat and pressure to perform lamination molding. Each circuit layer 2a, 2b... has an inspection line 1a,
lb... is provided. These inspection lines 1a, lb...
can be formed by etching a part of the metal foil in areas other than the circuit 3 when etching the metal foil to form the circuit 3. The inspection lines 1a, 1b, . . . are formed of a plurality of lines, such as scale lines, arranged in parallel at equal intervals. FIG. 1 shows an embodiment of the present invention, showing a test line 1a and a test line 1b on two circuit layers 2a and 2b, respectively.
are provided, and each inspection line la, lb is connected to each line 1ao, 1a+, 1a211 a s"' of inspection line 1a and inspection line 1b.
Each line 1b0 1b1b2. lb, . these lines 1
ao, 1 a+, 1az+1a co・-, 1be
, 1 bl+ 1 b2+ 1
The width W of bs- is set equally, and each line 1 an, 1 al, 1 a2+ 1 of the inspection line 1a
Miko... spacing dimensions! , and each line 1b of the inspection line 1b
, lbl, 1b2, 1bs... are set to have different interval dimensions from the interval 12, for example w=0.
．． 15mm + f + = 0, 10mm
−1t=0, set to 1625 mm. Also, each line 1ao of the inspection line 1a. 1 al, 1 a2.1 each line 1b of a code and inspection line 1b. , 1 bl, 1 bx, 1 bs..., the one located in the center is marked "0", and the ones on both sides are marked "1", "2", "3" outward in order. ...
The symbol is attached. When creating the multilayer printed wiring board A, if the lamination of the circuit layers 2a and 2b is accurately aligned, the line 1ao marked with the symbol "0" and the line 1b will align in a straight line. In this way, the inspection lines 1a and lb are arranged and provided on the circuit layers 2a and 2b. In addition, the inspection lines 1a and lb are located at − locations in the X direction,
The circuit layer 2a is provided at several locations in the Y direction perpendicular to the X direction. 2b in the X direction and the Y direction (see section 2 and FIG. 3). In FIG. 2, a multilayer printed wiring board A is created by laminating a circuit layer 2b on top of a circuit layer 2a of two circuit layers 2a and 2b formed by providing circuits 3, 3, and so on. In this case, an opening 8 is provided in the upper circuit layer 2b so that a part of the lower circuit layer 2a is exposed. In this device, an inspection line 1a is provided on the circuit layer 2a inside the opening 8, and an inspection line lb is provided on the circuit layer 2b at the edge of the opening 8. Therefore, with this device, each of the inspection lines 1a and lb exposed on the surface can be directly visually observed for inspection. Further, when the lower circuit layer 2a is completely covered by the upper circuit layer 2b and the lower circuit layer 2a is not exposed as shown in FIG. 3, the inspection line 1a formed on the lower circuit layer 2a is not visible. Sometimes you can't see it. Therefore, in this case, the inspection line 1a is detected by X-ray transmission. 1b will be detected and tested. Thus, the circuit layer 2a of the multilayer printed wiring board A. By measuring the inspection lines 1a and lb provided on the circuit layer 2a and 2b,
2b, each line 1 ao, 1 a l+ 1 a2+ 1 of inspection line 1a
a3... and each line 1 bo, 1 bl of inspection line 1b
, 1 b2. 1 Compare the positions of bx...
- This can be done by measuring a line that coincides with a straight line using a magnifying glass such as a microscope. That is, if the line 1ao with the code "0" of the inspection line 1a and the line 1bo with the code "0" of the inspection line 1b match in a straight line as shown in FIG. 1(a), the circuit layers 2a and 2b The alignment of the stacks is accurate. In addition, a line 1aa with the code "0" of the inspection line 1a and a line 1bo with the code "0" of the inspection line 1b.
If they are not aligned in a straight line, it means that there is a misalignment in the laminated position of the circuit layers 2a and 2b. If the line 1an with the code “4” of the line 1a and the line 1bs with the code r 3 J of the inspection line 1b match on a straight line,
L, -L2= (wX4+7+X4)-(WX3+/2
x3) = 0.0625 mm, and for example, as shown in Fig. 1 (
If the line 1a with the code “3” of the inspection line 1a and the line 1b2 with the code “2” of the inspection line 1b match on a straight line as shown in C), Ll-L4= (wX3+/.X3) -(Wx2+7zX2)=0.125mm. Therefore, each line 1ao, 1a+1 a2 . of the inspection line 1a.
1 each line 1b,, 1b+, lb of a2・- and inspection line 1b
By measuring the line that coincides with the - straight line of z, lb...
and the size of misalignment can be inspected. If you create a verification table of misalignment dimensions calculated for matching inspection lines 1a and lb in advance, you can immediately know the dimension of misalignment and also check whether the misalignment is outside the allowable range or not. This determination can also be made immediately. In the embodiment of FIG. 4, a test 1111a, a test line 1b, and a test line 1c are provided on the three circuit layers 2a and 2b2c, respectively, and each lit 1 b o of each test line 1b. 1b+, lbz, lbs..., each line of inspection line 1a 1 ao, 1 a,, 1 a2+ 1 a3"・
and each 1i1 co of the inspection line 1c, I CI+ I C
2, 1c, . . . are arranged so as to face each other in parallel and close to each other. These lines 1as, 1at, 1a
t, 1 as-, 1ao+ lbl, 1b 2
, 1 b Co = , I Co, 1 c
The widths W of l+ I C2 and I Cz- are set equal, and each line 1 aQ of the inspection line 1a
, 1 at, 1 a2+ 1 a3... spacing dimensions! 1 and inspection line 1c, each line ice, ICI, IC2, 1
c=... spacing dimension! , are set equally, and each line 1bo, 1b+, lb2, lb of the inspection line 1b
,... the interval 12 is! 1 is set to have a different interval dimension.1 For example, w = 0.15 mm, i = 0.
It is set to 10 mm and 1z=0.1625 mm. Also, each line 1ao of the inspection line 1a. 1 at, 1 a2+ 1 Each line 1b of the mini-1 inspection line 1b. 1 b8.1 b2.1 bs・=, each line ICo+ICII IC211C3 of the inspection line 1c, the one located in the center is marked with “Oj”, and the ones on both sides are marked with “1” outward in order. ”, “2”, “3”...
The symbol is attached. When creating the multilayer printed wiring board A, if the lamination of the circuit layers 2a, 2b, and 2C is accurately aligned, the line 1ao with the symbol "0", the line 1b0, and the line ICo are in a straight line. Inspection line 1a so as to match. 1b are arranged and provided on circuit layers 2a and 2b. In this embodiment, the mutual positional deviation between the circuit layer 2a and the circuit layer 2b can be inspected by measuring the inspection line 1a and the inspection line 1b as described above. By measuring the inspection line IC as described above, it is possible to inspect the mutual positional deviation between the circuit layer 2b and the circuit layer 2c.
上述のように本発明にあっては、等間隔で平行に配列さ
れる複数本の検査線を各回路層にそれぞれ互いに平行に
対向させて設けると共に、隣り合う一方の検査線の間隔
寸法と他方の検査線の間隔寸法とを異なる寸法に設定し
、各回路層の一方の検査線と他方の検査線の合致する線
を測定するようにしたので、検査線の合致する線を測定
することによってノギスのバーニヤ目盛りによる測長と
同じ原理で各回路層のずれの寸法を知ることができるも
のであり、測長機などを用いるような必要なく簡易な手
段で容易に回路層の位置ずれの検査をおこなうことがで
きるものである。As described above, in the present invention, a plurality of inspection lines arranged parallel to each other at equal intervals are provided in each circuit layer so as to face each other in parallel, and the distance between one adjacent inspection line and the other inspection line is By setting the interval dimension of the inspection lines to different dimensions and measuring the matching line between one inspection line and the other inspection line of each circuit layer, by measuring the matching line of the inspection lines, It is possible to determine the size of misalignment of each circuit layer using the same principle as length measurement using the vernier scale of calipers, and it is possible to easily inspect misalignment of circuit layers with a simple method without the need for using a length measuring machine. It is possible to do this.
第１図（ａ ）（ｂ Ｈｃ ）は本発明の一実施例にお
ける検査線の配置を示す平面図、第２図及び第３図はそ
れぞれ同上の多層プリント配線板の一部の平面図と一部
を破断した平面図、第４図は同上の他の実施例における
検査線の配置を示す平面図である。
ｌａ、ｌｂ・・・は検査線、２ａ、２ｂ・・・は回路層
、３は回路、Ａは多層プリント配線板である。FIGS. 1(a) and (bHc) are plan views showing the arrangement of inspection lines in one embodiment of the present invention, and FIGS. 2 and 3 are plan views of a part of the same multilayer printed wiring board, respectively. FIG. 4 is a plan view showing the arrangement of inspection lines in another embodiment of the same. la, lb... are inspection lines, 2a, 2b... are circuit layers, 3 is a circuit, and A is a multilayer printed wiring board.
Claims (1)
線板において、等間隔で平行に配列される複数本の検査
線を各回路層にそれぞれ互いに平行に対向させて設ける
と共に、隣り合う一方の検査線の間隔寸法と他方の検査
線の間隔寸法とを異なる寸法に設定し、各回路層の一方
の検査線と他方の検査線の合致する線を測定することを
特徴とする多層プリント配線板の層間ずれ検査方法。(1) In a multilayer printed wiring board formed by providing circuits in multiple layers, a plurality of inspection lines arranged parallel to each other at equal intervals are provided on each circuit layer in parallel and facing each other, and one of the adjacent The multilayer printed wiring is characterized in that the interval dimension of the inspection line and the interval dimension of the other inspection line are set to different dimensions, and the matching line between one inspection line and the other inspection line of each circuit layer is measured. Inspection method for interlayer deviation of boards.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2245333A JPH0777298B2 (en) | 1990-09-14 | 1990-09-14 | Interlayer deviation inspection method for multilayer printed wiring boards |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2245333A JPH0777298B2 (en) | 1990-09-14 | 1990-09-14 | Interlayer deviation inspection method for multilayer printed wiring boards |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04122842A true JPH04122842A (en) | 1992-04-23 |
| JPH0777298B2 JPH0777298B2 (en) | 1995-08-16 |
Family
ID=17132107
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2245333A Expired - Lifetime JPH0777298B2 (en) | 1990-09-14 | 1990-09-14 | Interlayer deviation inspection method for multilayer printed wiring boards |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0777298B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP4068913A1 (en) * | 2021-03-31 | 2022-10-05 | HENSOLDT Sensors GmbH | Structure produced by means of additive manufacturing and method for producing the same |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0232594A (en) * | 1988-07-22 | 1990-02-02 | Mitsubishi Electric Corp | Laminate type printed wiring board |
-
1990
- 1990-09-14 JP JP2245333A patent/JPH0777298B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0232594A (en) * | 1988-07-22 | 1990-02-02 | Mitsubishi Electric Corp | Laminate type printed wiring board |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP4068913A1 (en) * | 2021-03-31 | 2022-10-05 | HENSOLDT Sensors GmbH | Structure produced by means of additive manufacturing and method for producing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0777298B2 (en) | 1995-08-16 |
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