JPH03170006A - Testing method for multilayer printed wiring board - Google Patents
Testing method for multilayer printed wiring boardInfo
- Publication number
- JPH03170006A JPH03170006A JP30984589A JP30984589A JPH03170006A JP H03170006 A JPH03170006 A JP H03170006A JP 30984589 A JP30984589 A JP 30984589A JP 30984589 A JP30984589 A JP 30984589A JP H03170006 A JPH03170006 A JP H03170006A
- Authority
- JP
- Japan
- Prior art keywords
- printed wiring
- wiring board
- multilayer printed
- marks
- deviation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000012360 testing method Methods 0.000 title claims description 5
- 238000005259 measurement Methods 0.000 claims description 14
- 238000000034 method Methods 0.000 claims description 11
- 239000011229 interlayer Substances 0.000 claims description 7
- 238000010030 laminating Methods 0.000 claims description 2
- 238000010998 test method Methods 0.000 claims description 2
- 238000003475 lamination Methods 0.000 description 3
- 239000010410 layer Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0266—Marks, test patterns or identification means
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4638—Aligning and fixing the circuit boards before lamination; Detecting or measuring the misalignment after lamination; Aligning external circuit patterns or via connections relative to internal circuits
Landscapes
- Length-Measuring Devices Using Wave Or Particle Radiation (AREA)
Abstract
Description
【発明の詳細な説明】
（産業」二の利用分野）
本発明は、多層プリント配線板の試験方法、特に積層接
着時の層間ずれ量を求めるのに適した多層プリント配線
板の試験方法に関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Application in Industry) The present invention relates to a method for testing multilayer printed wiring boards, and particularly to a testing method for multilayer printed wiring boards suitable for determining the amount of interlayer deviation during lamination and bonding.
（従来技術）
従来の多層プリント配線板の試験方法として、特開昭５
６−３０７９３号公報に示されるように多層プリント配
線板に位置ずれ検出用パターンを設け、該銅箭パターン
間の静電容量を測定することにより層間位置ずれ竜を検
出する方法が知られているが、この方法ではずれの方向
がわからなかった。また、特開昭６２−８６７９５号に
示された方法では、ずれ量と方向はわかるが寸法測定用
マークを座ぐり出さねばならず手間がかかった。(Prior art) As a conventional test method for multilayer printed wiring boards,
As shown in Japanese Patent No. 6-30793, there is a known method of detecting interlayer misalignment by providing misalignment detection patterns on a multilayer printed wiring board and measuring the capacitance between the copper wire patterns. However, with this method, the direction of the deviation could not be determined. Further, in the method disclosed in Japanese Patent Application Laid-open No. 62-86795, although the amount and direction of deviation can be determined, it is necessary to counterbore the dimension measurement mark, which is time-consuming.
（発明が解決しようとする課題）
本発明は、多層プリント配線板の層間ずれ量を座ぐりな
しで定量的に得られる多層プリント配線板の試験方法を
提供するものである。(Problems to be Solved by the Invention) The present invention provides a method for testing a multilayer printed wiring board that can quantitatively determine the amount of interlayer misalignment of the multilayer printed wiring board without counterboring.
《課題を解決するための手段｝
本発門は（ａ）各プリント配線板の同一位置にそれぞれ
形状または大きさの異なる寸法測定用のマークを設ける
工程と、（ｂ）マークの設けられたプリント配線板を積
層接着する工程と、（ｃ）プリント基板はそのままでＸ
線投影機により該マークを一括投影寸法測定を行い各プ
リント配線板の層間ずれ量を求める工程とを有すること
を特徴とするものである。《Means for solving the problem》 The present invention consists of (a) the process of providing dimensional measurement marks of different shapes or sizes at the same position on each printed wiring board; and (b) the process of placing marks on the printed circuit board on which the marks are provided. (c) The process of laminating and bonding the wiring boards, and (c)
This method is characterized by comprising the step of projecting the marks all at once using a line projector and measuring the dimensions to determine the amount of interlayer misalignment of each printed wiring board.
《作用）
本発門の方法においては、各プリント配線板の寸法測定
用マークを、Ｘ線投影機によって一括投影寸法測定する
ことにより、設定基準層に対する各プリント配線板のず
れ量および方向を座ぐりなしで検出できるようになる。<<Operation>> In the method of this invention, the amount and direction of deviation of each printed wiring board with respect to the set reference layer can be calculated by projecting the dimension measurement marks on each printed wiring board at once using an X-ray projector. It becomes possible to detect without drilling.
（実施例の説Ｉｖ１）
以下、本発明の一実施例について図面を用いて説門する
。(Description of Embodiment Iv1) Hereinafter, one embodiment of the present invention will be explained using the drawings.
第１図は本実施例で川いる積層接着前のプリント配線板
２を示し、Ｘ−Ｙは寸法測定の座標系、１は寸法測定用
マークの配置を表わしている。第２図（Ａ）〜（Ｆ）は
本実施例で用いる寸法測定用マークを表わしており、６
枚のプリント配線板にそれぞれ形状の異なる寸法測定用
マーク３〜８を設ける。これら６枚のプリント配線板を
積層接着し多層プリント配線板を作製する。この多層プ
リント配線板をＸ線で投影したときの寸法測定用マーク
の一例を第３図に示す。このようにして得られた合戊パ
ターンを用い基準層を設定し、それに対してのずれ量９
，１０を寸法測定する。FIG. 1 shows the printed wiring board 2 of this embodiment before lamination and adhesion, where X-Y represents the coordinate system for dimension measurement, and 1 represents the arrangement of dimension measurement marks. FIGS. 2(A) to 2(F) show the dimension measurement marks used in this example.
Dimensional measurement marks 3 to 8 having different shapes are provided on each printed wiring board. These six printed wiring boards are laminated and bonded to produce a multilayer printed wiring board. FIG. 3 shows an example of a mark for dimension measurement when this multilayer printed wiring board is projected with X-rays. Using the composite pattern obtained in this way, a reference layer is set, and the amount of deviation from it is 9.
, 10 are measured.
本実施例により、多層プリント配線板の層間ずれはを座
ぐりなしで定量的にしかも精度よく求めることができる
。According to this embodiment, the interlayer misalignment of a multilayer printed wiring board can be determined quantitatively and accurately without counterbore.
《発明の効果》
以上述べたように本発明によれば、基準のプリント配線
板に対して各プリント配線板のずれ量と方向を座ぐりな
しで容易にかつ定量的に評価できるという効果がある。<<Effects of the Invention>> As described above, according to the present invention, there is an effect that the amount and direction of deviation of each printed wiring board with respect to a reference printed wiring board can be easily and quantitatively evaluated without counterboring. .
第１図は本発明の実施例に係る寸法測定用マークの位置
を示す斜視図、第２図（Ａ）〜（Ｆ）は本発叩の実施例
に用いられる寸法測定用マークの平面図、第３図は本発
明の実施例に係る多層プリント配線板の寸法測定用パタ
ーンをＸ線にて投影した平面図である。
符号の説明
１・・・寸法測定用パターン位置
２・・・積層接着前プリント配線板
３・・・寸法測定用マーク
４・・・同上
５・・・１言ＬＬ
６・・・同］二
７・・・同−１二
８・・・同」二
９・・・Ｙ方向ずれ量
１０・・・Ｘ方向ずれ量FIG. 1 is a perspective view showing the position of the dimension measurement mark according to the embodiment of the present invention, and FIGS. 2(A) to (F) are plan views of the dimension measurement mark used in the embodiment of the present punching. FIG. 3 is a plan view of a dimension measurement pattern of a multilayer printed wiring board according to an embodiment of the present invention projected by X-rays. Explanation of symbols 1...Dimension measurement pattern position 2...Printed wiring board before lamination and adhesion 3...Dimension measurement mark 4...Same as above 5...1 word LL 6...Same] 27 ...Same-128...Same'29...Y-direction deviation amount 10...X-direction deviation amount
Claims (1)
ト配線板の各プリント配線板の層間ずれ量を求める試験
方法において、 （ａ）前記各プリント配線板の同一位置にそれぞれ形状
または大きさの異なる寸法測定用のマークを設ける工程
と、 （ｂ）前記マークの設けられたプリント配線板を積層接
着する工程と、 （ｃ）前記プリント配線板はそのままでＸ線投影機によ
り前記マークを一括投影寸法測定を行い各プリント配線
板の層間ずれ量を求める工程とを有することを特徴とす
る多層プリント配線板の試験方法。[Claims] 1. In a test method for determining the amount of interlayer deviation of each printed wiring board of a multilayer printed wiring board in which a plurality of printed wiring boards are laminated and bonded, (b) laminating and bonding the printed wiring boards with the marks provided thereon; and (c) applying the printed wiring boards as they are to an X-ray projector. A method for testing a multilayer printed wiring board, comprising the step of performing a collective projection dimension measurement of the marks to determine the amount of interlayer misalignment of each printed wiring board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30984589A JPH03170006A (en) | 1989-11-29 | 1989-11-29 | Testing method for multilayer printed wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30984589A JPH03170006A (en) | 1989-11-29 | 1989-11-29 | Testing method for multilayer printed wiring board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03170006A true JPH03170006A (en) | 1991-07-23 |
Family
ID=17997976
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP30984589A Pending JPH03170006A (en) | 1989-11-29 | 1989-11-29 | Testing method for multilayer printed wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03170006A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102291949A (en) * | 2010-06-18 | 2011-12-21 | 富葵精密组件(深圳)有限公司 | Manufacturing method of multi-layer circuit board |
-
1989
- 1989-11-29 JP JP30984589A patent/JPH03170006A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102291949A (en) * | 2010-06-18 | 2011-12-21 | 富葵精密组件(深圳)有限公司 | Manufacturing method of multi-layer circuit board |
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